2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/isa-rev.h>
23 * The following macros are especially useful for __asm__
30 #define STR(x) __STR(x)
40 #define _ULCAST_ (unsigned long)
41 #define _U64CAST_ (u64)
45 * Coprocessor 0 register names
49 #define CP0_ENTRYLO0 $2
50 #define CP0_ENTRYLO1 $3
52 #define CP0_GLOBALNUMBER $3, 1
53 #define CP0_CONTEXT $4
54 #define CP0_PAGEMASK $5
55 #define CP0_PAGEGRAIN $5, 1
56 #define CP0_SEGCTL0 $5, 2
57 #define CP0_SEGCTL1 $5, 3
58 #define CP0_SEGCTL2 $5, 4
62 #define CP0_BADVADDR $8
63 #define CP0_BADINSTR $8, 1
65 #define CP0_ENTRYHI $10
66 #define CP0_GUESTCTL1 $10, 4
67 #define CP0_GUESTCTL2 $10, 5
68 #define CP0_GUESTCTL3 $10, 6
69 #define CP0_COMPARE $11
70 #define CP0_GUESTCTL0EXT $11, 4
71 #define CP0_STATUS $12
72 #define CP0_GUESTCTL0 $12, 6
73 #define CP0_GTOFFSET $12, 7
77 #define CP0_EBASE $15, 1
78 #define CP0_CMGCRBASE $15, 3
79 #define CP0_CONFIG $16
80 #define CP0_CONFIG3 $16, 3
81 #define CP0_CONFIG5 $16, 5
82 #define CP0_CONFIG6 $16, 6
83 #define CP0_LLADDR $17
84 #define CP0_WATCHLO $18
85 #define CP0_WATCHHI $19
86 #define CP0_XCONTEXT $20
87 #define CP0_FRAMEMASK $21
88 #define CP0_DIAGNOSTIC $22
91 #define CP0_PERFORMANCE $25
93 #define CP0_CACHEERR $27
96 #define CP0_ERROREPC $30
97 #define CP0_DESAVE $31
100 * R4640/R4650 cp0 register names. These registers are listed
101 * here only for completeness; without MMU these CPUs are not useable
102 * by Linux. A future ELKS port might take make Linux run on them
106 #define CP0_IBOUND $1
108 #define CP0_DBOUND $3
110 #define CP0_IWATCH $18
111 #define CP0_DWATCH $19
114 * Coprocessor 0 Set 1 register names
116 #define CP0_S1_DERRADDR0 $26
117 #define CP0_S1_DERRADDR1 $27
118 #define CP0_S1_INTCONTROL $20
121 * Coprocessor 0 Set 2 register names
123 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
126 * Coprocessor 0 Set 3 register names
128 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
133 #define CP0_TX39_CACHE $7
136 /* Generic EntryLo bit definitions */
137 #define ENTRYLO_G (_ULCAST_(1) << 0)
138 #define ENTRYLO_V (_ULCAST_(1) << 1)
139 #define ENTRYLO_D (_ULCAST_(1) << 2)
140 #define ENTRYLO_C_SHIFT 3
141 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
143 /* R3000 EntryLo bit definitions */
144 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
145 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
146 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
147 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
149 /* MIPS32/64 EntryLo bit definitions */
150 #define MIPS_ENTRYLO_PFN_SHIFT 6
151 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
155 * MIPSr6+ GlobalNumber register definitions
157 #define MIPS_GLOBALNUMBER_VP_SHF 0
158 #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
159 #define MIPS_GLOBALNUMBER_CORE_SHF 8
160 #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
161 #define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
162 #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
165 * Values for PageMask register
167 #ifdef CONFIG_CPU_VR41XX
169 /* Why doesn't stupidity hurt ... */
171 #define PM_1K 0x00000000
172 #define PM_4K 0x00001800
173 #define PM_16K 0x00007800
174 #define PM_64K 0x0001f800
175 #define PM_256K 0x0007f800
179 #define PM_4K 0x00000000
180 #define PM_8K 0x00002000
181 #define PM_16K 0x00006000
182 #define PM_32K 0x0000e000
183 #define PM_64K 0x0001e000
184 #define PM_128K 0x0003e000
185 #define PM_256K 0x0007e000
186 #define PM_512K 0x000fe000
187 #define PM_1M 0x001fe000
188 #define PM_2M 0x003fe000
189 #define PM_4M 0x007fe000
190 #define PM_8M 0x00ffe000
191 #define PM_16M 0x01ffe000
192 #define PM_32M 0x03ffe000
193 #define PM_64M 0x07ffe000
194 #define PM_256M 0x1fffe000
195 #define PM_1G 0x7fffe000
200 * Default page size for a given kernel configuration
202 #ifdef CONFIG_PAGE_SIZE_4KB
203 #define PM_DEFAULT_MASK PM_4K
204 #elif defined(CONFIG_PAGE_SIZE_8KB)
205 #define PM_DEFAULT_MASK PM_8K
206 #elif defined(CONFIG_PAGE_SIZE_16KB)
207 #define PM_DEFAULT_MASK PM_16K
208 #elif defined(CONFIG_PAGE_SIZE_32KB)
209 #define PM_DEFAULT_MASK PM_32K
210 #elif defined(CONFIG_PAGE_SIZE_64KB)
211 #define PM_DEFAULT_MASK PM_64K
213 #error Bad page size configuration!
217 * Default huge tlb size for a given kernel configuration
219 #ifdef CONFIG_PAGE_SIZE_4KB
220 #define PM_HUGE_MASK PM_1M
221 #elif defined(CONFIG_PAGE_SIZE_8KB)
222 #define PM_HUGE_MASK PM_4M
223 #elif defined(CONFIG_PAGE_SIZE_16KB)
224 #define PM_HUGE_MASK PM_16M
225 #elif defined(CONFIG_PAGE_SIZE_32KB)
226 #define PM_HUGE_MASK PM_64M
227 #elif defined(CONFIG_PAGE_SIZE_64KB)
228 #define PM_HUGE_MASK PM_256M
229 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
230 #error Bad page size configuration for hugetlbfs!
234 * Wired register bits
236 #define MIPSR6_WIRED_LIMIT_SHIFT 16
237 #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
238 #define MIPSR6_WIRED_WIRED_SHIFT 0
239 #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
242 * Values used for computation of new tlb entries
257 #define PG_RIE (_ULCAST_(1) << 31)
258 #define PG_XIE (_ULCAST_(1) << 30)
259 #define PG_ELPA (_ULCAST_(1) << 29)
260 #define PG_ESP (_ULCAST_(1) << 28)
261 #define PG_IEC (_ULCAST_(1) << 27)
263 /* MIPS32/64 EntryHI bit definitions */
264 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
265 #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
266 #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
269 * R4x00 interrupt enable / cause bits
271 #define IE_SW0 (_ULCAST_(1) << 8)
272 #define IE_SW1 (_ULCAST_(1) << 9)
273 #define IE_IRQ0 (_ULCAST_(1) << 10)
274 #define IE_IRQ1 (_ULCAST_(1) << 11)
275 #define IE_IRQ2 (_ULCAST_(1) << 12)
276 #define IE_IRQ3 (_ULCAST_(1) << 13)
277 #define IE_IRQ4 (_ULCAST_(1) << 14)
278 #define IE_IRQ5 (_ULCAST_(1) << 15)
281 * R4x00 interrupt cause bits
283 #define C_SW0 (_ULCAST_(1) << 8)
284 #define C_SW1 (_ULCAST_(1) << 9)
285 #define C_IRQ0 (_ULCAST_(1) << 10)
286 #define C_IRQ1 (_ULCAST_(1) << 11)
287 #define C_IRQ2 (_ULCAST_(1) << 12)
288 #define C_IRQ3 (_ULCAST_(1) << 13)
289 #define C_IRQ4 (_ULCAST_(1) << 14)
290 #define C_IRQ5 (_ULCAST_(1) << 15)
293 * Bitfields in the R4xx0 cp0 status register
295 #define ST0_IE 0x00000001
296 #define ST0_EXL 0x00000002
297 #define ST0_ERL 0x00000004
298 #define ST0_KSU 0x00000018
299 # define KSU_USER 0x00000010
300 # define KSU_SUPERVISOR 0x00000008
301 # define KSU_KERNEL 0x00000000
302 #define ST0_UX 0x00000020
303 #define ST0_SX 0x00000040
304 #define ST0_KX 0x00000080
305 #define ST0_DE 0x00010000
306 #define ST0_CE 0x00020000
309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
310 * cacheops in userspace. This bit exists only on RM7000 and RM9000
313 #define ST0_CO 0x08000000
316 * Bitfields in the R[23]000 cp0 status register.
318 #define ST0_IEC 0x00000001
319 #define ST0_KUC 0x00000002
320 #define ST0_IEP 0x00000004
321 #define ST0_KUP 0x00000008
322 #define ST0_IEO 0x00000010
323 #define ST0_KUO 0x00000020
324 /* bits 6 & 7 are reserved on R[23]000 */
325 #define ST0_ISC 0x00010000
326 #define ST0_SWC 0x00020000
327 #define ST0_CM 0x00080000
330 * Bits specific to the R4640/R4650
332 #define ST0_UM (_ULCAST_(1) << 4)
333 #define ST0_IL (_ULCAST_(1) << 23)
334 #define ST0_DL (_ULCAST_(1) << 24)
337 * Enable the MIPS MDMX and DSP ASEs
339 #define ST0_MX 0x01000000
342 * Status register bits available in all MIPS CPUs.
344 #define ST0_IM 0x0000ff00
345 #define STATUSB_IP0 8
346 #define STATUSF_IP0 (_ULCAST_(1) << 8)
347 #define STATUSB_IP1 9
348 #define STATUSF_IP1 (_ULCAST_(1) << 9)
349 #define STATUSB_IP2 10
350 #define STATUSF_IP2 (_ULCAST_(1) << 10)
351 #define STATUSB_IP3 11
352 #define STATUSF_IP3 (_ULCAST_(1) << 11)
353 #define STATUSB_IP4 12
354 #define STATUSF_IP4 (_ULCAST_(1) << 12)
355 #define STATUSB_IP5 13
356 #define STATUSF_IP5 (_ULCAST_(1) << 13)
357 #define STATUSB_IP6 14
358 #define STATUSF_IP6 (_ULCAST_(1) << 14)
359 #define STATUSB_IP7 15
360 #define STATUSF_IP7 (_ULCAST_(1) << 15)
361 #define STATUSB_IP8 0
362 #define STATUSF_IP8 (_ULCAST_(1) << 0)
363 #define STATUSB_IP9 1
364 #define STATUSF_IP9 (_ULCAST_(1) << 1)
365 #define STATUSB_IP10 2
366 #define STATUSF_IP10 (_ULCAST_(1) << 2)
367 #define STATUSB_IP11 3
368 #define STATUSF_IP11 (_ULCAST_(1) << 3)
369 #define STATUSB_IP12 4
370 #define STATUSF_IP12 (_ULCAST_(1) << 4)
371 #define STATUSB_IP13 5
372 #define STATUSF_IP13 (_ULCAST_(1) << 5)
373 #define STATUSB_IP14 6
374 #define STATUSF_IP14 (_ULCAST_(1) << 6)
375 #define STATUSB_IP15 7
376 #define STATUSF_IP15 (_ULCAST_(1) << 7)
377 #define ST0_CH 0x00040000
378 #define ST0_NMI 0x00080000
379 #define ST0_SR 0x00100000
380 #define ST0_TS 0x00200000
381 #define ST0_BEV 0x00400000
382 #define ST0_RE 0x02000000
383 #define ST0_FR 0x04000000
384 #define ST0_CU 0xf0000000
385 #define ST0_CU0 0x10000000
386 #define ST0_CU1 0x20000000
387 #define ST0_CU2 0x40000000
388 #define ST0_CU3 0x80000000
389 #define ST0_XX 0x80000000 /* MIPS IV naming */
392 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
394 #define INTCTLB_IPFDC 23
395 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
396 #define INTCTLB_IPPCI 26
397 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
398 #define INTCTLB_IPTI 29
399 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
402 * Bitfields and bit numbers in the coprocessor 0 cause register.
404 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
406 #define CAUSEB_EXCCODE 2
407 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
409 #define CAUSEF_IP (_ULCAST_(255) << 8)
411 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
413 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
414 #define CAUSEB_IP2 10
415 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
416 #define CAUSEB_IP3 11
417 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
418 #define CAUSEB_IP4 12
419 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
420 #define CAUSEB_IP5 13
421 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
422 #define CAUSEB_IP6 14
423 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
424 #define CAUSEB_IP7 15
425 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
426 #define CAUSEB_FDCI 21
427 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
429 #define CAUSEF_WP (_ULCAST_(1) << 22)
431 #define CAUSEF_IV (_ULCAST_(1) << 23)
432 #define CAUSEB_PCI 26
433 #define CAUSEF_PCI (_ULCAST_(1) << 26)
435 #define CAUSEF_DC (_ULCAST_(1) << 27)
437 #define CAUSEF_CE (_ULCAST_(3) << 28)
439 #define CAUSEF_TI (_ULCAST_(1) << 30)
441 #define CAUSEF_BD (_ULCAST_(1) << 31)
444 * Cause.ExcCode trap codes.
446 #define EXCCODE_INT 0 /* Interrupt pending */
447 #define EXCCODE_MOD 1 /* TLB modified fault */
448 #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
449 #define EXCCODE_TLBS 3 /* TLB miss on a store */
450 #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
451 #define EXCCODE_ADES 5 /* Address error on a store */
452 #define EXCCODE_IBE 6 /* Bus error on an ifetch */
453 #define EXCCODE_DBE 7 /* Bus error on a load or store */
454 #define EXCCODE_SYS 8 /* System call */
455 #define EXCCODE_BP 9 /* Breakpoint */
456 #define EXCCODE_RI 10 /* Reserved instruction exception */
457 #define EXCCODE_CPU 11 /* Coprocessor unusable */
458 #define EXCCODE_OV 12 /* Arithmetic overflow */
459 #define EXCCODE_TR 13 /* Trap instruction */
460 #define EXCCODE_MSAFPE 14 /* MSA floating point exception */
461 #define EXCCODE_FPE 15 /* Floating point exception */
462 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
463 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
464 #define EXCCODE_MSADIS 21 /* MSA disabled exception */
465 #define EXCCODE_MDMX 22 /* MDMX unusable exception */
466 #define EXCCODE_WATCH 23 /* Watch address reference */
467 #define EXCCODE_MCHECK 24 /* Machine check */
468 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
469 #define EXCCODE_DSPDIS 26 /* DSP disabled exception */
470 #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
472 /* Implementation specific trap codes used by MIPS cores */
473 #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
476 * Bits in the coprocessor 0 config register.
479 #define CONF_CM_CACHABLE_NO_WA 0
480 #define CONF_CM_CACHABLE_WA 1
481 #define CONF_CM_UNCACHED 2
482 #define CONF_CM_CACHABLE_NONCOHERENT 3
483 #define CONF_CM_CACHABLE_CE 4
484 #define CONF_CM_CACHABLE_COW 5
485 #define CONF_CM_CACHABLE_CUW 6
486 #define CONF_CM_CACHABLE_ACCELERATED 7
487 #define CONF_CM_CMASK 7
488 #define CONF_BE (_ULCAST_(1) << 15)
490 /* Bits common to various processors. */
491 #define CONF_CU (_ULCAST_(1) << 3)
492 #define CONF_DB (_ULCAST_(1) << 4)
493 #define CONF_IB (_ULCAST_(1) << 5)
494 #define CONF_DC (_ULCAST_(7) << 6)
495 #define CONF_IC (_ULCAST_(7) << 9)
496 #define CONF_EB (_ULCAST_(1) << 13)
497 #define CONF_EM (_ULCAST_(1) << 14)
498 #define CONF_SM (_ULCAST_(1) << 16)
499 #define CONF_SC (_ULCAST_(1) << 17)
500 #define CONF_EW (_ULCAST_(3) << 18)
501 #define CONF_EP (_ULCAST_(15)<< 24)
502 #define CONF_EC (_ULCAST_(7) << 28)
503 #define CONF_CM (_ULCAST_(1) << 31)
505 /* Bits specific to the R4xx0. */
506 #define R4K_CONF_SW (_ULCAST_(1) << 20)
507 #define R4K_CONF_SS (_ULCAST_(1) << 21)
508 #define R4K_CONF_SB (_ULCAST_(3) << 22)
510 /* Bits specific to the R5000. */
511 #define R5K_CONF_SE (_ULCAST_(1) << 12)
512 #define R5K_CONF_SS (_ULCAST_(3) << 20)
514 /* Bits specific to the RM7000. */
515 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
516 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
517 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
518 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
519 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
520 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
522 /* Bits specific to the R10000. */
523 #define R10K_CONF_DN (_ULCAST_(3) << 3)
524 #define R10K_CONF_CT (_ULCAST_(1) << 5)
525 #define R10K_CONF_PE (_ULCAST_(1) << 6)
526 #define R10K_CONF_PM (_ULCAST_(3) << 7)
527 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
528 #define R10K_CONF_SB (_ULCAST_(1) << 13)
529 #define R10K_CONF_SK (_ULCAST_(1) << 14)
530 #define R10K_CONF_SS (_ULCAST_(7) << 16)
531 #define R10K_CONF_SC (_ULCAST_(7) << 19)
532 #define R10K_CONF_DC (_ULCAST_(7) << 26)
533 #define R10K_CONF_IC (_ULCAST_(7) << 29)
535 /* Bits specific to the VR41xx. */
536 #define VR41_CONF_CS (_ULCAST_(1) << 12)
537 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
538 #define VR41_CONF_BP (_ULCAST_(1) << 16)
539 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
540 #define VR41_CONF_AD (_ULCAST_(1) << 23)
542 /* Bits specific to the R30xx. */
543 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
544 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
545 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
546 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
547 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
548 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
549 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
550 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
551 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
553 /* Bits specific to the TX49. */
554 #define TX49_CONF_DC (_ULCAST_(1) << 16)
555 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
556 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
557 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
559 /* Bits specific to the MIPS32/64 PRA. */
560 #define MIPS_CONF_VI (_ULCAST_(1) << 3)
561 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
562 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
563 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
564 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
565 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
566 #define MIPS_CONF_M (_ULCAST_(1) << 31)
569 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
571 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
572 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
573 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
574 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
575 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
576 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
577 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
578 #define MIPS_CONF1_DA_SHF 7
579 #define MIPS_CONF1_DA_SZ 3
580 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
581 #define MIPS_CONF1_DL_SHF 10
582 #define MIPS_CONF1_DL_SZ 3
583 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
584 #define MIPS_CONF1_DS_SHF 13
585 #define MIPS_CONF1_DS_SZ 3
586 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
587 #define MIPS_CONF1_IA_SHF 16
588 #define MIPS_CONF1_IA_SZ 3
589 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
590 #define MIPS_CONF1_IL_SHF 19
591 #define MIPS_CONF1_IL_SZ 3
592 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
593 #define MIPS_CONF1_IS_SHF 22
594 #define MIPS_CONF1_IS_SZ 3
595 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
596 #define MIPS_CONF1_TLBS_SHIFT (25)
597 #define MIPS_CONF1_TLBS_SIZE (6)
598 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
600 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
601 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
602 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
603 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
604 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
605 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
606 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
607 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
609 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
610 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
611 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
612 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
613 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
614 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
615 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
616 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
617 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
618 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
619 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
620 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
621 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
622 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
623 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
624 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
625 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
626 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
627 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
628 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
629 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
630 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
631 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
632 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
633 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
634 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
635 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
637 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
638 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
639 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
640 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
641 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
642 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
643 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
644 /* bits 10:8 in FTLB-only configurations */
645 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
646 /* bits 12:8 in VTLB-FTLB only configurations */
647 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
648 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
649 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
650 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
651 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
652 #define MIPS_CONF4_KSCREXIST_SHIFT (16)
653 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
654 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
655 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
656 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
657 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
658 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
660 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
661 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
662 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
663 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
664 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
665 #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
666 #define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
667 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
668 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
669 #define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
670 #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
671 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
672 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
673 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
674 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
676 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
677 /* proAptiv FTLB on/off bit */
678 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
679 /* Loongson-3 FTLB on/off bit */
680 #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
681 /* FTLB probability bits */
682 #define MIPS_CONF6_FTLBP_SHIFT (16)
684 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
686 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
688 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
689 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
691 /* Ingenic Config7 bits */
692 #define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
694 /* Config7 Bits specific to MIPS Technologies. */
696 /* Performance counters implemented Per TC */
697 #define MTI_CONF7_PTC (_ULCAST_(1) << 19)
699 /* WatchLo* register definitions */
700 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
702 /* WatchHi* register definitions */
703 #define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
704 #define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
705 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
706 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
707 #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
708 #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
709 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
710 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
711 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
712 #define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
713 #define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
714 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
715 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
717 /* PerfCnt control register definitions */
718 #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
719 #define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
720 #define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
721 #define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
722 #define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
723 #define MIPS_PERFCTRL_EVENT_S 5
724 #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
725 #define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
726 #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
727 #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
728 #define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
729 #define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
730 #define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
731 #define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
732 #define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
734 /* PerfCnt control register MT extensions used by MIPS cores */
735 #define MIPS_PERFCTRL_VPEID_S 16
736 #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
737 #define MIPS_PERFCTRL_TCID_S 22
738 #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
739 #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
740 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
741 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
742 #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
744 /* PerfCnt control register MT extensions used by BMIPS5000 */
745 #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
747 /* PerfCnt control register MT extensions used by Netlogic XLR */
748 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
750 /* MAAR bit definitions */
751 #define MIPS_MAAR_VH (_U64CAST_(1) << 63)
752 #define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
753 #define MIPS_MAAR_ADDR_SHIFT 12
754 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
755 #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
757 /* MAARI bit definitions */
758 #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
760 /* EBase bit definitions */
761 #define MIPS_EBASE_CPUNUM_SHIFT 0
762 #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
763 #define MIPS_EBASE_WG_SHIFT 11
764 #define MIPS_EBASE_WG (_ULCAST_(1) << 11)
765 #define MIPS_EBASE_BASE_SHIFT 12
766 #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
768 /* CMGCRBase bit definitions */
769 #define MIPS_CMGCRB_BASE 11
770 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
772 /* LLAddr bit definitions */
773 #define MIPS_LLADDR_LLB_SHIFT 0
774 #define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
777 * Bits in the MIPS32 Memory Segmentation registers.
779 #define MIPS_SEGCFG_PA_SHIFT 9
780 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
781 #define MIPS_SEGCFG_AM_SHIFT 4
782 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
783 #define MIPS_SEGCFG_EU_SHIFT 3
784 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
785 #define MIPS_SEGCFG_C_SHIFT 0
786 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
788 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
789 #define MIPS_SEGCFG_USK _ULCAST_(5)
790 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
791 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
792 #define MIPS_SEGCFG_MSK _ULCAST_(2)
793 #define MIPS_SEGCFG_MK _ULCAST_(1)
794 #define MIPS_SEGCFG_UK _ULCAST_(0)
796 #define MIPS_PWFIELD_GDI_SHIFT 24
797 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
798 #define MIPS_PWFIELD_UDI_SHIFT 18
799 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
800 #define MIPS_PWFIELD_MDI_SHIFT 12
801 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
802 #define MIPS_PWFIELD_PTI_SHIFT 6
803 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
804 #define MIPS_PWFIELD_PTEI_SHIFT 0
805 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
807 #define MIPS_PWSIZE_PS_SHIFT 30
808 #define MIPS_PWSIZE_PS_MASK 0x40000000
809 #define MIPS_PWSIZE_GDW_SHIFT 24
810 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
811 #define MIPS_PWSIZE_UDW_SHIFT 18
812 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
813 #define MIPS_PWSIZE_MDW_SHIFT 12
814 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
815 #define MIPS_PWSIZE_PTW_SHIFT 6
816 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
817 #define MIPS_PWSIZE_PTEW_SHIFT 0
818 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
820 #define MIPS_PWCTL_PWEN_SHIFT 31
821 #define MIPS_PWCTL_PWEN_MASK 0x80000000
822 #define MIPS_PWCTL_XK_SHIFT 28
823 #define MIPS_PWCTL_XK_MASK 0x10000000
824 #define MIPS_PWCTL_XS_SHIFT 27
825 #define MIPS_PWCTL_XS_MASK 0x08000000
826 #define MIPS_PWCTL_XU_SHIFT 26
827 #define MIPS_PWCTL_XU_MASK 0x04000000
828 #define MIPS_PWCTL_DPH_SHIFT 7
829 #define MIPS_PWCTL_DPH_MASK 0x00000080
830 #define MIPS_PWCTL_HUGEPG_SHIFT 6
831 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
832 #define MIPS_PWCTL_PSN_SHIFT 0
833 #define MIPS_PWCTL_PSN_MASK 0x0000003f
835 /* GuestCtl0 fields */
836 #define MIPS_GCTL0_GM_SHIFT 31
837 #define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
838 #define MIPS_GCTL0_RI_SHIFT 30
839 #define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
840 #define MIPS_GCTL0_MC_SHIFT 29
841 #define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
842 #define MIPS_GCTL0_CP0_SHIFT 28
843 #define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
844 #define MIPS_GCTL0_AT_SHIFT 26
845 #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
846 #define MIPS_GCTL0_GT_SHIFT 25
847 #define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
848 #define MIPS_GCTL0_CG_SHIFT 24
849 #define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
850 #define MIPS_GCTL0_CF_SHIFT 23
851 #define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
852 #define MIPS_GCTL0_G1_SHIFT 22
853 #define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
854 #define MIPS_GCTL0_G0E_SHIFT 19
855 #define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
856 #define MIPS_GCTL0_PT_SHIFT 18
857 #define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
858 #define MIPS_GCTL0_RAD_SHIFT 9
859 #define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
860 #define MIPS_GCTL0_DRG_SHIFT 8
861 #define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
862 #define MIPS_GCTL0_G2_SHIFT 7
863 #define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
864 #define MIPS_GCTL0_GEXC_SHIFT 2
865 #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
866 #define MIPS_GCTL0_SFC2_SHIFT 1
867 #define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
868 #define MIPS_GCTL0_SFC1_SHIFT 0
869 #define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
871 /* GuestCtl0.AT Guest address translation control */
872 #define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
873 #define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
875 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
876 #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
877 #define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
878 #define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
879 #define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
880 #define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
881 #define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
882 #define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
884 /* GuestCtl0Ext fields */
885 #define MIPS_GCTL0EXT_RPW_SHIFT 8
886 #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
887 #define MIPS_GCTL0EXT_NCC_SHIFT 6
888 #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
889 #define MIPS_GCTL0EXT_CGI_SHIFT 4
890 #define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
891 #define MIPS_GCTL0EXT_FCD_SHIFT 3
892 #define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
893 #define MIPS_GCTL0EXT_OG_SHIFT 2
894 #define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
895 #define MIPS_GCTL0EXT_BG_SHIFT 1
896 #define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
897 #define MIPS_GCTL0EXT_MG_SHIFT 0
898 #define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
900 /* GuestCtl0Ext.RPW Root page walk configuration */
901 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
902 #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
903 #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
905 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
906 #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
907 #define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
909 /* GuestCtl1 fields */
910 #define MIPS_GCTL1_ID_SHIFT 0
911 #define MIPS_GCTL1_ID_WIDTH 8
912 #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
913 #define MIPS_GCTL1_RID_SHIFT 16
914 #define MIPS_GCTL1_RID_WIDTH 8
915 #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
916 #define MIPS_GCTL1_EID_SHIFT 24
917 #define MIPS_GCTL1_EID_WIDTH 8
918 #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
920 /* GuestID reserved for root context */
921 #define MIPS_GCTL1_ROOT_GUESTID 0
923 /* CDMMBase register bit definitions */
924 #define MIPS_CDMMBASE_SIZE_SHIFT 0
925 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
926 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
927 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
928 #define MIPS_CDMMBASE_ADDR_SHIFT 11
929 #define MIPS_CDMMBASE_ADDR_START 15
931 /* RDHWR register numbers */
932 #define MIPS_HWR_CPUNUM 0 /* CPU number */
933 #define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
934 #define MIPS_HWR_CC 2 /* Cycle counter */
935 #define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
936 #define MIPS_HWR_ULR 29 /* UserLocal */
937 #define MIPS_HWR_IMPL1 30 /* Implementation dependent */
938 #define MIPS_HWR_IMPL2 31 /* Implementation dependent */
940 /* Bits in HWREna register */
941 #define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
942 #define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
943 #define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
944 #define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
945 #define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
946 #define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
947 #define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
950 * Bitfields in the TX39 family CP0 Configuration Register 3
952 #define TX39_CONF_ICS_SHIFT 19
953 #define TX39_CONF_ICS_MASK 0x00380000
954 #define TX39_CONF_ICS_1KB 0x00000000
955 #define TX39_CONF_ICS_2KB 0x00080000
956 #define TX39_CONF_ICS_4KB 0x00100000
957 #define TX39_CONF_ICS_8KB 0x00180000
958 #define TX39_CONF_ICS_16KB 0x00200000
960 #define TX39_CONF_DCS_SHIFT 16
961 #define TX39_CONF_DCS_MASK 0x00070000
962 #define TX39_CONF_DCS_1KB 0x00000000
963 #define TX39_CONF_DCS_2KB 0x00010000
964 #define TX39_CONF_DCS_4KB 0x00020000
965 #define TX39_CONF_DCS_8KB 0x00030000
966 #define TX39_CONF_DCS_16KB 0x00040000
968 #define TX39_CONF_CWFON 0x00004000
969 #define TX39_CONF_WBON 0x00002000
970 #define TX39_CONF_RF_SHIFT 10
971 #define TX39_CONF_RF_MASK 0x00000c00
972 #define TX39_CONF_DOZE 0x00000200
973 #define TX39_CONF_HALT 0x00000100
974 #define TX39_CONF_LOCK 0x00000080
975 #define TX39_CONF_ICE 0x00000020
976 #define TX39_CONF_DCE 0x00000010
977 #define TX39_CONF_IRSIZE_SHIFT 2
978 #define TX39_CONF_IRSIZE_MASK 0x0000000c
979 #define TX39_CONF_DRSIZE_SHIFT 0
980 #define TX39_CONF_DRSIZE_MASK 0x00000003
983 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
985 /* Disable Branch Target Address Cache */
986 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
987 /* Enable Branch Prediction Global History */
988 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
989 /* Disable Branch Return Cache */
990 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
993 #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
995 #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
997 #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
999 #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1001 /* CvmCtl register field definitions */
1002 #define CVMCTL_IPPCI_SHIFT 7
1003 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1004 #define CVMCTL_IPTI_SHIFT 4
1005 #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1007 /* CvmMemCtl2 register field definitions */
1008 #define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1010 /* CvmVMConfig register field definitions */
1011 #define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1012 #define CVMVMCONF_MMUSIZEM1_S 12
1013 #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1014 #define CVMVMCONF_RMMUSIZEM1_S 0
1015 #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1018 * Coprocessor 1 (FPU) register names
1020 #define CP1_REVISION $0
1023 #define CP1_FCCR $25
1024 #define CP1_FEXR $26
1025 #define CP1_FENR $28
1026 #define CP1_STATUS $31
1030 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1032 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
1033 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
1034 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1035 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1036 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
1037 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
1038 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1039 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1040 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1041 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1044 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1046 #define MIPS_FCCR_CONDX_S 0
1047 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1048 #define MIPS_FCCR_COND0_S 0
1049 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1050 #define MIPS_FCCR_COND1_S 1
1051 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1052 #define MIPS_FCCR_COND2_S 2
1053 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1054 #define MIPS_FCCR_COND3_S 3
1055 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1056 #define MIPS_FCCR_COND4_S 4
1057 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1058 #define MIPS_FCCR_COND5_S 5
1059 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1060 #define MIPS_FCCR_COND6_S 6
1061 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1062 #define MIPS_FCCR_COND7_S 7
1063 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1066 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1068 #define MIPS_FENR_FS_S 2
1069 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1072 * FPU Status Register Values
1074 #define FPU_CSR_COND_S 23 /* $fcc0 */
1075 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1077 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1078 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1080 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1081 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1082 #define FPU_CSR_COND1_S 25 /* $fcc1 */
1083 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1084 #define FPU_CSR_COND2_S 26 /* $fcc2 */
1085 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1086 #define FPU_CSR_COND3_S 27 /* $fcc3 */
1087 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1088 #define FPU_CSR_COND4_S 28 /* $fcc4 */
1089 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1090 #define FPU_CSR_COND5_S 29 /* $fcc5 */
1091 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1092 #define FPU_CSR_COND6_S 30 /* $fcc6 */
1093 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1094 #define FPU_CSR_COND7_S 31 /* $fcc7 */
1095 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1098 * Bits 22:20 of the FPU Status Register will be read as 0,
1099 * and should be written as zero.
1101 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1103 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1104 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1107 * X the exception cause indicator
1108 * E the exception enable
1109 * S the sticky/flag bit
1111 #define FPU_CSR_ALL_X 0x0003f000
1112 #define FPU_CSR_UNI_X 0x00020000
1113 #define FPU_CSR_INV_X 0x00010000
1114 #define FPU_CSR_DIV_X 0x00008000
1115 #define FPU_CSR_OVF_X 0x00004000
1116 #define FPU_CSR_UDF_X 0x00002000
1117 #define FPU_CSR_INE_X 0x00001000
1119 #define FPU_CSR_ALL_E 0x00000f80
1120 #define FPU_CSR_INV_E 0x00000800
1121 #define FPU_CSR_DIV_E 0x00000400
1122 #define FPU_CSR_OVF_E 0x00000200
1123 #define FPU_CSR_UDF_E 0x00000100
1124 #define FPU_CSR_INE_E 0x00000080
1126 #define FPU_CSR_ALL_S 0x0000007c
1127 #define FPU_CSR_INV_S 0x00000040
1128 #define FPU_CSR_DIV_S 0x00000020
1129 #define FPU_CSR_OVF_S 0x00000010
1130 #define FPU_CSR_UDF_S 0x00000008
1131 #define FPU_CSR_INE_S 0x00000004
1133 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1134 #define FPU_CSR_RM 0x00000003
1135 #define FPU_CSR_RN 0x0 /* nearest */
1136 #define FPU_CSR_RZ 0x1 /* towards zero */
1137 #define FPU_CSR_RU 0x2 /* towards +Infinity */
1138 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1141 #ifndef __ASSEMBLY__
1144 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1146 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1147 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1148 #define get_isa16_mode(x) ((x) & 0x1)
1149 #define msk_isa16_mode(x) ((x) & ~0x1)
1150 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1152 #define get_isa16_mode(x) 0
1153 #define msk_isa16_mode(x) (x)
1154 #define set_isa16_mode(x) do { } while(0)
1158 * microMIPS instructions can be 16-bit or 32-bit in length. This
1159 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1161 static inline int mm_insn_16bit(u16 insn)
1163 u16 opcode = (insn >> 10) & 0x7;
1165 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1169 * Helper macros for generating raw instruction encodings in inline asm.
1171 #ifdef CONFIG_CPU_MICROMIPS
1172 #define _ASM_INSN16_IF_MM(_enc) \
1174 ".hword (" #_enc ")\n\t"
1175 #define _ASM_INSN32_IF_MM(_enc) \
1177 ".hword ((" #_enc ") >> 16)\n\t" \
1178 ".hword ((" #_enc ") & 0xffff)\n\t"
1180 #define _ASM_INSN_IF_MIPS(_enc) \
1182 ".word (" #_enc ")\n\t"
1185 #ifndef _ASM_INSN16_IF_MM
1186 #define _ASM_INSN16_IF_MM(_enc)
1188 #ifndef _ASM_INSN32_IF_MM
1189 #define _ASM_INSN32_IF_MM(_enc)
1191 #ifndef _ASM_INSN_IF_MIPS
1192 #define _ASM_INSN_IF_MIPS(_enc)
1196 * parse_r var, r - Helper assembler macro for parsing register names.
1198 * This converts the register name in $n form provided in \r to the
1199 * corresponding register number, which is assigned to the variable \var. It is
1200 * needed to allow explicit encoding of instructions in inline assembly where
1201 * registers are chosen by the compiler in $n form, allowing us to avoid using
1202 * fixed register numbers.
1204 * It also allows newer instructions (not implemented by the assembler) to be
1205 * transparently implemented using assembler macros, instead of needing separate
1206 * cases depending on toolchain support.
1208 * Simple usage example:
1209 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1212 * ".word (0x41606000 | (__rt << 16))"
1216 /* Match an individual register number and assign to \var */
1217 #define _IFC_REG(n) \
1218 ".ifc \\r, $" #n "\n\t" \
1219 "\\var = " #n "\n\t" \
1222 __asm__(".macro parse_r var r\n\t"
1224 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1225 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1226 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1227 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1228 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1229 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1230 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1231 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1233 ".error \"Unable to parse register name \\r\"\n\t"
1240 * C macros for generating assembler macros for common instruction formats.
1242 * The names of the operands can be chosen by the caller, and the encoding of
1243 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1244 * the ENC encodings.
1247 /* Instructions with no operands */
1248 #define _ASM_MACRO_0(OP, ENC) \
1249 __asm__(".macro " #OP "\n\t" \
1253 /* Instructions with 2 register operands */
1254 #define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1255 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1256 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1257 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1261 /* Instructions with 3 register operands */
1262 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1263 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1264 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1265 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1266 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1270 /* Instructions with 2 register operands and 1 optional select operand */
1271 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1272 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1273 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1274 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1279 * TLB Invalidate Flush
1281 static inline void tlbinvf(void)
1283 __asm__ __volatile__(
1285 ".set noreorder\n\t"
1287 _ASM_INSN_IF_MIPS(0x42000004)
1288 _ASM_INSN32_IF_MM(0x0000537c)
1294 * Functions to access the R10000 performance counters. These are basically
1295 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1296 * performance counter number encoded into bits 1 ... 5 of the instruction.
1297 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1298 * disassembler these will look like an access to sel 0 or 1.
1300 #define read_r10k_perf_cntr(counter) \
1302 unsigned int __res; \
1303 __asm__ __volatile__( \
1311 #define write_r10k_perf_cntr(counter,val) \
1313 __asm__ __volatile__( \
1316 : "r" (val), "i" (counter)); \
1319 #define read_r10k_perf_event(counter) \
1321 unsigned int __res; \
1322 __asm__ __volatile__( \
1330 #define write_r10k_perf_cntl(counter,val) \
1332 __asm__ __volatile__( \
1335 : "r" (val), "i" (counter)); \
1340 * Macros to access the system control coprocessor
1343 #define ___read_32bit_c0_register(source, sel, vol) \
1344 ({ unsigned int __res; \
1347 "mfc0\t%0, " #source "\n\t" \
1351 ".set\tmips32\n\t" \
1352 "mfc0\t%0, " #source ", " #sel "\n\t" \
1358 #define ___read_64bit_c0_register(source, sel, vol) \
1359 ({ unsigned long long __res; \
1360 if (sizeof(unsigned long) == 4) \
1361 __res = __read_64bit_c0_split(source, sel, vol); \
1362 else if (sel == 0) \
1365 "dmfc0\t%0, " #source "\n\t" \
1370 ".set\tmips64\n\t" \
1371 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1377 #define __read_32bit_c0_register(source, sel) \
1378 ___read_32bit_c0_register(source, sel, __volatile__)
1380 #define __read_const_32bit_c0_register(source, sel) \
1381 ___read_32bit_c0_register(source, sel,)
1383 #define __read_64bit_c0_register(source, sel) \
1384 ___read_64bit_c0_register(source, sel, __volatile__)
1386 #define __read_const_64bit_c0_register(source, sel) \
1387 ___read_64bit_c0_register(source, sel,)
1389 #define __write_32bit_c0_register(register, sel, value) \
1392 __asm__ __volatile__( \
1393 "mtc0\t%z0, " #register "\n\t" \
1394 : : "Jr" ((unsigned int)(value))); \
1396 __asm__ __volatile__( \
1397 ".set\tmips32\n\t" \
1398 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1400 : : "Jr" ((unsigned int)(value))); \
1403 #define __write_64bit_c0_register(register, sel, value) \
1405 if (sizeof(unsigned long) == 4) \
1406 __write_64bit_c0_split(register, sel, value); \
1407 else if (sel == 0) \
1408 __asm__ __volatile__( \
1410 "dmtc0\t%z0, " #register "\n\t" \
1412 : : "Jr" (value)); \
1414 __asm__ __volatile__( \
1415 ".set\tmips64\n\t" \
1416 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1418 : : "Jr" (value)); \
1421 #define __read_ulong_c0_register(reg, sel) \
1422 ((sizeof(unsigned long) == 4) ? \
1423 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1424 (unsigned long) __read_64bit_c0_register(reg, sel))
1426 #define __read_const_ulong_c0_register(reg, sel) \
1427 ((sizeof(unsigned long) == 4) ? \
1428 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1429 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1431 #define __write_ulong_c0_register(reg, sel, val) \
1433 if (sizeof(unsigned long) == 4) \
1434 __write_32bit_c0_register(reg, sel, val); \
1436 __write_64bit_c0_register(reg, sel, val); \
1440 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1442 #define __read_32bit_c0_ctrl_register(source) \
1443 ({ unsigned int __res; \
1444 __asm__ __volatile__( \
1445 "cfc0\t%0, " #source "\n\t" \
1450 #define __write_32bit_c0_ctrl_register(register, value) \
1452 __asm__ __volatile__( \
1453 "ctc0\t%z0, " #register "\n\t" \
1454 : : "Jr" ((unsigned int)(value))); \
1458 * These versions are only needed for systems with more than 38 bits of
1459 * physical address space running the 32-bit kernel. That's none atm :-)
1461 #define __read_64bit_c0_split(source, sel, vol) \
1463 unsigned long long __val; \
1464 unsigned long __flags; \
1466 local_irq_save(__flags); \
1469 ".set\tmips64\n\t" \
1470 "dmfc0\t%L0, " #source "\n\t" \
1471 "dsra\t%M0, %L0, 32\n\t" \
1472 "sll\t%L0, %L0, 0\n\t" \
1477 ".set\tmips64\n\t" \
1478 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1479 "dsra\t%M0, %L0, 32\n\t" \
1480 "sll\t%L0, %L0, 0\n\t" \
1483 local_irq_restore(__flags); \
1488 #define __write_64bit_c0_split(source, sel, val) \
1490 unsigned long long __tmp = (val); \
1491 unsigned long __flags; \
1493 local_irq_save(__flags); \
1494 if (MIPS_ISA_REV >= 2) \
1495 __asm__ __volatile__( \
1497 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1498 "dins\t%L0, %M0, 32, 32\n\t" \
1499 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1502 else if (sel == 0) \
1503 __asm__ __volatile__( \
1504 ".set\tmips64\n\t" \
1505 "dsll\t%L0, %L0, 32\n\t" \
1506 "dsrl\t%L0, %L0, 32\n\t" \
1507 "dsll\t%M0, %M0, 32\n\t" \
1508 "or\t%L0, %L0, %M0\n\t" \
1509 "dmtc0\t%L0, " #source "\n\t" \
1513 __asm__ __volatile__( \
1514 ".set\tmips64\n\t" \
1515 "dsll\t%L0, %L0, 32\n\t" \
1516 "dsrl\t%L0, %L0, 32\n\t" \
1517 "dsll\t%M0, %M0, 32\n\t" \
1518 "or\t%L0, %L0, %M0\n\t" \
1519 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1522 local_irq_restore(__flags); \
1525 #ifndef TOOLCHAIN_SUPPORTS_XPA
1526 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1527 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1528 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1529 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1530 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1531 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1532 #define _ASM_SET_XPA ""
1533 #else /* !TOOLCHAIN_SUPPORTS_XPA */
1534 #define _ASM_SET_XPA ".set\txpa\n\t"
1537 #define __readx_32bit_c0_register(source, sel) \
1539 unsigned int __res; \
1541 __asm__ __volatile__( \
1543 " .set mips32r2 \n" \
1545 " mfhc0 %0, " #source ", %1 \n" \
1552 #define __writex_32bit_c0_register(register, sel, value) \
1554 __asm__ __volatile__( \
1556 " .set mips32r2 \n" \
1558 " mthc0 %z0, " #register ", %1 \n" \
1561 : "Jr" (value), "i" (sel)); \
1564 #define read_c0_index() __read_32bit_c0_register($0, 0)
1565 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1567 #define read_c0_random() __read_32bit_c0_register($1, 0)
1568 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1570 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1571 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1573 #define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1574 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1576 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1577 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1579 #define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1580 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1582 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1583 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1585 #define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1587 #define read_c0_context() __read_ulong_c0_register($4, 0)
1588 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1590 #define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1591 #define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1593 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1594 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1596 #define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1597 #define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1599 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1600 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1602 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1603 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1605 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1606 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1608 #define read_c0_info() __read_32bit_c0_register($7, 0)
1610 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1611 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1613 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1614 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1616 #define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1617 #define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1619 #define read_c0_count() __read_32bit_c0_register($9, 0)
1620 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1622 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1623 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1625 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1626 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1628 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1629 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1631 #define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1632 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1634 #define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1635 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1637 #define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1638 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1640 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1641 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1643 #define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1644 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1646 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1647 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1649 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1650 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1652 #define read_c0_status() __read_32bit_c0_register($12, 0)
1654 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1656 #define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1657 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1659 #define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1660 #define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1662 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1663 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1665 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1666 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1668 #define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1670 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1672 #define read_c0_config() __read_32bit_c0_register($16, 0)
1673 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1674 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1675 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1676 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1677 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1678 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1679 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1680 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1681 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1682 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1683 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1684 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1685 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1686 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1687 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1689 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1690 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1691 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1692 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1693 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1694 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1697 * The WatchLo register. There may be up to 8 of them.
1699 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1700 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1701 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1702 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1703 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1704 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1705 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1706 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1707 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1708 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1709 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1710 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1711 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1712 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1713 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1714 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1717 * The WatchHi register. There may be up to 8 of them.
1719 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1720 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1721 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1722 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1723 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1724 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1725 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1726 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1728 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1729 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1730 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1731 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1732 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1733 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1734 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1735 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1737 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1738 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1740 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1741 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1743 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1744 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1746 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1747 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1749 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1750 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1751 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1753 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1754 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1756 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1757 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1759 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1760 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1762 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1763 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1765 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1766 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1768 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1769 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1771 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1772 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1775 * MIPS32 / MIPS64 performance counters
1777 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1778 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1779 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1780 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1781 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1782 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1783 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1784 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1785 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1786 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1787 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1788 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1789 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1790 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1791 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1792 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1793 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1794 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1795 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1796 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1797 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1798 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1799 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1800 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1802 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1803 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1805 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1806 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1808 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1810 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1811 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1813 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1814 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1816 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1817 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1819 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1820 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1822 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1823 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1825 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1826 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1828 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1829 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1832 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1833 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1835 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1836 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1838 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1839 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1841 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1842 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1844 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1845 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1847 #define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1848 #define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1850 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1851 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1854 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1855 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1857 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1858 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1860 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1861 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1863 /* Hardware Page Table Walker */
1864 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1865 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1867 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1868 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1870 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1871 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1873 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1874 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1876 #define read_c0_pgd() __read_64bit_c0_register($9, 7)
1877 #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1879 #define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1880 #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1882 /* Cavium OCTEON (cnMIPS) */
1883 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1884 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1886 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1887 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1889 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1890 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1892 #define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1893 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1895 #define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1896 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1899 * The cacheerr registers are not standardized. On OCTEON, they are
1902 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1903 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1905 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1906 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1909 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1910 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1912 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1913 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1915 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1916 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1919 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1920 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1922 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1923 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1925 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1926 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1928 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1929 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1931 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1932 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1935 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1936 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1938 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1939 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1941 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1942 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1944 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1945 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1947 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1948 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1950 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1951 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1954 * Macros to access the guest system control coprocessor
1957 #ifndef TOOLCHAIN_SUPPORTS_VIRT
1958 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1959 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1960 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1961 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1962 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1963 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1964 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1965 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1966 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1967 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1968 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1969 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1970 _ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
1971 _ASM_INSN32_IF_MM(0x0000017c));
1972 _ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
1973 _ASM_INSN32_IF_MM(0x0000117c));
1974 _ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
1975 _ASM_INSN32_IF_MM(0x0000217c));
1976 _ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
1977 _ASM_INSN32_IF_MM(0x0000317c));
1978 _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1979 _ASM_INSN32_IF_MM(0x0000517c));
1980 #define _ASM_SET_VIRT ""
1981 #else /* !TOOLCHAIN_SUPPORTS_VIRT */
1982 #define _ASM_SET_VIRT ".set\tvirt\n\t"
1985 #define __read_32bit_gc0_register(source, sel) \
1987 __asm__ __volatile__( \
1989 ".set\tmips32r5\n\t" \
1991 "mfgc0\t%0, " #source ", %1\n\t" \
1998 #define __read_64bit_gc0_register(source, sel) \
1999 ({ unsigned long long __res; \
2000 __asm__ __volatile__( \
2002 ".set\tmips64r5\n\t" \
2004 "dmfgc0\t%0, " #source ", %1\n\t" \
2011 #define __write_32bit_gc0_register(register, sel, value) \
2013 __asm__ __volatile__( \
2015 ".set\tmips32r5\n\t" \
2017 "mtgc0\t%z0, " #register ", %1\n\t" \
2019 : : "Jr" ((unsigned int)(value)), \
2023 #define __write_64bit_gc0_register(register, sel, value) \
2025 __asm__ __volatile__( \
2027 ".set\tmips64r5\n\t" \
2029 "dmtgc0\t%z0, " #register ", %1\n\t" \
2035 #define __read_ulong_gc0_register(reg, sel) \
2036 ((sizeof(unsigned long) == 4) ? \
2037 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2038 (unsigned long) __read_64bit_gc0_register(reg, sel))
2040 #define __write_ulong_gc0_register(reg, sel, val) \
2042 if (sizeof(unsigned long) == 4) \
2043 __write_32bit_gc0_register(reg, sel, val); \
2045 __write_64bit_gc0_register(reg, sel, val); \
2048 #define read_gc0_index() __read_32bit_gc0_register($0, 0)
2049 #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2051 #define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2052 #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2054 #define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2055 #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2057 #define read_gc0_context() __read_ulong_gc0_register($4, 0)
2058 #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2060 #define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2061 #define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2063 #define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2064 #define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2066 #define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2067 #define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2069 #define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2070 #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2072 #define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2073 #define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2075 #define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2076 #define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2078 #define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2079 #define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2081 #define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2082 #define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2084 #define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2085 #define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2087 #define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2088 #define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2090 #define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2091 #define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2093 #define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2094 #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2096 #define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2097 #define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2099 #define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2100 #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2102 #define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2103 #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2105 #define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2106 #define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2108 #define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2109 #define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2111 #define read_gc0_count() __read_32bit_gc0_register($9, 0)
2113 #define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2114 #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2116 #define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2117 #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2119 #define read_gc0_status() __read_32bit_gc0_register($12, 0)
2120 #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2122 #define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2123 #define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2125 #define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2126 #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2128 #define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2129 #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2131 #define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2133 #define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2134 #define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2136 #define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2137 #define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2139 #define read_gc0_config() __read_32bit_gc0_register($16, 0)
2140 #define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2141 #define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2142 #define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2143 #define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2144 #define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2145 #define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2146 #define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2147 #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2148 #define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2149 #define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2150 #define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2151 #define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2152 #define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2153 #define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2154 #define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2156 #define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2157 #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2159 #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2160 #define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2161 #define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2162 #define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2163 #define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2164 #define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2165 #define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2166 #define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2167 #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2168 #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2169 #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2170 #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2171 #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2172 #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2173 #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2174 #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2176 #define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2177 #define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2178 #define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2179 #define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2180 #define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2181 #define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2182 #define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2183 #define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2184 #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2185 #define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2186 #define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2187 #define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2188 #define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2189 #define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2190 #define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2191 #define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2193 #define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2194 #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2196 #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2197 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2198 #define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2199 #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2200 #define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2201 #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2202 #define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2203 #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2204 #define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2205 #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2206 #define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2207 #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2208 #define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2209 #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2210 #define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2211 #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2212 #define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2213 #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2214 #define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2215 #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2216 #define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2217 #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2218 #define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2219 #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2221 #define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2222 #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2224 #define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2225 #define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2226 #define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2227 #define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2228 #define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2229 #define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2230 #define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2231 #define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2232 #define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2233 #define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2234 #define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2235 #define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2237 /* Cavium OCTEON (cnMIPS) */
2238 #define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2239 #define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2241 #define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2242 #define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2244 #define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2245 #define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2247 #define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2248 #define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2251 * Macros to access the floating point coprocessor control registers
2253 #define _read_32bit_cp1_register(source, gas_hardfloat) \
2255 unsigned int __res; \
2257 __asm__ __volatile__( \
2259 " .set reorder \n" \
2260 " # gas fails to assemble cfc1 for some archs, \n" \
2261 " # like Octeon. \n" \
2263 " "STR(gas_hardfloat)" \n" \
2264 " cfc1 %0,"STR(source)" \n" \
2270 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2272 __asm__ __volatile__( \
2274 " .set reorder \n" \
2275 " "STR(gas_hardfloat)" \n" \
2276 " ctc1 %0,"STR(dest)" \n" \
2281 #ifdef GAS_HAS_SET_HARDFLOAT
2282 #define read_32bit_cp1_register(source) \
2283 _read_32bit_cp1_register(source, .set hardfloat)
2284 #define write_32bit_cp1_register(dest, val) \
2285 _write_32bit_cp1_register(dest, val, .set hardfloat)
2287 #define read_32bit_cp1_register(source) \
2288 _read_32bit_cp1_register(source, )
2289 #define write_32bit_cp1_register(dest, val) \
2290 _write_32bit_cp1_register(dest, val, )
2294 #define rddsp(mask) \
2296 unsigned int __dspctl; \
2298 __asm__ __volatile__( \
2301 " rddsp %0, %x1 \n" \
2308 #define wrdsp(val, mask) \
2310 __asm__ __volatile__( \
2313 " wrdsp %0, %x1 \n" \
2316 : "r" (val), "i" (mask)); \
2325 " mflo %0, $ac0 \n" \
2337 " mflo %0, $ac1 \n" \
2349 " mflo %0, $ac2 \n" \
2361 " mflo %0, $ac3 \n" \
2373 " mfhi %0, $ac0 \n" \
2385 " mfhi %0, $ac1 \n" \
2397 " mfhi %0, $ac2 \n" \
2409 " mfhi %0, $ac3 \n" \
2421 " mtlo %0, $ac0 \n" \
2432 " mtlo %0, $ac1 \n" \
2443 " mtlo %0, $ac2 \n" \
2454 " mtlo %0, $ac3 \n" \
2465 " mthi %0, $ac0 \n" \
2476 " mthi %0, $ac1 \n" \
2487 " mthi %0, $ac2 \n" \
2498 " mthi %0, $ac3 \n" \
2506 #define rddsp(mask) \
2508 unsigned int __res; \
2510 __asm__ __volatile__( \
2513 " # rddsp $1, %x1 \n" \
2514 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2515 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2523 #define wrdsp(val, mask) \
2525 __asm__ __volatile__( \
2529 " # wrdsp $1, %x1 \n" \
2530 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2531 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2534 : "r" (val), "i" (mask)); \
2537 #define _dsp_mfxxx(ins) \
2539 unsigned long __treg; \
2541 __asm__ __volatile__( \
2544 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2545 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2553 #define _dsp_mtxxx(val, ins) \
2555 __asm__ __volatile__( \
2559 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2560 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2563 : "r" (val), "i" (ins)); \
2566 #ifdef CONFIG_CPU_MICROMIPS
2568 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2569 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2571 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2572 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2574 #else /* !CONFIG_CPU_MICROMIPS */
2576 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2577 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2579 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2580 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2582 #endif /* CONFIG_CPU_MICROMIPS */
2584 #define mflo0() _dsp_mflo(0)
2585 #define mflo1() _dsp_mflo(1)
2586 #define mflo2() _dsp_mflo(2)
2587 #define mflo3() _dsp_mflo(3)
2589 #define mfhi0() _dsp_mfhi(0)
2590 #define mfhi1() _dsp_mfhi(1)
2591 #define mfhi2() _dsp_mfhi(2)
2592 #define mfhi3() _dsp_mfhi(3)
2594 #define mtlo0(x) _dsp_mtlo(x, 0)
2595 #define mtlo1(x) _dsp_mtlo(x, 1)
2596 #define mtlo2(x) _dsp_mtlo(x, 2)
2597 #define mtlo3(x) _dsp_mtlo(x, 3)
2599 #define mthi0(x) _dsp_mthi(x, 0)
2600 #define mthi1(x) _dsp_mthi(x, 1)
2601 #define mthi2(x) _dsp_mthi(x, 2)
2602 #define mthi3(x) _dsp_mthi(x, 3)
2609 * It is responsibility of the caller to take care of any TLB hazards.
2611 static inline void tlb_probe(void)
2613 __asm__ __volatile__(
2614 ".set noreorder\n\t"
2619 static inline void tlb_read(void)
2621 #if MIPS34K_MISSED_ITLB_WAR
2624 __asm__ __volatile__(
2626 " .set noreorder \n"
2629 " .word 0x41610001 # dvpe $1 \n"
2635 instruction_hazard();
2638 __asm__ __volatile__(
2639 ".set noreorder\n\t"
2643 #if MIPS34K_MISSED_ITLB_WAR
2644 if ((res & _ULCAST_(1)))
2645 __asm__ __volatile__(
2647 " .set noreorder \n"
2650 " .word 0x41600021 # evpe \n"
2656 static inline void tlb_write_indexed(void)
2658 __asm__ __volatile__(
2659 ".set noreorder\n\t"
2664 static inline void tlb_write_random(void)
2666 __asm__ __volatile__(
2667 ".set noreorder\n\t"
2673 * Guest TLB operations.
2675 * It is responsibility of the caller to take care of any TLB hazards.
2677 static inline void guest_tlb_probe(void)
2679 __asm__ __volatile__(
2681 ".set noreorder\n\t"
2687 static inline void guest_tlb_read(void)
2689 __asm__ __volatile__(
2691 ".set noreorder\n\t"
2697 static inline void guest_tlb_write_indexed(void)
2699 __asm__ __volatile__(
2701 ".set noreorder\n\t"
2707 static inline void guest_tlb_write_random(void)
2709 __asm__ __volatile__(
2711 ".set noreorder\n\t"
2718 * Guest TLB Invalidate Flush
2720 static inline void guest_tlbinvf(void)
2722 __asm__ __volatile__(
2724 ".set noreorder\n\t"
2731 * Manipulate bits in a register.
2733 #define __BUILD_SET_COMMON(name) \
2734 static inline unsigned int \
2735 set_##name(unsigned int set) \
2737 unsigned int res, new; \
2739 res = read_##name(); \
2741 write_##name(new); \
2746 static inline unsigned int \
2747 clear_##name(unsigned int clear) \
2749 unsigned int res, new; \
2751 res = read_##name(); \
2752 new = res & ~clear; \
2753 write_##name(new); \
2758 static inline unsigned int \
2759 change_##name(unsigned int change, unsigned int val) \
2761 unsigned int res, new; \
2763 res = read_##name(); \
2764 new = res & ~change; \
2765 new |= (val & change); \
2766 write_##name(new); \
2772 * Manipulate bits in a c0 register.
2774 #define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2776 __BUILD_SET_C0(status)
2777 __BUILD_SET_C0(cause)
2778 __BUILD_SET_C0(config)
2779 __BUILD_SET_C0(config5)
2780 __BUILD_SET_C0(config7)
2781 __BUILD_SET_C0(intcontrol)
2782 __BUILD_SET_C0(intctl)
2783 __BUILD_SET_C0(srsmap)
2784 __BUILD_SET_C0(pagegrain)
2785 __BUILD_SET_C0(guestctl0)
2786 __BUILD_SET_C0(guestctl0ext)
2787 __BUILD_SET_C0(guestctl1)
2788 __BUILD_SET_C0(guestctl2)
2789 __BUILD_SET_C0(guestctl3)
2790 __BUILD_SET_C0(brcm_config_0)
2791 __BUILD_SET_C0(brcm_bus_pll)
2792 __BUILD_SET_C0(brcm_reset)
2793 __BUILD_SET_C0(brcm_cmt_intr)
2794 __BUILD_SET_C0(brcm_cmt_ctrl)
2795 __BUILD_SET_C0(brcm_config)
2796 __BUILD_SET_C0(brcm_mode)
2799 * Manipulate bits in a guest c0 register.
2801 #define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2803 __BUILD_SET_GC0(wired)
2804 __BUILD_SET_GC0(status)
2805 __BUILD_SET_GC0(cause)
2806 __BUILD_SET_GC0(ebase)
2807 __BUILD_SET_GC0(config1)
2810 * Return low 10 bits of ebase.
2811 * Note that under KVM (MIPSVZ) this returns vcpu id.
2813 static inline unsigned int get_ebase_cpunum(void)
2815 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2818 #endif /* !__ASSEMBLY__ */
2820 #endif /* _ASM_MIPSREGS_H */