arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #define _U64CAST_
  38 #else
  39 #define _ULCAST_ (unsigned long)
  40 #define _U64CAST_ (u64)
  41 #endif
  42
  43 /*
  44  * Coprocessor 0 register names
  45  */
  46 #define CP0_INDEX $0
  47 #define CP0_RANDOM $1
  48 #define CP0_ENTRYLO0 $2
  49 #define CP0_ENTRYLO1 $3
  50 #define CP0_CONF $3
  51 #define CP0_GLOBALNUMBER $3, 1
  52 #define CP0_CONTEXT $4
  53 #define CP0_PAGEMASK $5
  54 #define CP0_SEGCTL0 $5, 2
  55 #define CP0_SEGCTL1 $5, 3
  56 #define CP0_SEGCTL2 $5, 4
  57 #define CP0_WIRED $6
  58 #define CP0_INFO $7
  59 #define CP0_HWRENA $7
  60 #define CP0_BADVADDR $8
  61 #define CP0_BADINSTR $8, 1
  62 #define CP0_COUNT $9
  63 #define CP0_ENTRYHI $10
  64 #define CP0_GUESTCTL1 $10, 4
  65 #define CP0_GUESTCTL2 $10, 5
  66 #define CP0_GUESTCTL3 $10, 6
  67 #define CP0_COMPARE $11
  68 #define CP0_GUESTCTL0EXT $11, 4
  69 #define CP0_STATUS $12
  70 #define CP0_GUESTCTL0 $12, 6
  71 #define CP0_GTOFFSET $12, 7
  72 #define CP0_CAUSE $13
  73 #define CP0_EPC $14
  74 #define CP0_PRID $15
  75 #define CP0_EBASE $15, 1
  76 #define CP0_CMGCRBASE $15, 3
  77 #define CP0_CONFIG $16
  78 #define CP0_CONFIG3 $16, 3
  79 #define CP0_CONFIG5 $16, 5
  80 #define CP0_LLADDR $17
  81 #define CP0_WATCHLO $18
  82 #define CP0_WATCHHI $19
  83 #define CP0_XCONTEXT $20
  84 #define CP0_FRAMEMASK $21
  85 #define CP0_DIAGNOSTIC $22
  86 #define CP0_DEBUG $23
  87 #define CP0_DEPC $24
  88 #define CP0_PERFORMANCE $25
  89 #define CP0_ECC $26
  90 #define CP0_CACHEERR $27
  91 #define CP0_TAGLO $28
  92 #define CP0_TAGHI $29
  93 #define CP0_ERROREPC $30
  94 #define CP0_DESAVE $31
  95
  96 /*
  97  * R4640/R4650 cp0 register names.  These registers are listed
  98  * here only for completeness; without MMU these CPUs are not useable
  99  * by Linux.  A future ELKS port might take make Linux run on them
 100  * though ...
 101  */
 102 #define CP0_IBASE $0
 103 #define CP0_IBOUND $1
 104 #define CP0_DBASE $2
 105 #define CP0_DBOUND $3
 106 #define CP0_CALG $17
 107 #define CP0_IWATCH $18
 108 #define CP0_DWATCH $19
 109
 110 /*
 111  * Coprocessor 0 Set 1 register names
 112  */
 113 #define CP0_S1_DERRADDR0  $26
 114 #define CP0_S1_DERRADDR1  $27
 115 #define CP0_S1_INTCONTROL $20
 116
 117 /*
 118  * Coprocessor 0 Set 2 register names
 119  */
 120 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 121
 122 /*
 123  * Coprocessor 0 Set 3 register names
 124  */
 125 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 126
 127 /*
 128  *  TX39 Series
 129  */
 130 #define CP0_TX39_CACHE  $7
 131
 132
 133 /* Generic EntryLo bit definitions */
 134 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 135 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 136 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 137 #define ENTRYLO_C_SHIFT         3
 138 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 139
 140 /* R3000 EntryLo bit definitions */
 141 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 142 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 143 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 144 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 145
 146 /* MIPS32/64 EntryLo bit definitions */
 147 #define MIPS_ENTRYLO_PFN_SHIFT  6
 148 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 149 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 150
 151 /*
 152  * MIPSr6+ GlobalNumber register definitions
 153  */
 154 #define MIPS_GLOBALNUMBER_VP_SHF        0
 155 #define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 156 #define MIPS_GLOBALNUMBER_CORE_SHF      8
 157 #define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 158 #define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
 159 #define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 160
 161 /*
 162  * Values for PageMask register
 163  */
 164 #ifdef CONFIG_CPU_VR41XX
 165
 166 /* Why doesn't stupidity hurt ... */
 167
 168 #define PM_1K           0x00000000
 169 #define PM_4K           0x00001800
 170 #define PM_16K          0x00007800
 171 #define PM_64K          0x0001f800
 172 #define PM_256K         0x0007f800
 173
 174 #else
 175
 176 #define PM_4K           0x00000000
 177 #define PM_8K           0x00002000
 178 #define PM_16K          0x00006000
 179 #define PM_32K          0x0000e000
 180 #define PM_64K          0x0001e000
 181 #define PM_128K         0x0003e000
 182 #define PM_256K         0x0007e000
 183 #define PM_512K         0x000fe000
 184 #define PM_1M           0x001fe000
 185 #define PM_2M           0x003fe000
 186 #define PM_4M           0x007fe000
 187 #define PM_8M           0x00ffe000
 188 #define PM_16M          0x01ffe000
 189 #define PM_32M          0x03ffe000
 190 #define PM_64M          0x07ffe000
 191 #define PM_256M         0x1fffe000
 192 #define PM_1G           0x7fffe000
 193
 194 #endif
 195
 196 /*
 197  * Default page size for a given kernel configuration
 198  */
 199 #ifdef CONFIG_PAGE_SIZE_4KB
 200 #define PM_DEFAULT_MASK PM_4K
 201 #elif defined(CONFIG_PAGE_SIZE_8KB)
 202 #define PM_DEFAULT_MASK PM_8K
 203 #elif defined(CONFIG_PAGE_SIZE_16KB)
 204 #define PM_DEFAULT_MASK PM_16K
 205 #elif defined(CONFIG_PAGE_SIZE_32KB)
 206 #define PM_DEFAULT_MASK PM_32K
 207 #elif defined(CONFIG_PAGE_SIZE_64KB)
 208 #define PM_DEFAULT_MASK PM_64K
 209 #else
 210 #error Bad page size configuration!
 211 #endif
 212
 213 /*
 214  * Default huge tlb size for a given kernel configuration
 215  */
 216 #ifdef CONFIG_PAGE_SIZE_4KB
 217 #define PM_HUGE_MASK    PM_1M
 218 #elif defined(CONFIG_PAGE_SIZE_8KB)
 219 #define PM_HUGE_MASK    PM_4M
 220 #elif defined(CONFIG_PAGE_SIZE_16KB)
 221 #define PM_HUGE_MASK    PM_16M
 222 #elif defined(CONFIG_PAGE_SIZE_32KB)
 223 #define PM_HUGE_MASK    PM_64M
 224 #elif defined(CONFIG_PAGE_SIZE_64KB)
 225 #define PM_HUGE_MASK    PM_256M
 226 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 227 #error Bad page size configuration for hugetlbfs!
 228 #endif
 229
 230 /*
 231  * Wired register bits
 232  */
 233 #define MIPSR6_WIRED_LIMIT_SHIFT 16
 234 #define MIPSR6_WIRED_LIMIT      (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
 235 #define MIPSR6_WIRED_WIRED_SHIFT 0
 236 #define MIPSR6_WIRED_WIRED      (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
 237
 238 /*
 239  * Values used for computation of new tlb entries
 240  */
 241 #define PL_4K           12
 242 #define PL_16K          14
 243 #define PL_64K          16
 244 #define PL_256K         18
 245 #define PL_1M           20
 246 #define PL_4M           22
 247 #define PL_16M          24
 248 #define PL_64M          26
 249 #define PL_256M         28
 250
 251 /*
 252  * PageGrain bits
 253  */
 254 #define PG_RIE          (_ULCAST_(1) <<  31)
 255 #define PG_XIE          (_ULCAST_(1) <<  30)
 256 #define PG_ELPA         (_ULCAST_(1) <<  29)
 257 #define PG_ESP          (_ULCAST_(1) <<  28)
 258 #define PG_IEC          (_ULCAST_(1) <<  27)
 259
 260 /* MIPS32/64 EntryHI bit definitions */
 261 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 262 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 263 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 264
 265 /*
 266  * R4x00 interrupt enable / cause bits
 267  */
 268 #define IE_SW0          (_ULCAST_(1) <<  8)
 269 #define IE_SW1          (_ULCAST_(1) <<  9)
 270 #define IE_IRQ0         (_ULCAST_(1) << 10)
 271 #define IE_IRQ1         (_ULCAST_(1) << 11)
 272 #define IE_IRQ2         (_ULCAST_(1) << 12)
 273 #define IE_IRQ3         (_ULCAST_(1) << 13)
 274 #define IE_IRQ4         (_ULCAST_(1) << 14)
 275 #define IE_IRQ5         (_ULCAST_(1) << 15)
 276
 277 /*
 278  * R4x00 interrupt cause bits
 279  */
 280 #define C_SW0           (_ULCAST_(1) <<  8)
 281 #define C_SW1           (_ULCAST_(1) <<  9)
 282 #define C_IRQ0          (_ULCAST_(1) << 10)
 283 #define C_IRQ1          (_ULCAST_(1) << 11)
 284 #define C_IRQ2          (_ULCAST_(1) << 12)
 285 #define C_IRQ3          (_ULCAST_(1) << 13)
 286 #define C_IRQ4          (_ULCAST_(1) << 14)
 287 #define C_IRQ5          (_ULCAST_(1) << 15)
 288
 289 /*
 290  * Bitfields in the R4xx0 cp0 status register
 291  */
 292 #define ST0_IE                  0x00000001
 293 #define ST0_EXL                 0x00000002
 294 #define ST0_ERL                 0x00000004
 295 #define ST0_KSU                 0x00000018
 296 #  define KSU_USER              0x00000010
 297 #  define KSU_SUPERVISOR        0x00000008
 298 #  define KSU_KERNEL            0x00000000
 299 #define ST0_UX                  0x00000020
 300 #define ST0_SX                  0x00000040
 301 #define ST0_KX                  0x00000080
 302 #define ST0_DE                  0x00010000
 303 #define ST0_CE                  0x00020000
 304
 305 /*
 306  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 307  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 308  * processors.
 309  */
 310 #define ST0_CO                  0x08000000
 311
 312 /*
 313  * Bitfields in the R[23]000 cp0 status register.
 314  */
 315 #define ST0_IEC                 0x00000001
 316 #define ST0_KUC                 0x00000002
 317 #define ST0_IEP                 0x00000004
 318 #define ST0_KUP                 0x00000008
 319 #define ST0_IEO                 0x00000010
 320 #define ST0_KUO                 0x00000020
 321 /* bits 6 & 7 are reserved on R[23]000 */
 322 #define ST0_ISC                 0x00010000
 323 #define ST0_SWC                 0x00020000
 324 #define ST0_CM                  0x00080000
 325
 326 /*
 327  * Bits specific to the R4640/R4650
 328  */
 329 #define ST0_UM                  (_ULCAST_(1) <<  4)
 330 #define ST0_IL                  (_ULCAST_(1) << 23)
 331 #define ST0_DL                  (_ULCAST_(1) << 24)
 332
 333 /*
 334  * Enable the MIPS MDMX and DSP ASEs
 335  */
 336 #define ST0_MX                  0x01000000
 337
 338 /*
 339  * Status register bits available in all MIPS CPUs.
 340  */
 341 #define ST0_IM                  0x0000ff00
 342 #define  STATUSB_IP0            8
 343 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 344 #define  STATUSB_IP1            9
 345 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 346 #define  STATUSB_IP2            10
 347 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 348 #define  STATUSB_IP3            11
 349 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 350 #define  STATUSB_IP4            12
 351 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 352 #define  STATUSB_IP5            13
 353 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 354 #define  STATUSB_IP6            14
 355 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 356 #define  STATUSB_IP7            15
 357 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 358 #define  STATUSB_IP8            0
 359 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 360 #define  STATUSB_IP9            1
 361 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 362 #define  STATUSB_IP10           2
 363 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 364 #define  STATUSB_IP11           3
 365 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 366 #define  STATUSB_IP12           4
 367 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 368 #define  STATUSB_IP13           5
 369 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 370 #define  STATUSB_IP14           6
 371 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 372 #define  STATUSB_IP15           7
 373 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 374 #define ST0_CH                  0x00040000
 375 #define ST0_NMI                 0x00080000
 376 #define ST0_SR                  0x00100000
 377 #define ST0_TS                  0x00200000
 378 #define ST0_BEV                 0x00400000
 379 #define ST0_RE                  0x02000000
 380 #define ST0_FR                  0x04000000
 381 #define ST0_CU                  0xf0000000
 382 #define ST0_CU0                 0x10000000
 383 #define ST0_CU1                 0x20000000
 384 #define ST0_CU2                 0x40000000
 385 #define ST0_CU3                 0x80000000
 386 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 387
 388 /*
 389  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 390  */
 391 #define INTCTLB_IPFDC           23
 392 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 393 #define INTCTLB_IPPCI           26
 394 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 395 #define INTCTLB_IPTI            29
 396 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 397
 398 /*
 399  * Bitfields and bit numbers in the coprocessor 0 cause register.
 400  *
 401  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 402  */
 403 #define CAUSEB_EXCCODE          2
 404 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 405 #define CAUSEB_IP               8
 406 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 407 #define  CAUSEB_IP0             8
 408 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 409 #define  CAUSEB_IP1             9
 410 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 411 #define  CAUSEB_IP2             10
 412 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 413 #define  CAUSEB_IP3             11
 414 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 415 #define  CAUSEB_IP4             12
 416 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 417 #define  CAUSEB_IP5             13
 418 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 419 #define  CAUSEB_IP6             14
 420 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 421 #define  CAUSEB_IP7             15
 422 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 423 #define CAUSEB_FDCI             21
 424 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 425 #define CAUSEB_WP               22
 426 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 427 #define CAUSEB_IV               23
 428 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 429 #define CAUSEB_PCI              26
 430 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 431 #define CAUSEB_DC               27
 432 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 433 #define CAUSEB_CE               28
 434 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 435 #define CAUSEB_TI               30
 436 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 437 #define CAUSEB_BD               31
 438 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 439
 440 /*
 441  * Cause.ExcCode trap codes.
 442  */
 443 #define EXCCODE_INT             0       /* Interrupt pending */
 444 #define EXCCODE_MOD             1       /* TLB modified fault */
 445 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 446 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 447 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 448 #define EXCCODE_ADES            5       /* Address error on a store */
 449 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 450 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 451 #define EXCCODE_SYS             8       /* System call */
 452 #define EXCCODE_BP              9       /* Breakpoint */
 453 #define EXCCODE_RI              10      /* Reserved instruction exception */
 454 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 455 #define EXCCODE_OV              12      /* Arithmetic overflow */
 456 #define EXCCODE_TR              13      /* Trap instruction */
 457 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 458 #define EXCCODE_FPE             15      /* Floating point exception */
 459 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 460 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 461 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 462 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 463 #define EXCCODE_WATCH           23      /* Watch address reference */
 464 #define EXCCODE_MCHECK          24      /* Machine check */
 465 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 466 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 467 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 468
 469 /* Implementation specific trap codes used by MIPS cores */
 470 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 471
 472 /*
 473  * Bits in the coprocessor 0 config register.
 474  */
 475 /* Generic bits.  */
 476 #define CONF_CM_CACHABLE_NO_WA          0
 477 #define CONF_CM_CACHABLE_WA             1
 478 #define CONF_CM_UNCACHED                2
 479 #define CONF_CM_CACHABLE_NONCOHERENT    3
 480 #define CONF_CM_CACHABLE_CE             4
 481 #define CONF_CM_CACHABLE_COW            5
 482 #define CONF_CM_CACHABLE_CUW            6
 483 #define CONF_CM_CACHABLE_ACCELERATED    7
 484 #define CONF_CM_CMASK                   7
 485 #define CONF_BE                 (_ULCAST_(1) << 15)
 486
 487 /* Bits common to various processors.  */
 488 #define CONF_CU                 (_ULCAST_(1) <<  3)
 489 #define CONF_DB                 (_ULCAST_(1) <<  4)
 490 #define CONF_IB                 (_ULCAST_(1) <<  5)
 491 #define CONF_DC                 (_ULCAST_(7) <<  6)
 492 #define CONF_IC                 (_ULCAST_(7) <<  9)
 493 #define CONF_EB                 (_ULCAST_(1) << 13)
 494 #define CONF_EM                 (_ULCAST_(1) << 14)
 495 #define CONF_SM                 (_ULCAST_(1) << 16)
 496 #define CONF_SC                 (_ULCAST_(1) << 17)
 497 #define CONF_EW                 (_ULCAST_(3) << 18)
 498 #define CONF_EP                 (_ULCAST_(15)<< 24)
 499 #define CONF_EC                 (_ULCAST_(7) << 28)
 500 #define CONF_CM                 (_ULCAST_(1) << 31)
 501
 502 /* Bits specific to the R4xx0.  */
 503 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 504 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 505 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 506
 507 /* Bits specific to the R5000.  */
 508 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 509 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 510
 511 /* Bits specific to the RM7000.  */
 512 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 513 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 514 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 515 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 516 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 517 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 518
 519 /* Bits specific to the R10000.  */
 520 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 521 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 522 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 523 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 524 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 525 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 526 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 527 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 528 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 529 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 530 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 531
 532 /* Bits specific to the VR41xx.  */
 533 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 534 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 535 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 536 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 537 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 538
 539 /* Bits specific to the R30xx.  */
 540 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 541 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 542 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 543 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 544 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 545 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 546 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 547 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 548 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 549
 550 /* Bits specific to the TX49.  */
 551 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 552 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 553 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 554 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 555
 556 /* Bits specific to the MIPS32/64 PRA.  */
 557 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 558 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 559 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 560 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 561 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 562 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 563 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 564
 565 /*
 566  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 567  */
 568 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 569 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 570 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 571 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 572 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 573 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 574 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 575 #define MIPS_CONF1_DA_SHF       7
 576 #define MIPS_CONF1_DA_SZ        3
 577 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 578 #define MIPS_CONF1_DL_SHF       10
 579 #define MIPS_CONF1_DL_SZ        3
 580 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 581 #define MIPS_CONF1_DS_SHF       13
 582 #define MIPS_CONF1_DS_SZ        3
 583 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 584 #define MIPS_CONF1_IA_SHF       16
 585 #define MIPS_CONF1_IA_SZ        3
 586 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 587 #define MIPS_CONF1_IL_SHF       19
 588 #define MIPS_CONF1_IL_SZ        3
 589 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 590 #define MIPS_CONF1_IS_SHF       22
 591 #define MIPS_CONF1_IS_SZ        3
 592 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 593 #define MIPS_CONF1_TLBS_SHIFT   (25)
 594 #define MIPS_CONF1_TLBS_SIZE    (6)
 595 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 596
 597 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 598 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 599 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 600 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 601 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 602 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 603 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 604 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 605
 606 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 607 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 608 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 609 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 610 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 611 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 612 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 613 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 614 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 615 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 616 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 617 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 618 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 619 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 620 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 621 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 622 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 623 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 624 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 625 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 626 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 627 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 628 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 629 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 630 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 631 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 632 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 633
 634 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 635 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 636 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 637 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 638 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 639 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 640 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 641 /* bits 10:8 in FTLB-only configurations */
 642 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 643 /* bits 12:8 in VTLB-FTLB only configurations */
 644 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 645 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 646 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 647 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 648 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 649 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 650 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 651 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 652 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 653 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 654 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 655 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 656
 657 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 658 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 659 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 660 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 661 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 662 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 663 #define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
 664 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 665 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 666 #define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
 667 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 668 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 669 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 670 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 671
 672 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 673 /* proAptiv FTLB on/off bit */
 674 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 675 /* Loongson-3 FTLB on/off bit */
 676 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 677 /* FTLB probability bits */
 678 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 679
 680 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 681
 682 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 683
 684 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 685 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 686
 687 /* WatchLo* register definitions */
 688 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 689
 690 /* WatchHi* register definitions */
 691 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 692 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 693 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 694 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 695 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 696 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 697 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 698 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 699 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 700 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 701 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 702 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 703 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 704
 705 /* PerfCnt control register definitions */
 706 #define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
 707 #define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
 708 #define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
 709 #define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
 710 #define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
 711 #define MIPS_PERFCTRL_EVENT_S   5
 712 #define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 713 #define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
 714 #define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
 715 #define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
 716 #define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
 717 #define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
 718 #define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
 719 #define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
 720 #define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
 721
 722 /* PerfCnt control register MT extensions used by MIPS cores */
 723 #define MIPS_PERFCTRL_VPEID_S   16
 724 #define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 725 #define MIPS_PERFCTRL_TCID_S    22
 726 #define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 727 #define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
 728 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
 729 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
 730 #define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
 731
 732 /* PerfCnt control register MT extensions used by BMIPS5000 */
 733 #define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
 734
 735 /* PerfCnt control register MT extensions used by Netlogic XLR */
 736 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
 737
 738 /* MAAR bit definitions */
 739 #define MIPS_MAAR_VH            (_U64CAST_(1) << 63)
 740 #define MIPS_MAAR_ADDR          GENMASK_ULL(55, 12)
 741 #define MIPS_MAAR_ADDR_SHIFT    12
 742 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 743 #define MIPS_MAAR_VL            (_ULCAST_(1) << 0)
 744
 745 /* MAARI bit definitions */
 746 #define MIPS_MAARI_INDEX        (_ULCAST_(0x3f) << 0)
 747
 748 /* EBase bit definitions */
 749 #define MIPS_EBASE_CPUNUM_SHIFT 0
 750 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 751 #define MIPS_EBASE_WG_SHIFT     11
 752 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 753 #define MIPS_EBASE_BASE_SHIFT   12
 754 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 755
 756 /* CMGCRBase bit definitions */
 757 #define MIPS_CMGCRB_BASE        11
 758 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 759
 760 /* LLAddr bit definitions */
 761 #define MIPS_LLADDR_LLB_SHIFT   0
 762 #define MIPS_LLADDR_LLB         (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 763
 764 /*
 765  * Bits in the MIPS32 Memory Segmentation registers.
 766  */
 767 #define MIPS_SEGCFG_PA_SHIFT    9
 768 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 769 #define MIPS_SEGCFG_AM_SHIFT    4
 770 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 771 #define MIPS_SEGCFG_EU_SHIFT    3
 772 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 773 #define MIPS_SEGCFG_C_SHIFT     0
 774 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 775
 776 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 777 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 778 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 779 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 780 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 781 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 782 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 783
 784 #define MIPS_PWFIELD_GDI_SHIFT  24
 785 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 786 #define MIPS_PWFIELD_UDI_SHIFT  18
 787 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 788 #define MIPS_PWFIELD_MDI_SHIFT  12
 789 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 790 #define MIPS_PWFIELD_PTI_SHIFT  6
 791 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 792 #define MIPS_PWFIELD_PTEI_SHIFT 0
 793 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 794
 795 #define MIPS_PWSIZE_PS_SHIFT    30
 796 #define MIPS_PWSIZE_PS_MASK     0x40000000
 797 #define MIPS_PWSIZE_GDW_SHIFT   24
 798 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 799 #define MIPS_PWSIZE_UDW_SHIFT   18
 800 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 801 #define MIPS_PWSIZE_MDW_SHIFT   12
 802 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 803 #define MIPS_PWSIZE_PTW_SHIFT   6
 804 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 805 #define MIPS_PWSIZE_PTEW_SHIFT  0
 806 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 807
 808 #define MIPS_PWCTL_PWEN_SHIFT   31
 809 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 810 #define MIPS_PWCTL_XK_SHIFT     28
 811 #define MIPS_PWCTL_XK_MASK      0x10000000
 812 #define MIPS_PWCTL_XS_SHIFT     27
 813 #define MIPS_PWCTL_XS_MASK      0x08000000
 814 #define MIPS_PWCTL_XU_SHIFT     26
 815 #define MIPS_PWCTL_XU_MASK      0x04000000
 816 #define MIPS_PWCTL_DPH_SHIFT    7
 817 #define MIPS_PWCTL_DPH_MASK     0x00000080
 818 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 819 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 820 #define MIPS_PWCTL_PSN_SHIFT    0
 821 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 822
 823 /* GuestCtl0 fields */
 824 #define MIPS_GCTL0_GM_SHIFT     31
 825 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 826 #define MIPS_GCTL0_RI_SHIFT     30
 827 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 828 #define MIPS_GCTL0_MC_SHIFT     29
 829 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 830 #define MIPS_GCTL0_CP0_SHIFT    28
 831 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 832 #define MIPS_GCTL0_AT_SHIFT     26
 833 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 834 #define MIPS_GCTL0_GT_SHIFT     25
 835 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 836 #define MIPS_GCTL0_CG_SHIFT     24
 837 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 838 #define MIPS_GCTL0_CF_SHIFT     23
 839 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 840 #define MIPS_GCTL0_G1_SHIFT     22
 841 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 842 #define MIPS_GCTL0_G0E_SHIFT    19
 843 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 844 #define MIPS_GCTL0_PT_SHIFT     18
 845 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 846 #define MIPS_GCTL0_RAD_SHIFT    9
 847 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 848 #define MIPS_GCTL0_DRG_SHIFT    8
 849 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 850 #define MIPS_GCTL0_G2_SHIFT     7
 851 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 852 #define MIPS_GCTL0_GEXC_SHIFT   2
 853 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 854 #define MIPS_GCTL0_SFC2_SHIFT   1
 855 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 856 #define MIPS_GCTL0_SFC1_SHIFT   0
 857 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 858
 859 /* GuestCtl0.AT Guest address translation control */
 860 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 861 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 862
 863 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 864 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 865 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 866 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 867 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 868 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 869 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 870 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 871
 872 /* GuestCtl0Ext fields */
 873 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 874 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 875 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 876 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 877 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 878 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 879 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 880 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 881 #define MIPS_GCTL0EXT_OG_SHIFT  2
 882 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 883 #define MIPS_GCTL0EXT_BG_SHIFT  1
 884 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 885 #define MIPS_GCTL0EXT_MG_SHIFT  0
 886 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 887
 888 /* GuestCtl0Ext.RPW Root page walk configuration */
 889 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 890 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 891 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 892
 893 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 894 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 895 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 896
 897 /* GuestCtl1 fields */
 898 #define MIPS_GCTL1_ID_SHIFT     0
 899 #define MIPS_GCTL1_ID_WIDTH     8
 900 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 901 #define MIPS_GCTL1_RID_SHIFT    16
 902 #define MIPS_GCTL1_RID_WIDTH    8
 903 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 904 #define MIPS_GCTL1_EID_SHIFT    24
 905 #define MIPS_GCTL1_EID_WIDTH    8
 906 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 907
 908 /* GuestID reserved for root context */
 909 #define MIPS_GCTL1_ROOT_GUESTID 0
 910
 911 /* CDMMBase register bit definitions */
 912 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 913 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 914 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 915 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 916 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 917 #define MIPS_CDMMBASE_ADDR_START 15
 918
 919 /* RDHWR register numbers */
 920 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 921 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 922 #define MIPS_HWR_CC             2       /* Cycle counter */
 923 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 924 #define MIPS_HWR_ULR            29      /* UserLocal */
 925 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 926 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 927
 928 /* Bits in HWREna register */
 929 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 930 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 931 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 932 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 933 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 934 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 935 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 936
 937 /*
 938  * Bitfields in the TX39 family CP0 Configuration Register 3
 939  */
 940 #define TX39_CONF_ICS_SHIFT     19
 941 #define TX39_CONF_ICS_MASK      0x00380000
 942 #define TX39_CONF_ICS_1KB       0x00000000
 943 #define TX39_CONF_ICS_2KB       0x00080000
 944 #define TX39_CONF_ICS_4KB       0x00100000
 945 #define TX39_CONF_ICS_8KB       0x00180000
 946 #define TX39_CONF_ICS_16KB      0x00200000
 947
 948 #define TX39_CONF_DCS_SHIFT     16
 949 #define TX39_CONF_DCS_MASK      0x00070000
 950 #define TX39_CONF_DCS_1KB       0x00000000
 951 #define TX39_CONF_DCS_2KB       0x00010000
 952 #define TX39_CONF_DCS_4KB       0x00020000
 953 #define TX39_CONF_DCS_8KB       0x00030000
 954 #define TX39_CONF_DCS_16KB      0x00040000
 955
 956 #define TX39_CONF_CWFON         0x00004000
 957 #define TX39_CONF_WBON          0x00002000
 958 #define TX39_CONF_RF_SHIFT      10
 959 #define TX39_CONF_RF_MASK       0x00000c00
 960 #define TX39_CONF_DOZE          0x00000200
 961 #define TX39_CONF_HALT          0x00000100
 962 #define TX39_CONF_LOCK          0x00000080
 963 #define TX39_CONF_ICE           0x00000020
 964 #define TX39_CONF_DCE           0x00000010
 965 #define TX39_CONF_IRSIZE_SHIFT  2
 966 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 967 #define TX39_CONF_DRSIZE_SHIFT  0
 968 #define TX39_CONF_DRSIZE_MASK   0x00000003
 969
 970 /*
 971  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 972  */
 973 /* Disable Branch Target Address Cache */
 974 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 975 /* Enable Branch Prediction Global History */
 976 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 977 /* Disable Branch Return Cache */
 978 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 979
 980 /* Flush ITLB */
 981 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 982 /* Flush DTLB */
 983 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 984 /* Flush VTLB */
 985 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 986 /* Flush FTLB */
 987 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 988
 989 /* CvmCtl register field definitions */
 990 #define CVMCTL_IPPCI_SHIFT      7
 991 #define CVMCTL_IPPCI            (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
 992 #define CVMCTL_IPTI_SHIFT       4
 993 #define CVMCTL_IPTI             (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
 994
 995 /* CvmMemCtl2 register field definitions */
 996 #define CVMMEMCTL2_INHIBITTS    (_U64CAST_(1) << 17)
 997
 998 /* CvmVMConfig register field definitions */
 999 #define CVMVMCONF_DGHT          (_U64CAST_(1) << 60)
1000 #define CVMVMCONF_MMUSIZEM1_S   12
1001 #define CVMVMCONF_MMUSIZEM1     (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1002 #define CVMVMCONF_RMMUSIZEM1_S  0
1003 #define CVMVMCONF_RMMUSIZEM1    (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1004
1005 /*
1006  * Coprocessor 1 (FPU) register names
1007  */
1008 #define CP1_REVISION    $0
1009 #define CP1_UFR         $1
1010 #define CP1_UNFR        $4
1011 #define CP1_FCCR        $25
1012 #define CP1_FEXR        $26
1013 #define CP1_FENR        $28
1014 #define CP1_STATUS      $31
1015
1016
1017 /*
1018  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1019  */
1020 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
1021 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
1022 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
1023 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
1024 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
1025 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
1026 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
1027 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
1028 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
1029 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
1030
1031 /*
1032  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1033  */
1034 #define MIPS_FCCR_CONDX_S       0
1035 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1036 #define MIPS_FCCR_COND0_S       0
1037 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1038 #define MIPS_FCCR_COND1_S       1
1039 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1040 #define MIPS_FCCR_COND2_S       2
1041 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1042 #define MIPS_FCCR_COND3_S       3
1043 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1044 #define MIPS_FCCR_COND4_S       4
1045 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1046 #define MIPS_FCCR_COND5_S       5
1047 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1048 #define MIPS_FCCR_COND6_S       6
1049 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1050 #define MIPS_FCCR_COND7_S       7
1051 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1052
1053 /*
1054  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1055  */
1056 #define MIPS_FENR_FS_S          2
1057 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
1058
1059 /*
1060  * FPU Status Register Values
1061  */
1062 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
1063 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
1064
1065 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
1066 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
1067
1068 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
1069 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
1070 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
1071 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
1072 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
1073 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
1074 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
1075 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
1076 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
1077 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1078 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1079 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1080 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1081 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1082 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1083 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1084
1085 /*
1086  * Bits 22:20 of the FPU Status Register will be read as 0,
1087  * and should be written as zero.
1088  */
1089 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1090
1091 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1092 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1093
1094 /*
1095  * X the exception cause indicator
1096  * E the exception enable
1097  * S the sticky/flag bit
1098 */
1099 #define FPU_CSR_ALL_X   0x0003f000
1100 #define FPU_CSR_UNI_X   0x00020000
1101 #define FPU_CSR_INV_X   0x00010000
1102 #define FPU_CSR_DIV_X   0x00008000
1103 #define FPU_CSR_OVF_X   0x00004000
1104 #define FPU_CSR_UDF_X   0x00002000
1105 #define FPU_CSR_INE_X   0x00001000
1106
1107 #define FPU_CSR_ALL_E   0x00000f80
1108 #define FPU_CSR_INV_E   0x00000800
1109 #define FPU_CSR_DIV_E   0x00000400
1110 #define FPU_CSR_OVF_E   0x00000200
1111 #define FPU_CSR_UDF_E   0x00000100
1112 #define FPU_CSR_INE_E   0x00000080
1113
1114 #define FPU_CSR_ALL_S   0x0000007c
1115 #define FPU_CSR_INV_S   0x00000040
1116 #define FPU_CSR_DIV_S   0x00000020
1117 #define FPU_CSR_OVF_S   0x00000010
1118 #define FPU_CSR_UDF_S   0x00000008
1119 #define FPU_CSR_INE_S   0x00000004
1120
1121 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1122 #define FPU_CSR_RM      0x00000003
1123 #define FPU_CSR_RN      0x0     /* nearest */
1124 #define FPU_CSR_RZ      0x1     /* towards zero */
1125 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1126 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1127
1128
1129 #ifndef __ASSEMBLY__
1130
1131 /*
1132  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1133  */
1134 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1135     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1136 #define get_isa16_mode(x)               ((x) & 0x1)
1137 #define msk_isa16_mode(x)               ((x) & ~0x1)
1138 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1139 #else
1140 #define get_isa16_mode(x)               0
1141 #define msk_isa16_mode(x)               (x)
1142 #define set_isa16_mode(x)               do { } while(0)
1143 #endif
1144
1145 /*
1146  * microMIPS instructions can be 16-bit or 32-bit in length. This
1147  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1148  */
1149 static inline int mm_insn_16bit(u16 insn)
1150 {
1151         u16 opcode = (insn >> 10) & 0x7;
1152
1153         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1154 }
1155
1156 /*
1157  * Helper macros for generating raw instruction encodings in inline asm.
1158  */
1159 #ifdef CONFIG_CPU_MICROMIPS
1160 #define _ASM_INSN16_IF_MM(_enc)                 \
1161         ".insn\n\t"                             \
1162         ".hword (" #_enc ")\n\t"
1163 #define _ASM_INSN32_IF_MM(_enc)                 \
1164         ".insn\n\t"                             \
1165         ".hword ((" #_enc ") >> 16)\n\t"        \
1166         ".hword ((" #_enc ") & 0xffff)\n\t"
1167 #else
1168 #define _ASM_INSN_IF_MIPS(_enc)                 \
1169         ".insn\n\t"                             \
1170         ".word (" #_enc ")\n\t"
1171 #endif
1172
1173 #ifndef _ASM_INSN16_IF_MM
1174 #define _ASM_INSN16_IF_MM(_enc)
1175 #endif
1176 #ifndef _ASM_INSN32_IF_MM
1177 #define _ASM_INSN32_IF_MM(_enc)
1178 #endif
1179 #ifndef _ASM_INSN_IF_MIPS
1180 #define _ASM_INSN_IF_MIPS(_enc)
1181 #endif
1182
1183 /*
1184  * TLB Invalidate Flush
1185  */
1186 static inline void tlbinvf(void)
1187 {
1188         __asm__ __volatile__(
1189                 ".set push\n\t"
1190                 ".set noreorder\n\t"
1191                 "# tlbinvf\n\t"
1192                 _ASM_INSN_IF_MIPS(0x42000004)
1193                 _ASM_INSN32_IF_MM(0x0000537c)
1194                 ".set pop");
1195 }
1196
1197
1198 /*
1199  * Functions to access the R10000 performance counters.  These are basically
1200  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1201  * performance counter number encoded into bits 1 ... 5 of the instruction.
1202  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1203  * disassembler these will look like an access to sel 0 or 1.
1204  */
1205 #define read_r10k_perf_cntr(counter)                            \
1206 ({                                                              \
1207         unsigned int __res;                                     \
1208         __asm__ __volatile__(                                   \
1209         "mfpc\t%0, %1"                                          \
1210         : "=r" (__res)                                          \
1211         : "i" (counter));                                       \
1212                                                                 \
1213         __res;                                                  \
1214 })
1215
1216 #define write_r10k_perf_cntr(counter,val)                       \
1217 do {                                                            \
1218         __asm__ __volatile__(                                   \
1219         "mtpc\t%0, %1"                                          \
1220         :                                                       \
1221         : "r" (val), "i" (counter));                            \
1222 } while (0)
1223
1224 #define read_r10k_perf_event(counter)                           \
1225 ({                                                              \
1226         unsigned int __res;                                     \
1227         __asm__ __volatile__(                                   \
1228         "mfps\t%0, %1"                                          \
1229         : "=r" (__res)                                          \
1230         : "i" (counter));                                       \
1231                                                                 \
1232         __res;                                                  \
1233 })
1234
1235 #define write_r10k_perf_cntl(counter,val)                       \
1236 do {                                                            \
1237         __asm__ __volatile__(                                   \
1238         "mtps\t%0, %1"                                          \
1239         :                                                       \
1240         : "r" (val), "i" (counter));                            \
1241 } while (0)
1242
1243
1244 /*
1245  * Macros to access the system control coprocessor
1246  */
1247
1248 #define __read_32bit_c0_register(source, sel)                           \
1249 ({ unsigned int __res;                                                  \
1250         if (sel == 0)                                                   \
1251                 __asm__ __volatile__(                                   \
1252                         "mfc0\t%0, " #source "\n\t"                     \
1253                         : "=r" (__res));                                \
1254         else                                                            \
1255                 __asm__ __volatile__(                                   \
1256                         ".set\tmips32\n\t"                              \
1257                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1258                         ".set\tmips0\n\t"                               \
1259                         : "=r" (__res));                                \
1260         __res;                                                          \
1261 })
1262
1263 #define __read_64bit_c0_register(source, sel)                           \
1264 ({ unsigned long long __res;                                            \
1265         if (sizeof(unsigned long) == 4)                                 \
1266                 __res = __read_64bit_c0_split(source, sel);             \
1267         else if (sel == 0)                                              \
1268                 __asm__ __volatile__(                                   \
1269                         ".set\tmips3\n\t"                               \
1270                         "dmfc0\t%0, " #source "\n\t"                    \
1271                         ".set\tmips0"                                   \
1272                         : "=r" (__res));                                \
1273         else                                                            \
1274                 __asm__ __volatile__(                                   \
1275                         ".set\tmips64\n\t"                              \
1276                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1277                         ".set\tmips0"                                   \
1278                         : "=r" (__res));                                \
1279         __res;                                                          \
1280 })
1281
1282 #define __write_32bit_c0_register(register, sel, value)                 \
1283 do {                                                                    \
1284         if (sel == 0)                                                   \
1285                 __asm__ __volatile__(                                   \
1286                         "mtc0\t%z0, " #register "\n\t"                  \
1287                         : : "Jr" ((unsigned int)(value)));              \
1288         else                                                            \
1289                 __asm__ __volatile__(                                   \
1290                         ".set\tmips32\n\t"                              \
1291                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1292                         ".set\tmips0"                                   \
1293                         : : "Jr" ((unsigned int)(value)));              \
1294 } while (0)
1295
1296 #define __write_64bit_c0_register(register, sel, value)                 \
1297 do {                                                                    \
1298         if (sizeof(unsigned long) == 4)                                 \
1299                 __write_64bit_c0_split(register, sel, value);           \
1300         else if (sel == 0)                                              \
1301                 __asm__ __volatile__(                                   \
1302                         ".set\tmips3\n\t"                               \
1303                         "dmtc0\t%z0, " #register "\n\t"                 \
1304                         ".set\tmips0"                                   \
1305                         : : "Jr" (value));                              \
1306         else                                                            \
1307                 __asm__ __volatile__(                                   \
1308                         ".set\tmips64\n\t"                              \
1309                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1310                         ".set\tmips0"                                   \
1311                         : : "Jr" (value));                              \
1312 } while (0)
1313
1314 #define __read_ulong_c0_register(reg, sel)                              \
1315         ((sizeof(unsigned long) == 4) ?                                 \
1316         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1317         (unsigned long) __read_64bit_c0_register(reg, sel))
1318
1319 #define __write_ulong_c0_register(reg, sel, val)                        \
1320 do {                                                                    \
1321         if (sizeof(unsigned long) == 4)                                 \
1322                 __write_32bit_c0_register(reg, sel, val);               \
1323         else                                                            \
1324                 __write_64bit_c0_register(reg, sel, val);               \
1325 } while (0)
1326
1327 /*
1328  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1329  */
1330 #define __read_32bit_c0_ctrl_register(source)                           \
1331 ({ unsigned int __res;                                                  \
1332         __asm__ __volatile__(                                           \
1333                 "cfc0\t%0, " #source "\n\t"                             \
1334                 : "=r" (__res));                                        \
1335         __res;                                                          \
1336 })
1337
1338 #define __write_32bit_c0_ctrl_register(register, value)                 \
1339 do {                                                                    \
1340         __asm__ __volatile__(                                           \
1341                 "ctc0\t%z0, " #register "\n\t"                          \
1342                 : : "Jr" ((unsigned int)(value)));                      \
1343 } while (0)
1344
1345 /*
1346  * These versions are only needed for systems with more than 38 bits of
1347  * physical address space running the 32-bit kernel.  That's none atm :-)
1348  */
1349 #define __read_64bit_c0_split(source, sel)                              \
1350 ({                                                                      \
1351         unsigned long long __val;                                       \
1352         unsigned long __flags;                                          \
1353                                                                         \
1354         local_irq_save(__flags);                                        \
1355         if (sel == 0)                                                   \
1356                 __asm__ __volatile__(                                   \
1357                         ".set\tmips64\n\t"                              \
1358                         "dmfc0\t%M0, " #source "\n\t"                   \
1359                         "dsll\t%L0, %M0, 32\n\t"                        \
1360                         "dsra\t%M0, %M0, 32\n\t"                        \
1361                         "dsra\t%L0, %L0, 32\n\t"                        \
1362                         ".set\tmips0"                                   \
1363                         : "=r" (__val));                                \
1364         else                                                            \
1365                 __asm__ __volatile__(                                   \
1366                         ".set\tmips64\n\t"                              \
1367                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1368                         "dsll\t%L0, %M0, 32\n\t"                        \
1369                         "dsra\t%M0, %M0, 32\n\t"                        \
1370                         "dsra\t%L0, %L0, 32\n\t"                        \
1371                         ".set\tmips0"                                   \
1372                         : "=r" (__val));                                \
1373         local_irq_restore(__flags);                                     \
1374                                                                         \
1375         __val;                                                          \
1376 })
1377
1378 #define __write_64bit_c0_split(source, sel, val)                        \
1379 do {                                                                    \
1380         unsigned long long __tmp;                                       \
1381         unsigned long __flags;                                          \
1382                                                                         \
1383         local_irq_save(__flags);                                        \
1384         if (sel == 0)                                                   \
1385                 __asm__ __volatile__(                                   \
1386                         ".set\tmips64\n\t"                              \
1387                         "dsll\t%L0, %L1, 32\n\t"                        \
1388                         "dsrl\t%L0, %L0, 32\n\t"                        \
1389                         "dsll\t%M0, %M1, 32\n\t"                        \
1390                         "or\t%L0, %L0, %M0\n\t"                         \
1391                         "dmtc0\t%L0, " #source "\n\t"                   \
1392                         ".set\tmips0"                                   \
1393                         : "=&r,r" (__tmp)                               \
1394                         : "r,0" (val));                                 \
1395         else                                                            \
1396                 __asm__ __volatile__(                                   \
1397                         ".set\tmips64\n\t"                              \
1398                         "dsll\t%L0, %L1, 32\n\t"                        \
1399                         "dsrl\t%L0, %L0, 32\n\t"                        \
1400                         "dsll\t%M0, %M1, 32\n\t"                        \
1401                         "or\t%L0, %L0, %M0\n\t"                         \
1402                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1403                         ".set\tmips0"                                   \
1404                         : "=&r,r" (__tmp)                               \
1405                         : "r,0" (val));                                 \
1406         local_irq_restore(__flags);                                     \
1407 } while (0)
1408
1409 #define __readx_32bit_c0_register(source)                               \
1410 ({                                                                      \
1411         unsigned int __res;                                             \
1412                                                                         \
1413         __asm__ __volatile__(                                           \
1414         "       .set    push                                    \n"     \
1415         "       .set    noat                                    \n"     \
1416         "       .set    mips32r2                                \n"     \
1417         "       # mfhc0 $1, %1                                  \n"     \
1418         _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11))             \
1419         _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16))             \
1420         "       move    %0, $1                                  \n"     \
1421         "       .set    pop                                     \n"     \
1422         : "=r" (__res)                                                  \
1423         : "i" (source));                                                \
1424         __res;                                                          \
1425 })
1426
1427 #define __writex_32bit_c0_register(register, value)                     \
1428 do {                                                                    \
1429         __asm__ __volatile__(                                           \
1430         "       .set    push                                    \n"     \
1431         "       .set    noat                                    \n"     \
1432         "       .set    mips32r2                                \n"     \
1433         "       move    $1, %0                                  \n"     \
1434         "       # mthc0 $1, %1                                  \n"     \
1435         _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11))             \
1436         _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16))             \
1437         "       .set    pop                                     \n"     \
1438         :                                                               \
1439         : "r" (value), "i" (register));                                 \
1440 } while (0)
1441
1442 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1443 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1444
1445 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1446 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1447
1448 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1449 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1450
1451 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1452 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1453
1454 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1455 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1456
1457 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1458 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1459
1460 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1461 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1462
1463 #define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
1464
1465 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1466 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1467
1468 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1469 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1470
1471 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1472 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1473
1474 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1475 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1476
1477 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1478 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1479
1480 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1481 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1482
1483 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1484 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1485
1486 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1487
1488 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1489 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1490
1491 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1492 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1493
1494 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1495 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1496
1497 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1498 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1499
1500 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1501 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1502
1503 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1504 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1505
1506 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1507 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1508
1509 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1510 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1511
1512 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1513 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1514
1515 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1516 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1517
1518 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1519 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1520
1521 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1522 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1523
1524 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1525 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1526
1527 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1528 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1529
1530 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1531
1532 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1533
1534 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1535 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1536
1537 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1538 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1539
1540 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1541 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1542
1543 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1544 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1545
1546 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1547
1548 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1549
1550 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1551 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1552 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1553 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1554 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1555 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1556 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1557 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1558 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1559 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1560 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1561 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1562 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1563 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1564 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1565 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1566
1567 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1568 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1569 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1570 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1571 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1572 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1573
1574 /*
1575  * The WatchLo register.  There may be up to 8 of them.
1576  */
1577 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1578 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1579 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1580 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1581 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1582 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1583 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1584 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1585 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1586 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1587 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1588 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1589 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1590 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1591 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1592 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1593
1594 /*
1595  * The WatchHi register.  There may be up to 8 of them.
1596  */
1597 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1598 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1599 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1600 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1601 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1602 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1603 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1604 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1605
1606 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1607 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1608 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1609 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1610 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1611 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1612 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1613 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1614
1615 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1616 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1617
1618 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1619 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1620
1621 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1622 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1623
1624 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1625 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1626
1627 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1628 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1629 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1630
1631 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1632 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1633
1634 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1635 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1636
1637 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1638 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1639
1640 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1641 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1642
1643 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1644 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1645
1646 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1647 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1648
1649 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1650 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1651
1652 /*
1653  * MIPS32 / MIPS64 performance counters
1654  */
1655 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1656 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1657 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1658 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1659 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1660 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1661 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1662 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1663 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1664 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1665 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1666 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1667 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1668 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1669 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1670 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1671 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1672 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1673 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1674 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1675 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1676 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1677 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1678 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1679
1680 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1681 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1682
1683 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1684 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1685
1686 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1687
1688 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1689 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1690
1691 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1692 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1693
1694 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1695 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1696
1697 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1698 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1699
1700 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1701 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1702
1703 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1704 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1705
1706 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1707 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1708
1709 /* MIPSR2 */
1710 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1711 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1712
1713 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1714 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1715
1716 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1717 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1718
1719 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1720 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1721
1722 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1723 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1724
1725 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1726 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1727
1728 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1729 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1730
1731 /* MIPSR3 */
1732 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1733 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1734
1735 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1736 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1737
1738 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1739 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1740
1741 /* Hardware Page Table Walker */
1742 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1743 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1744
1745 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1746 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1747
1748 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1749 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1750
1751 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1752 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1753
1754 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1755 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1756
1757 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1758 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1759
1760 /* Cavium OCTEON (cnMIPS) */
1761 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1762 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1763
1764 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1765 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1766
1767 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1768 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1769
1770 #define read_c0_cvmmemctl2()    __read_64bit_c0_register($16, 6)
1771 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1772
1773 #define read_c0_cvmvmconfig()   __read_64bit_c0_register($16, 7)
1774 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1775
1776 /*
1777  * The cacheerr registers are not standardized.  On OCTEON, they are
1778  * 64 bits wide.
1779  */
1780 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1781 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1782
1783 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1784 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1785
1786 /* BMIPS3300 */
1787 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1788 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1789
1790 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1791 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1792
1793 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1794 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1795
1796 /* BMIPS43xx */
1797 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1798 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1799
1800 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1801 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1802
1803 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1804 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1805
1806 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1807 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1808
1809 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1810 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1811
1812 /* BMIPS5000 */
1813 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1814 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1815
1816 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1817 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1818
1819 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1820 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1821
1822 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1823 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1824
1825 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1826 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1827
1828 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1829 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1830
1831 /*
1832  * Macros to access the guest system control coprocessor
1833  */
1834
1835 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1836
1837 #define __read_32bit_gc0_register(source, sel)                          \
1838 ({ int __res;                                                           \
1839         __asm__ __volatile__(                                           \
1840                 ".set\tpush\n\t"                                        \
1841                 ".set\tmips32r2\n\t"                                    \
1842                 ".set\tvirt\n\t"                                        \
1843                 "mfgc0\t%0, $%1, %2\n\t"                                \
1844                 ".set\tpop"                                             \
1845                 : "=r" (__res)                                          \
1846                 : "i" (source), "i" (sel));                             \
1847         __res;                                                          \
1848 })
1849
1850 #define __read_64bit_gc0_register(source, sel)                          \
1851 ({ unsigned long long __res;                                            \
1852         __asm__ __volatile__(                                           \
1853                 ".set\tpush\n\t"                                        \
1854                 ".set\tmips64r2\n\t"                                    \
1855                 ".set\tvirt\n\t"                                        \
1856                 "dmfgc0\t%0, $%1, %2\n\t"                       \
1857                 ".set\tpop"                                             \
1858                 : "=r" (__res)                                          \
1859                 : "i" (source), "i" (sel));                             \
1860         __res;                                                          \
1861 })
1862
1863 #define __write_32bit_gc0_register(register, sel, value)                \
1864 do {                                                                    \
1865         __asm__ __volatile__(                                           \
1866                 ".set\tpush\n\t"                                        \
1867                 ".set\tmips32r2\n\t"                                    \
1868                 ".set\tvirt\n\t"                                        \
1869                 "mtgc0\t%z0, $%1, %2\n\t"                               \
1870                 ".set\tpop"                                             \
1871                 : : "Jr" ((unsigned int)(value)),                       \
1872                     "i" (register), "i" (sel));                         \
1873 } while (0)
1874
1875 #define __write_64bit_gc0_register(register, sel, value)                \
1876 do {                                                                    \
1877         __asm__ __volatile__(                                           \
1878                 ".set\tpush\n\t"                                        \
1879                 ".set\tmips64r2\n\t"                                    \
1880                 ".set\tvirt\n\t"                                        \
1881                 "dmtgc0\t%z0, $%1, %2\n\t"                              \
1882                 ".set\tpop"                                             \
1883                 : : "Jr" (value),                                       \
1884                     "i" (register), "i" (sel));                         \
1885 } while (0)
1886
1887 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
1888
1889 #define __read_32bit_gc0_register(source, sel)                          \
1890 ({ int __res;                                                           \
1891         __asm__ __volatile__(                                           \
1892                 ".set\tpush\n\t"                                        \
1893                 ".set\tnoat\n\t"                                        \
1894                 "# mfgc0\t$1, $%1, %2\n\t"                              \
1895                 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2)           \
1896                 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11)     \
1897                 "move\t%0, $1\n\t"                                      \
1898                 ".set\tpop"                                             \
1899                 : "=r" (__res)                                          \
1900                 : "i" (source), "i" (sel));                             \
1901         __res;                                                          \
1902 })
1903
1904 #define __read_64bit_gc0_register(source, sel)                          \
1905 ({ unsigned long long __res;                                            \
1906         __asm__ __volatile__(                                           \
1907                 ".set\tpush\n\t"                                        \
1908                 ".set\tnoat\n\t"                                        \
1909                 "# dmfgc0\t$1, $%1, %2\n\t"                             \
1910                 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2)           \
1911                 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11)     \
1912                 "move\t%0, $1\n\t"                                      \
1913                 ".set\tpop"                                             \
1914                 : "=r" (__res)                                          \
1915                 : "i" (source), "i" (sel));                             \
1916         __res;                                                          \
1917 })
1918
1919 #define __write_32bit_gc0_register(register, sel, value)                \
1920 do {                                                                    \
1921         __asm__ __volatile__(                                           \
1922                 ".set\tpush\n\t"                                        \
1923                 ".set\tnoat\n\t"                                        \
1924                 "move\t$1, %z0\n\t"                                     \
1925                 "# mtgc0\t$1, $%1, %2\n\t"                              \
1926                 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2)           \
1927                 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11)     \
1928                 ".set\tpop"                                             \
1929                 : : "Jr" ((unsigned int)(value)),                       \
1930                     "i" (register), "i" (sel));                         \
1931 } while (0)
1932
1933 #define __write_64bit_gc0_register(register, sel, value)                \
1934 do {                                                                    \
1935         __asm__ __volatile__(                                           \
1936                 ".set\tpush\n\t"                                        \
1937                 ".set\tnoat\n\t"                                        \
1938                 "move\t$1, %z0\n\t"                                     \
1939                 "# dmtgc0\t$1, $%1, %2\n\t"                             \
1940                 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2)           \
1941                 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11)     \
1942                 ".set\tpop"                                             \
1943                 : : "Jr" (value),                                       \
1944                     "i" (register), "i" (sel));                         \
1945 } while (0)
1946
1947 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
1948
1949 #define __read_ulong_gc0_register(reg, sel)                             \
1950         ((sizeof(unsigned long) == 4) ?                                 \
1951         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
1952         (unsigned long) __read_64bit_gc0_register(reg, sel))
1953
1954 #define __write_ulong_gc0_register(reg, sel, val)                       \
1955 do {                                                                    \
1956         if (sizeof(unsigned long) == 4)                                 \
1957                 __write_32bit_gc0_register(reg, sel, val);              \
1958         else                                                            \
1959                 __write_64bit_gc0_register(reg, sel, val);              \
1960 } while (0)
1961
1962 #define read_gc0_index()                __read_32bit_gc0_register(0, 0)
1963 #define write_gc0_index(val)            __write_32bit_gc0_register(0, 0, val)
1964
1965 #define read_gc0_entrylo0()             __read_ulong_gc0_register(2, 0)
1966 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register(2, 0, val)
1967
1968 #define read_gc0_entrylo1()             __read_ulong_gc0_register(3, 0)
1969 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register(3, 0, val)
1970
1971 #define read_gc0_context()              __read_ulong_gc0_register(4, 0)
1972 #define write_gc0_context(val)          __write_ulong_gc0_register(4, 0, val)
1973
1974 #define read_gc0_contextconfig()        __read_32bit_gc0_register(4, 1)
1975 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register(4, 1, val)
1976
1977 #define read_gc0_userlocal()            __read_ulong_gc0_register(4, 2)
1978 #define write_gc0_userlocal(val)        __write_ulong_gc0_register(4, 2, val)
1979
1980 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register(4, 3)
1981 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register(4, 3, val)
1982
1983 #define read_gc0_pagemask()             __read_32bit_gc0_register(5, 0)
1984 #define write_gc0_pagemask(val)         __write_32bit_gc0_register(5, 0, val)
1985
1986 #define read_gc0_pagegrain()            __read_32bit_gc0_register(5, 1)
1987 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register(5, 1, val)
1988
1989 #define read_gc0_segctl0()              __read_ulong_gc0_register(5, 2)
1990 #define write_gc0_segctl0(val)          __write_ulong_gc0_register(5, 2, val)
1991
1992 #define read_gc0_segctl1()              __read_ulong_gc0_register(5, 3)
1993 #define write_gc0_segctl1(val)          __write_ulong_gc0_register(5, 3, val)
1994
1995 #define read_gc0_segctl2()              __read_ulong_gc0_register(5, 4)
1996 #define write_gc0_segctl2(val)          __write_ulong_gc0_register(5, 4, val)
1997
1998 #define read_gc0_pwbase()               __read_ulong_gc0_register(5, 5)
1999 #define write_gc0_pwbase(val)           __write_ulong_gc0_register(5, 5, val)
2000
2001 #define read_gc0_pwfield()              __read_ulong_gc0_register(5, 6)
2002 #define write_gc0_pwfield(val)          __write_ulong_gc0_register(5, 6, val)
2003
2004 #define read_gc0_pwsize()               __read_ulong_gc0_register(5, 7)
2005 #define write_gc0_pwsize(val)           __write_ulong_gc0_register(5, 7, val)
2006
2007 #define read_gc0_wired()                __read_32bit_gc0_register(6, 0)
2008 #define write_gc0_wired(val)            __write_32bit_gc0_register(6, 0, val)
2009
2010 #define read_gc0_pwctl()                __read_32bit_gc0_register(6, 6)
2011 #define write_gc0_pwctl(val)            __write_32bit_gc0_register(6, 6, val)
2012
2013 #define read_gc0_hwrena()               __read_32bit_gc0_register(7, 0)
2014 #define write_gc0_hwrena(val)           __write_32bit_gc0_register(7, 0, val)
2015
2016 #define read_gc0_badvaddr()             __read_ulong_gc0_register(8, 0)
2017 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register(8, 0, val)
2018
2019 #define read_gc0_badinstr()             __read_32bit_gc0_register(8, 1)
2020 #define write_gc0_badinstr(val)         __write_32bit_gc0_register(8, 1, val)
2021
2022 #define read_gc0_badinstrp()            __read_32bit_gc0_register(8, 2)
2023 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register(8, 2, val)
2024
2025 #define read_gc0_count()                __read_32bit_gc0_register(9, 0)
2026
2027 #define read_gc0_entryhi()              __read_ulong_gc0_register(10, 0)
2028 #define write_gc0_entryhi(val)          __write_ulong_gc0_register(10, 0, val)
2029
2030 #define read_gc0_compare()              __read_32bit_gc0_register(11, 0)
2031 #define write_gc0_compare(val)          __write_32bit_gc0_register(11, 0, val)
2032
2033 #define read_gc0_status()               __read_32bit_gc0_register(12, 0)
2034 #define write_gc0_status(val)           __write_32bit_gc0_register(12, 0, val)
2035
2036 #define read_gc0_intctl()               __read_32bit_gc0_register(12, 1)
2037 #define write_gc0_intctl(val)           __write_32bit_gc0_register(12, 1, val)
2038
2039 #define read_gc0_cause()                __read_32bit_gc0_register(13, 0)
2040 #define write_gc0_cause(val)            __write_32bit_gc0_register(13, 0, val)
2041
2042 #define read_gc0_epc()                  __read_ulong_gc0_register(14, 0)
2043 #define write_gc0_epc(val)              __write_ulong_gc0_register(14, 0, val)
2044
2045 #define read_gc0_prid()                 __read_32bit_gc0_register(15, 0)
2046
2047 #define read_gc0_ebase()                __read_32bit_gc0_register(15, 1)
2048 #define write_gc0_ebase(val)            __write_32bit_gc0_register(15, 1, val)
2049
2050 #define read_gc0_ebase_64()             __read_64bit_gc0_register(15, 1)
2051 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register(15, 1, val)
2052
2053 #define read_gc0_config()               __read_32bit_gc0_register(16, 0)
2054 #define read_gc0_config1()              __read_32bit_gc0_register(16, 1)
2055 #define read_gc0_config2()              __read_32bit_gc0_register(16, 2)
2056 #define read_gc0_config3()              __read_32bit_gc0_register(16, 3)
2057 #define read_gc0_config4()              __read_32bit_gc0_register(16, 4)
2058 #define read_gc0_config5()              __read_32bit_gc0_register(16, 5)
2059 #define read_gc0_config6()              __read_32bit_gc0_register(16, 6)
2060 #define read_gc0_config7()              __read_32bit_gc0_register(16, 7)
2061 #define write_gc0_config(val)           __write_32bit_gc0_register(16, 0, val)
2062 #define write_gc0_config1(val)          __write_32bit_gc0_register(16, 1, val)
2063 #define write_gc0_config2(val)          __write_32bit_gc0_register(16, 2, val)
2064 #define write_gc0_config3(val)          __write_32bit_gc0_register(16, 3, val)
2065 #define write_gc0_config4(val)          __write_32bit_gc0_register(16, 4, val)
2066 #define write_gc0_config5(val)          __write_32bit_gc0_register(16, 5, val)
2067 #define write_gc0_config6(val)          __write_32bit_gc0_register(16, 6, val)
2068 #define write_gc0_config7(val)          __write_32bit_gc0_register(16, 7, val)
2069
2070 #define read_gc0_lladdr()               __read_ulong_gc0_register(17, 0)
2071 #define write_gc0_lladdr(val)           __write_ulong_gc0_register(17, 0, val)
2072
2073 #define read_gc0_watchlo0()             __read_ulong_gc0_register(18, 0)
2074 #define read_gc0_watchlo1()             __read_ulong_gc0_register(18, 1)
2075 #define read_gc0_watchlo2()             __read_ulong_gc0_register(18, 2)
2076 #define read_gc0_watchlo3()             __read_ulong_gc0_register(18, 3)
2077 #define read_gc0_watchlo4()             __read_ulong_gc0_register(18, 4)
2078 #define read_gc0_watchlo5()             __read_ulong_gc0_register(18, 5)
2079 #define read_gc0_watchlo6()             __read_ulong_gc0_register(18, 6)
2080 #define read_gc0_watchlo7()             __read_ulong_gc0_register(18, 7)
2081 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register(18, 0, val)
2082 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register(18, 1, val)
2083 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register(18, 2, val)
2084 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register(18, 3, val)
2085 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register(18, 4, val)
2086 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register(18, 5, val)
2087 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register(18, 6, val)
2088 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register(18, 7, val)
2089
2090 #define read_gc0_watchhi0()             __read_32bit_gc0_register(19, 0)
2091 #define read_gc0_watchhi1()             __read_32bit_gc0_register(19, 1)
2092 #define read_gc0_watchhi2()             __read_32bit_gc0_register(19, 2)
2093 #define read_gc0_watchhi3()             __read_32bit_gc0_register(19, 3)
2094 #define read_gc0_watchhi4()             __read_32bit_gc0_register(19, 4)
2095 #define read_gc0_watchhi5()             __read_32bit_gc0_register(19, 5)
2096 #define read_gc0_watchhi6()             __read_32bit_gc0_register(19, 6)
2097 #define read_gc0_watchhi7()             __read_32bit_gc0_register(19, 7)
2098 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register(19, 0, val)
2099 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register(19, 1, val)
2100 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register(19, 2, val)
2101 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register(19, 3, val)
2102 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register(19, 4, val)
2103 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register(19, 5, val)
2104 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register(19, 6, val)
2105 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register(19, 7, val)
2106
2107 #define read_gc0_xcontext()             __read_ulong_gc0_register(20, 0)
2108 #define write_gc0_xcontext(val)         __write_ulong_gc0_register(20, 0, val)
2109
2110 #define read_gc0_perfctrl0()            __read_32bit_gc0_register(25, 0)
2111 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register(25, 0, val)
2112 #define read_gc0_perfcntr0()            __read_32bit_gc0_register(25, 1)
2113 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register(25, 1, val)
2114 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register(25, 1)
2115 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register(25, 1, val)
2116 #define read_gc0_perfctrl1()            __read_32bit_gc0_register(25, 2)
2117 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register(25, 2, val)
2118 #define read_gc0_perfcntr1()            __read_32bit_gc0_register(25, 3)
2119 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register(25, 3, val)
2120 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register(25, 3)
2121 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register(25, 3, val)
2122 #define read_gc0_perfctrl2()            __read_32bit_gc0_register(25, 4)
2123 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register(25, 4, val)
2124 #define read_gc0_perfcntr2()            __read_32bit_gc0_register(25, 5)
2125 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register(25, 5, val)
2126 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register(25, 5)
2127 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register(25, 5, val)
2128 #define read_gc0_perfctrl3()            __read_32bit_gc0_register(25, 6)
2129 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register(25, 6, val)
2130 #define read_gc0_perfcntr3()            __read_32bit_gc0_register(25, 7)
2131 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register(25, 7, val)
2132 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register(25, 7)
2133 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register(25, 7, val)
2134
2135 #define read_gc0_errorepc()             __read_ulong_gc0_register(30, 0)
2136 #define write_gc0_errorepc(val)         __write_ulong_gc0_register(30, 0, val)
2137
2138 #define read_gc0_kscratch1()            __read_ulong_gc0_register(31, 2)
2139 #define read_gc0_kscratch2()            __read_ulong_gc0_register(31, 3)
2140 #define read_gc0_kscratch3()            __read_ulong_gc0_register(31, 4)
2141 #define read_gc0_kscratch4()            __read_ulong_gc0_register(31, 5)
2142 #define read_gc0_kscratch5()            __read_ulong_gc0_register(31, 6)
2143 #define read_gc0_kscratch6()            __read_ulong_gc0_register(31, 7)
2144 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register(31, 2, val)
2145 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register(31, 3, val)
2146 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register(31, 4, val)
2147 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register(31, 5, val)
2148 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register(31, 6, val)
2149 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register(31, 7, val)
2150
2151 /* Cavium OCTEON (cnMIPS) */
2152 #define read_gc0_cvmcount()             __read_ulong_gc0_register(9, 6)
2153 #define write_gc0_cvmcount(val)         __write_ulong_gc0_register(9, 6, val)
2154
2155 #define read_gc0_cvmctl()               __read_64bit_gc0_register(9, 7)
2156 #define write_gc0_cvmctl(val)           __write_64bit_gc0_register(9, 7, val)
2157
2158 #define read_gc0_cvmmemctl()            __read_64bit_gc0_register(11, 7)
2159 #define write_gc0_cvmmemctl(val)        __write_64bit_gc0_register(11, 7, val)
2160
2161 #define read_gc0_cvmmemctl2()           __read_64bit_gc0_register(16, 6)
2162 #define write_gc0_cvmmemctl2(val)       __write_64bit_gc0_register(16, 6, val)
2163
2164 /*
2165  * Macros to access the floating point coprocessor control registers
2166  */
2167 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2168 ({                                                                      \
2169         unsigned int __res;                                             \
2170                                                                         \
2171         __asm__ __volatile__(                                           \
2172         "       .set    push                                    \n"     \
2173         "       .set    reorder                                 \n"     \
2174         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2175         "       # like Octeon.                                  \n"     \
2176         "       .set    mips1                                   \n"     \
2177         "       "STR(gas_hardfloat)"                            \n"     \
2178         "       cfc1    %0,"STR(source)"                        \n"     \
2179         "       .set    pop                                     \n"     \
2180         : "=r" (__res));                                                \
2181         __res;                                                          \
2182 })
2183
2184 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2185 do {                                                                    \
2186         __asm__ __volatile__(                                           \
2187         "       .set    push                                    \n"     \
2188         "       .set    reorder                                 \n"     \
2189         "       "STR(gas_hardfloat)"                            \n"     \
2190         "       ctc1    %0,"STR(dest)"                          \n"     \
2191         "       .set    pop                                     \n"     \
2192         : : "r" (val));                                                 \
2193 } while (0)
2194
2195 #ifdef GAS_HAS_SET_HARDFLOAT
2196 #define read_32bit_cp1_register(source)                                 \
2197         _read_32bit_cp1_register(source, .set hardfloat)
2198 #define write_32bit_cp1_register(dest, val)                             \
2199         _write_32bit_cp1_register(dest, val, .set hardfloat)
2200 #else
2201 #define read_32bit_cp1_register(source)                                 \
2202         _read_32bit_cp1_register(source, )
2203 #define write_32bit_cp1_register(dest, val)                             \
2204         _write_32bit_cp1_register(dest, val, )
2205 #endif
2206
2207 #ifdef HAVE_AS_DSP
2208 #define rddsp(mask)                                                     \
2209 ({                                                                      \
2210         unsigned int __dspctl;                                          \
2211                                                                         \
2212         __asm__ __volatile__(                                           \
2213         "       .set push                                       \n"     \
2214         "       .set dsp                                        \n"     \
2215         "       rddsp   %0, %x1                                 \n"     \
2216         "       .set pop                                        \n"     \
2217         : "=r" (__dspctl)                                               \
2218         : "i" (mask));                                                  \
2219         __dspctl;                                                       \
2220 })
2221
2222 #define wrdsp(val, mask)                                                \
2223 do {                                                                    \
2224         __asm__ __volatile__(                                           \
2225         "       .set push                                       \n"     \
2226         "       .set dsp                                        \n"     \
2227         "       wrdsp   %0, %x1                                 \n"     \
2228         "       .set pop                                        \n"     \
2229         :                                                               \
2230         : "r" (val), "i" (mask));                                       \
2231 } while (0)
2232
2233 #define mflo0()                                                         \
2234 ({                                                                      \
2235         long mflo0;                                                     \
2236         __asm__(                                                        \
2237         "       .set push                                       \n"     \
2238         "       .set dsp                                        \n"     \
2239         "       mflo %0, $ac0                                   \n"     \
2240         "       .set pop                                        \n"     \
2241         : "=r" (mflo0));                                                \
2242         mflo0;                                                          \
2243 })
2244
2245 #define mflo1()                                                         \
2246 ({                                                                      \
2247         long mflo1;                                                     \
2248         __asm__(                                                        \
2249         "       .set push                                       \n"     \
2250         "       .set dsp                                        \n"     \
2251         "       mflo %0, $ac1                                   \n"     \
2252         "       .set pop                                        \n"     \
2253         : "=r" (mflo1));                                                \
2254         mflo1;                                                          \
2255 })
2256
2257 #define mflo2()                                                         \
2258 ({                                                                      \
2259         long mflo2;                                                     \
2260         __asm__(                                                        \
2261         "       .set push                                       \n"     \
2262         "       .set dsp                                        \n"     \
2263         "       mflo %0, $ac2                                   \n"     \
2264         "       .set pop                                        \n"     \
2265         : "=r" (mflo2));                                                \
2266         mflo2;                                                          \
2267 })
2268
2269 #define mflo3()                                                         \
2270 ({                                                                      \
2271         long mflo3;                                                     \
2272         __asm__(                                                        \
2273         "       .set push                                       \n"     \
2274         "       .set dsp                                        \n"     \
2275         "       mflo %0, $ac3                                   \n"     \
2276         "       .set pop                                        \n"     \
2277         : "=r" (mflo3));                                                \
2278         mflo3;                                                          \
2279 })
2280
2281 #define mfhi0()                                                         \
2282 ({                                                                      \
2283         long mfhi0;                                                     \
2284         __asm__(                                                        \
2285         "       .set push                                       \n"     \
2286         "       .set dsp                                        \n"     \
2287         "       mfhi %0, $ac0                                   \n"     \
2288         "       .set pop                                        \n"     \
2289         : "=r" (mfhi0));                                                \
2290         mfhi0;                                                          \
2291 })
2292
2293 #define mfhi1()                                                         \
2294 ({                                                                      \
2295         long mfhi1;                                                     \
2296         __asm__(                                                        \
2297         "       .set push                                       \n"     \
2298         "       .set dsp                                        \n"     \
2299         "       mfhi %0, $ac1                                   \n"     \
2300         "       .set pop                                        \n"     \
2301         : "=r" (mfhi1));                                                \
2302         mfhi1;                                                          \
2303 })
2304
2305 #define mfhi2()                                                         \
2306 ({                                                                      \
2307         long mfhi2;                                                     \
2308         __asm__(                                                        \
2309         "       .set push                                       \n"     \
2310         "       .set dsp                                        \n"     \
2311         "       mfhi %0, $ac2                                   \n"     \
2312         "       .set pop                                        \n"     \
2313         : "=r" (mfhi2));                                                \
2314         mfhi2;                                                          \
2315 })
2316
2317 #define mfhi3()                                                         \
2318 ({                                                                      \
2319         long mfhi3;                                                     \
2320         __asm__(                                                        \
2321         "       .set push                                       \n"     \
2322         "       .set dsp                                        \n"     \
2323         "       mfhi %0, $ac3                                   \n"     \
2324         "       .set pop                                        \n"     \
2325         : "=r" (mfhi3));                                                \
2326         mfhi3;                                                          \
2327 })
2328
2329
2330 #define mtlo0(x)                                                        \
2331 ({                                                                      \
2332         __asm__(                                                        \
2333         "       .set push                                       \n"     \
2334         "       .set dsp                                        \n"     \
2335         "       mtlo %0, $ac0                                   \n"     \
2336         "       .set pop                                        \n"     \
2337         :                                                               \
2338         : "r" (x));                                                     \
2339 })
2340
2341 #define mtlo1(x)                                                        \
2342 ({                                                                      \
2343         __asm__(                                                        \
2344         "       .set push                                       \n"     \
2345         "       .set dsp                                        \n"     \
2346         "       mtlo %0, $ac1                                   \n"     \
2347         "       .set pop                                        \n"     \
2348         :                                                               \
2349         : "r" (x));                                                     \
2350 })
2351
2352 #define mtlo2(x)                                                        \
2353 ({                                                                      \
2354         __asm__(                                                        \
2355         "       .set push                                       \n"     \
2356         "       .set dsp                                        \n"     \
2357         "       mtlo %0, $ac2                                   \n"     \
2358         "       .set pop                                        \n"     \
2359         :                                                               \
2360         : "r" (x));                                                     \
2361 })
2362
2363 #define mtlo3(x)                                                        \
2364 ({                                                                      \
2365         __asm__(                                                        \
2366         "       .set push                                       \n"     \
2367         "       .set dsp                                        \n"     \
2368         "       mtlo %0, $ac3                                   \n"     \
2369         "       .set pop                                        \n"     \
2370         :                                                               \
2371         : "r" (x));                                                     \
2372 })
2373
2374 #define mthi0(x)                                                        \
2375 ({                                                                      \
2376         __asm__(                                                        \
2377         "       .set push                                       \n"     \
2378         "       .set dsp                                        \n"     \
2379         "       mthi %0, $ac0                                   \n"     \
2380         "       .set pop                                        \n"     \
2381         :                                                               \
2382         : "r" (x));                                                     \
2383 })
2384
2385 #define mthi1(x)                                                        \
2386 ({                                                                      \
2387         __asm__(                                                        \
2388         "       .set push                                       \n"     \
2389         "       .set dsp                                        \n"     \
2390         "       mthi %0, $ac1                                   \n"     \
2391         "       .set pop                                        \n"     \
2392         :                                                               \
2393         : "r" (x));                                                     \
2394 })
2395
2396 #define mthi2(x)                                                        \
2397 ({                                                                      \
2398         __asm__(                                                        \
2399         "       .set push                                       \n"     \
2400         "       .set dsp                                        \n"     \
2401         "       mthi %0, $ac2                                   \n"     \
2402         "       .set pop                                        \n"     \
2403         :                                                               \
2404         : "r" (x));                                                     \
2405 })
2406
2407 #define mthi3(x)                                                        \
2408 ({                                                                      \
2409         __asm__(                                                        \
2410         "       .set push                                       \n"     \
2411         "       .set dsp                                        \n"     \
2412         "       mthi %0, $ac3                                   \n"     \
2413         "       .set pop                                        \n"     \
2414         :                                                               \
2415         : "r" (x));                                                     \
2416 })
2417
2418 #else
2419
2420 #define rddsp(mask)                                                     \
2421 ({                                                                      \
2422         unsigned int __res;                                             \
2423                                                                         \
2424         __asm__ __volatile__(                                           \
2425         "       .set    push                                    \n"     \
2426         "       .set    noat                                    \n"     \
2427         "       # rddsp $1, %x1                                 \n"     \
2428         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2429         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2430         "       move    %0, $1                                  \n"     \
2431         "       .set    pop                                     \n"     \
2432         : "=r" (__res)                                                  \
2433         : "i" (mask));                                                  \
2434         __res;                                                          \
2435 })
2436
2437 #define wrdsp(val, mask)                                                \
2438 do {                                                                    \
2439         __asm__ __volatile__(                                           \
2440         "       .set    push                                    \n"     \
2441         "       .set    noat                                    \n"     \
2442         "       move    $1, %0                                  \n"     \
2443         "       # wrdsp $1, %x1                                 \n"     \
2444         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2445         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2446         "       .set    pop                                     \n"     \
2447         :                                                               \
2448         : "r" (val), "i" (mask));                                       \
2449 } while (0)
2450
2451 #define _dsp_mfxxx(ins)                                                 \
2452 ({                                                                      \
2453         unsigned long __treg;                                           \
2454                                                                         \
2455         __asm__ __volatile__(                                           \
2456         "       .set    push                                    \n"     \
2457         "       .set    noat                                    \n"     \
2458         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2459         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2460         "       move    %0, $1                                  \n"     \
2461         "       .set    pop                                     \n"     \
2462         : "=r" (__treg)                                                 \
2463         : "i" (ins));                                                   \
2464         __treg;                                                         \
2465 })
2466
2467 #define _dsp_mtxxx(val, ins)                                            \
2468 do {                                                                    \
2469         __asm__ __volatile__(                                           \
2470         "       .set    push                                    \n"     \
2471         "       .set    noat                                    \n"     \
2472         "       move    $1, %0                                  \n"     \
2473         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2474         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2475         "       .set    pop                                     \n"     \
2476         :                                                               \
2477         : "r" (val), "i" (ins));                                        \
2478 } while (0)
2479
2480 #ifdef CONFIG_CPU_MICROMIPS
2481
2482 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2483 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2484
2485 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2486 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2487
2488 #else  /* !CONFIG_CPU_MICROMIPS */
2489
2490 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2491 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2492
2493 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2494 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2495
2496 #endif /* CONFIG_CPU_MICROMIPS */
2497
2498 #define mflo0() _dsp_mflo(0)
2499 #define mflo1() _dsp_mflo(1)
2500 #define mflo2() _dsp_mflo(2)
2501 #define mflo3() _dsp_mflo(3)
2502
2503 #define mfhi0() _dsp_mfhi(0)
2504 #define mfhi1() _dsp_mfhi(1)
2505 #define mfhi2() _dsp_mfhi(2)
2506 #define mfhi3() _dsp_mfhi(3)
2507
2508 #define mtlo0(x) _dsp_mtlo(x, 0)
2509 #define mtlo1(x) _dsp_mtlo(x, 1)
2510 #define mtlo2(x) _dsp_mtlo(x, 2)
2511 #define mtlo3(x) _dsp_mtlo(x, 3)
2512
2513 #define mthi0(x) _dsp_mthi(x, 0)
2514 #define mthi1(x) _dsp_mthi(x, 1)
2515 #define mthi2(x) _dsp_mthi(x, 2)
2516 #define mthi3(x) _dsp_mthi(x, 3)
2517
2518 #endif
2519
2520 /*
2521  * TLB operations.
2522  *
2523  * It is responsibility of the caller to take care of any TLB hazards.
2524  */
2525 static inline void tlb_probe(void)
2526 {
2527         __asm__ __volatile__(
2528                 ".set noreorder\n\t"
2529                 "tlbp\n\t"
2530                 ".set reorder");
2531 }
2532
2533 static inline void tlb_read(void)
2534 {
2535 #if MIPS34K_MISSED_ITLB_WAR
2536         int res = 0;
2537
2538         __asm__ __volatile__(
2539         "       .set    push                                    \n"
2540         "       .set    noreorder                               \n"
2541         "       .set    noat                                    \n"
2542         "       .set    mips32r2                                \n"
2543         "       .word   0x41610001              # dvpe $1       \n"
2544         "       move    %0, $1                                  \n"
2545         "       ehb                                             \n"
2546         "       .set    pop                                     \n"
2547         : "=r" (res));
2548
2549         instruction_hazard();
2550 #endif
2551
2552         __asm__ __volatile__(
2553                 ".set noreorder\n\t"
2554                 "tlbr\n\t"
2555                 ".set reorder");
2556
2557 #if MIPS34K_MISSED_ITLB_WAR
2558         if ((res & _ULCAST_(1)))
2559                 __asm__ __volatile__(
2560                 "       .set    push                            \n"
2561                 "       .set    noreorder                       \n"
2562                 "       .set    noat                            \n"
2563                 "       .set    mips32r2                        \n"
2564                 "       .word   0x41600021      # evpe          \n"
2565                 "       ehb                                     \n"
2566                 "       .set    pop                             \n");
2567 #endif
2568 }
2569
2570 static inline void tlb_write_indexed(void)
2571 {
2572         __asm__ __volatile__(
2573                 ".set noreorder\n\t"
2574                 "tlbwi\n\t"
2575                 ".set reorder");
2576 }
2577
2578 static inline void tlb_write_random(void)
2579 {
2580         __asm__ __volatile__(
2581                 ".set noreorder\n\t"
2582                 "tlbwr\n\t"
2583                 ".set reorder");
2584 }
2585
2586 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2587
2588 /*
2589  * Guest TLB operations.
2590  *
2591  * It is responsibility of the caller to take care of any TLB hazards.
2592  */
2593 static inline void guest_tlb_probe(void)
2594 {
2595         __asm__ __volatile__(
2596                 ".set push\n\t"
2597                 ".set noreorder\n\t"
2598                 ".set virt\n\t"
2599                 "tlbgp\n\t"
2600                 ".set pop");
2601 }
2602
2603 static inline void guest_tlb_read(void)
2604 {
2605         __asm__ __volatile__(
2606                 ".set push\n\t"
2607                 ".set noreorder\n\t"
2608                 ".set virt\n\t"
2609                 "tlbgr\n\t"
2610                 ".set pop");
2611 }
2612
2613 static inline void guest_tlb_write_indexed(void)
2614 {
2615         __asm__ __volatile__(
2616                 ".set push\n\t"
2617                 ".set noreorder\n\t"
2618                 ".set virt\n\t"
2619                 "tlbgwi\n\t"
2620                 ".set pop");
2621 }
2622
2623 static inline void guest_tlb_write_random(void)
2624 {
2625         __asm__ __volatile__(
2626                 ".set push\n\t"
2627                 ".set noreorder\n\t"
2628                 ".set virt\n\t"
2629                 "tlbgwr\n\t"
2630                 ".set pop");
2631 }
2632
2633 /*
2634  * Guest TLB Invalidate Flush
2635  */
2636 static inline void guest_tlbinvf(void)
2637 {
2638         __asm__ __volatile__(
2639                 ".set push\n\t"
2640                 ".set noreorder\n\t"
2641                 ".set virt\n\t"
2642                 "tlbginvf\n\t"
2643                 ".set pop");
2644 }
2645
2646 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
2647
2648 /*
2649  * Guest TLB operations.
2650  *
2651  * It is responsibility of the caller to take care of any TLB hazards.
2652  */
2653 static inline void guest_tlb_probe(void)
2654 {
2655         __asm__ __volatile__(
2656                 "# tlbgp\n\t"
2657                 _ASM_INSN_IF_MIPS(0x42000010)
2658                 _ASM_INSN32_IF_MM(0x0000017c));
2659 }
2660
2661 static inline void guest_tlb_read(void)
2662 {
2663         __asm__ __volatile__(
2664                 "# tlbgr\n\t"
2665                 _ASM_INSN_IF_MIPS(0x42000009)
2666                 _ASM_INSN32_IF_MM(0x0000117c));
2667 }
2668
2669 static inline void guest_tlb_write_indexed(void)
2670 {
2671         __asm__ __volatile__(
2672                 "# tlbgwi\n\t"
2673                 _ASM_INSN_IF_MIPS(0x4200000a)
2674                 _ASM_INSN32_IF_MM(0x0000217c));
2675 }
2676
2677 static inline void guest_tlb_write_random(void)
2678 {
2679         __asm__ __volatile__(
2680                 "# tlbgwr\n\t"
2681                 _ASM_INSN_IF_MIPS(0x4200000e)
2682                 _ASM_INSN32_IF_MM(0x0000317c));
2683 }
2684
2685 /*
2686  * Guest TLB Invalidate Flush
2687  */
2688 static inline void guest_tlbinvf(void)
2689 {
2690         __asm__ __volatile__(
2691                 "# tlbginvf\n\t"
2692                 _ASM_INSN_IF_MIPS(0x4200000c)
2693                 _ASM_INSN32_IF_MM(0x0000517c));
2694 }
2695
2696 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
2697
2698 /*
2699  * Manipulate bits in a register.
2700  */
2701 #define __BUILD_SET_COMMON(name)                                \
2702 static inline unsigned int                                      \
2703 set_##name(unsigned int set)                                    \
2704 {                                                               \
2705         unsigned int res, new;                                  \
2706                                                                 \
2707         res = read_##name();                                    \
2708         new = res | set;                                        \
2709         write_##name(new);                                      \
2710                                                                 \
2711         return res;                                             \
2712 }                                                               \
2713                                                                 \
2714 static inline unsigned int                                      \
2715 clear_##name(unsigned int clear)                                \
2716 {                                                               \
2717         unsigned int res, new;                                  \
2718                                                                 \
2719         res = read_##name();                                    \
2720         new = res & ~clear;                                     \
2721         write_##name(new);                                      \
2722                                                                 \
2723         return res;                                             \
2724 }                                                               \
2725                                                                 \
2726 static inline unsigned int                                      \
2727 change_##name(unsigned int change, unsigned int val)            \
2728 {                                                               \
2729         unsigned int res, new;                                  \
2730                                                                 \
2731         res = read_##name();                                    \
2732         new = res & ~change;                                    \
2733         new |= (val & change);                                  \
2734         write_##name(new);                                      \
2735                                                                 \
2736         return res;                                             \
2737 }
2738
2739 /*
2740  * Manipulate bits in a c0 register.
2741  */
2742 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2743
2744 __BUILD_SET_C0(status)
2745 __BUILD_SET_C0(cause)
2746 __BUILD_SET_C0(config)
2747 __BUILD_SET_C0(config5)
2748 __BUILD_SET_C0(intcontrol)
2749 __BUILD_SET_C0(intctl)
2750 __BUILD_SET_C0(srsmap)
2751 __BUILD_SET_C0(pagegrain)
2752 __BUILD_SET_C0(guestctl0)
2753 __BUILD_SET_C0(guestctl0ext)
2754 __BUILD_SET_C0(guestctl1)
2755 __BUILD_SET_C0(guestctl2)
2756 __BUILD_SET_C0(guestctl3)
2757 __BUILD_SET_C0(brcm_config_0)
2758 __BUILD_SET_C0(brcm_bus_pll)
2759 __BUILD_SET_C0(brcm_reset)
2760 __BUILD_SET_C0(brcm_cmt_intr)
2761 __BUILD_SET_C0(brcm_cmt_ctrl)
2762 __BUILD_SET_C0(brcm_config)
2763 __BUILD_SET_C0(brcm_mode)
2764
2765 /*
2766  * Manipulate bits in a guest c0 register.
2767  */
2768 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2769
2770 __BUILD_SET_GC0(wired)
2771 __BUILD_SET_GC0(status)
2772 __BUILD_SET_GC0(cause)
2773 __BUILD_SET_GC0(ebase)
2774 __BUILD_SET_GC0(config1)
2775
2776 /*
2777  * Return low 10 bits of ebase.
2778  * Note that under KVM (MIPSVZ) this returns vcpu id.
2779  */
2780 static inline unsigned int get_ebase_cpunum(void)
2781 {
2782         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2783 }
2784
2785 #endif /* !__ASSEMBLY__ */
2786
2787 #endif /* _ASM_MIPSREGS_H */