arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/isa-rev.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #define _U64CAST_
  38 #else
  39 #define _ULCAST_ (unsigned long)
  40 #define _U64CAST_ (u64)
  41 #endif
  42
  43 /*
  44  * Coprocessor 0 register names
  45  */
  46 #define CP0_INDEX $0
  47 #define CP0_RANDOM $1
  48 #define CP0_ENTRYLO0 $2
  49 #define CP0_ENTRYLO1 $3
  50 #define CP0_CONF $3
  51 #define CP0_GLOBALNUMBER $3, 1
  52 #define CP0_CONTEXT $4
  53 #define CP0_PAGEMASK $5
  54 #define CP0_PAGEGRAIN $5, 1
  55 #define CP0_SEGCTL0 $5, 2
  56 #define CP0_SEGCTL1 $5, 3
  57 #define CP0_SEGCTL2 $5, 4
  58 #define CP0_WIRED $6
  59 #define CP0_INFO $7
  60 #define CP0_HWRENA $7
  61 #define CP0_BADVADDR $8
  62 #define CP0_BADINSTR $8, 1
  63 #define CP0_COUNT $9
  64 #define CP0_ENTRYHI $10
  65 #define CP0_GUESTCTL1 $10, 4
  66 #define CP0_GUESTCTL2 $10, 5
  67 #define CP0_GUESTCTL3 $10, 6
  68 #define CP0_COMPARE $11
  69 #define CP0_GUESTCTL0EXT $11, 4
  70 #define CP0_STATUS $12
  71 #define CP0_GUESTCTL0 $12, 6
  72 #define CP0_GTOFFSET $12, 7
  73 #define CP0_CAUSE $13
  74 #define CP0_EPC $14
  75 #define CP0_PRID $15
  76 #define CP0_EBASE $15, 1
  77 #define CP0_CMGCRBASE $15, 3
  78 #define CP0_CONFIG $16
  79 #define CP0_CONFIG3 $16, 3
  80 #define CP0_CONFIG5 $16, 5
  81 #define CP0_CONFIG6 $16, 6
  82 #define CP0_LLADDR $17
  83 #define CP0_WATCHLO $18
  84 #define CP0_WATCHHI $19
  85 #define CP0_XCONTEXT $20
  86 #define CP0_FRAMEMASK $21
  87 #define CP0_DIAGNOSTIC $22
  88 #define CP0_DIAGNOSTIC1 $22, 1
  89 #define CP0_DEBUG $23
  90 #define CP0_DEPC $24
  91 #define CP0_PERFORMANCE $25
  92 #define CP0_ECC $26
  93 #define CP0_CACHEERR $27
  94 #define CP0_TAGLO $28
  95 #define CP0_TAGHI $29
  96 #define CP0_ERROREPC $30
  97 #define CP0_DESAVE $31
  98
  99 /*
 100  * R4640/R4650 cp0 register names.  These registers are listed
 101  * here only for completeness; without MMU these CPUs are not useable
 102  * by Linux.  A future ELKS port might take make Linux run on them
 103  * though ...
 104  */
 105 #define CP0_IBASE $0
 106 #define CP0_IBOUND $1
 107 #define CP0_DBASE $2
 108 #define CP0_DBOUND $3
 109 #define CP0_CALG $17
 110 #define CP0_IWATCH $18
 111 #define CP0_DWATCH $19
 112
 113 /*
 114  * Coprocessor 0 Set 1 register names
 115  */
 116 #define CP0_S1_DERRADDR0  $26
 117 #define CP0_S1_DERRADDR1  $27
 118 #define CP0_S1_INTCONTROL $20
 119
 120 /*
 121  * Coprocessor 0 Set 2 register names
 122  */
 123 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 124
 125 /*
 126  * Coprocessor 0 Set 3 register names
 127  */
 128 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 129
 130 /*
 131  *  TX39 Series
 132  */
 133 #define CP0_TX39_CACHE  $7
 134
 135
 136 /* Generic EntryLo bit definitions */
 137 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 138 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 139 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 140 #define ENTRYLO_C_SHIFT         3
 141 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 142
 143 /* R3000 EntryLo bit definitions */
 144 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 145 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 146 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 147 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 148
 149 /* MIPS32/64 EntryLo bit definitions */
 150 #define MIPS_ENTRYLO_PFN_SHIFT  6
 151 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 152 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 153
 154 /*
 155  * MIPSr6+ GlobalNumber register definitions
 156  */
 157 #define MIPS_GLOBALNUMBER_VP_SHF        0
 158 #define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 159 #define MIPS_GLOBALNUMBER_CORE_SHF      8
 160 #define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 161 #define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
 162 #define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 163
 164 /*
 165  * Values for PageMask register
 166  */
 167 #define PM_4K           0x00000000
 168 #define PM_8K           0x00002000
 169 #define PM_16K          0x00006000
 170 #define PM_32K          0x0000e000
 171 #define PM_64K          0x0001e000
 172 #define PM_128K         0x0003e000
 173 #define PM_256K         0x0007e000
 174 #define PM_512K         0x000fe000
 175 #define PM_1M           0x001fe000
 176 #define PM_2M           0x003fe000
 177 #define PM_4M           0x007fe000
 178 #define PM_8M           0x00ffe000
 179 #define PM_16M          0x01ffe000
 180 #define PM_32M          0x03ffe000
 181 #define PM_64M          0x07ffe000
 182 #define PM_256M         0x1fffe000
 183 #define PM_1G           0x7fffe000
 184
 185 /*
 186  * Default page size for a given kernel configuration
 187  */
 188 #ifdef CONFIG_PAGE_SIZE_4KB
 189 #define PM_DEFAULT_MASK PM_4K
 190 #elif defined(CONFIG_PAGE_SIZE_8KB)
 191 #define PM_DEFAULT_MASK PM_8K
 192 #elif defined(CONFIG_PAGE_SIZE_16KB)
 193 #define PM_DEFAULT_MASK PM_16K
 194 #elif defined(CONFIG_PAGE_SIZE_32KB)
 195 #define PM_DEFAULT_MASK PM_32K
 196 #elif defined(CONFIG_PAGE_SIZE_64KB)
 197 #define PM_DEFAULT_MASK PM_64K
 198 #else
 199 #error Bad page size configuration!
 200 #endif
 201
 202 /*
 203  * Default huge tlb size for a given kernel configuration
 204  */
 205 #ifdef CONFIG_PAGE_SIZE_4KB
 206 #define PM_HUGE_MASK    PM_1M
 207 #elif defined(CONFIG_PAGE_SIZE_8KB)
 208 #define PM_HUGE_MASK    PM_4M
 209 #elif defined(CONFIG_PAGE_SIZE_16KB)
 210 #define PM_HUGE_MASK    PM_16M
 211 #elif defined(CONFIG_PAGE_SIZE_32KB)
 212 #define PM_HUGE_MASK    PM_64M
 213 #elif defined(CONFIG_PAGE_SIZE_64KB)
 214 #define PM_HUGE_MASK    PM_256M
 215 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 216 #error Bad page size configuration for hugetlbfs!
 217 #endif
 218
 219 /*
 220  * Wired register bits
 221  */
 222 #define MIPSR6_WIRED_LIMIT_SHIFT 16
 223 #define MIPSR6_WIRED_LIMIT      (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
 224 #define MIPSR6_WIRED_WIRED_SHIFT 0
 225 #define MIPSR6_WIRED_WIRED      (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
 226
 227 /*
 228  * Values used for computation of new tlb entries
 229  */
 230 #define PL_4K           12
 231 #define PL_16K          14
 232 #define PL_64K          16
 233 #define PL_256K         18
 234 #define PL_1M           20
 235 #define PL_4M           22
 236 #define PL_16M          24
 237 #define PL_64M          26
 238 #define PL_256M         28
 239
 240 /*
 241  * PageGrain bits
 242  */
 243 #define PG_RIE          (_ULCAST_(1) <<  31)
 244 #define PG_XIE          (_ULCAST_(1) <<  30)
 245 #define PG_ELPA         (_ULCAST_(1) <<  29)
 246 #define PG_ESP          (_ULCAST_(1) <<  28)
 247 #define PG_IEC          (_ULCAST_(1) <<  27)
 248
 249 /* MIPS32/64 EntryHI bit definitions */
 250 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 251 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 252 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 253
 254 /*
 255  * R4x00 interrupt enable / cause bits
 256  */
 257 #define IE_SW0          (_ULCAST_(1) <<  8)
 258 #define IE_SW1          (_ULCAST_(1) <<  9)
 259 #define IE_IRQ0         (_ULCAST_(1) << 10)
 260 #define IE_IRQ1         (_ULCAST_(1) << 11)
 261 #define IE_IRQ2         (_ULCAST_(1) << 12)
 262 #define IE_IRQ3         (_ULCAST_(1) << 13)
 263 #define IE_IRQ4         (_ULCAST_(1) << 14)
 264 #define IE_IRQ5         (_ULCAST_(1) << 15)
 265
 266 /*
 267  * R4x00 interrupt cause bits
 268  */
 269 #define C_SW0           (_ULCAST_(1) <<  8)
 270 #define C_SW1           (_ULCAST_(1) <<  9)
 271 #define C_IRQ0          (_ULCAST_(1) << 10)
 272 #define C_IRQ1          (_ULCAST_(1) << 11)
 273 #define C_IRQ2          (_ULCAST_(1) << 12)
 274 #define C_IRQ3          (_ULCAST_(1) << 13)
 275 #define C_IRQ4          (_ULCAST_(1) << 14)
 276 #define C_IRQ5          (_ULCAST_(1) << 15)
 277
 278 /*
 279  * Bitfields in the R4xx0 cp0 status register
 280  */
 281 #define ST0_IE                  0x00000001
 282 #define ST0_EXL                 0x00000002
 283 #define ST0_ERL                 0x00000004
 284 #define ST0_KSU                 0x00000018
 285 #  define KSU_USER              0x00000010
 286 #  define KSU_SUPERVISOR        0x00000008
 287 #  define KSU_KERNEL            0x00000000
 288 #define ST0_UX                  0x00000020
 289 #define ST0_SX                  0x00000040
 290 #define ST0_KX                  0x00000080
 291 #define ST0_DE                  0x00010000
 292 #define ST0_CE                  0x00020000
 293
 294 /*
 295  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 296  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 297  * processors.
 298  */
 299 #define ST0_CO                  0x08000000
 300
 301 /*
 302  * Bitfields in the R[23]000 cp0 status register.
 303  */
 304 #define ST0_IEC                 0x00000001
 305 #define ST0_KUC                 0x00000002
 306 #define ST0_IEP                 0x00000004
 307 #define ST0_KUP                 0x00000008
 308 #define ST0_IEO                 0x00000010
 309 #define ST0_KUO                 0x00000020
 310 /* bits 6 & 7 are reserved on R[23]000 */
 311 #define ST0_ISC                 0x00010000
 312 #define ST0_SWC                 0x00020000
 313 #define ST0_CM                  0x00080000
 314
 315 /*
 316  * Bits specific to the R4640/R4650
 317  */
 318 #define ST0_UM                  (_ULCAST_(1) <<  4)
 319 #define ST0_IL                  (_ULCAST_(1) << 23)
 320 #define ST0_DL                  (_ULCAST_(1) << 24)
 321
 322 /*
 323  * Enable the MIPS MDMX and DSP ASEs
 324  */
 325 #define ST0_MX                  0x01000000
 326
 327 /*
 328  * Status register bits available in all MIPS CPUs.
 329  */
 330 #define ST0_IM                  0x0000ff00
 331 #define  STATUSB_IP0            8
 332 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 333 #define  STATUSB_IP1            9
 334 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 335 #define  STATUSB_IP2            10
 336 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 337 #define  STATUSB_IP3            11
 338 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 339 #define  STATUSB_IP4            12
 340 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 341 #define  STATUSB_IP5            13
 342 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 343 #define  STATUSB_IP6            14
 344 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 345 #define  STATUSB_IP7            15
 346 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 347 #define  STATUSB_IP8            0
 348 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 349 #define  STATUSB_IP9            1
 350 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 351 #define  STATUSB_IP10           2
 352 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 353 #define  STATUSB_IP11           3
 354 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 355 #define  STATUSB_IP12           4
 356 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 357 #define  STATUSB_IP13           5
 358 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 359 #define  STATUSB_IP14           6
 360 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 361 #define  STATUSB_IP15           7
 362 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 363 #define ST0_CH                  0x00040000
 364 #define ST0_NMI                 0x00080000
 365 #define ST0_SR                  0x00100000
 366 #define ST0_TS                  0x00200000
 367 #define ST0_BEV                 0x00400000
 368 #define ST0_RE                  0x02000000
 369 #define ST0_FR                  0x04000000
 370 #define ST0_CU                  0xf0000000
 371 #define ST0_CU0                 0x10000000
 372 #define ST0_CU1                 0x20000000
 373 #define ST0_CU2                 0x40000000
 374 #define ST0_CU3                 0x80000000
 375 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 376
 377 /* in-kernel enabled CUs */
 378 #ifdef CONFIG_CPU_LOONGSON64
 379 #define ST0_KERNEL_CUMASK      (ST0_CU0 | ST0_CU2)
 380 #else
 381 #define ST0_KERNEL_CUMASK      ST0_CU0
 382 #endif
 383
 384 /*
 385  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 386  */
 387 #define INTCTLB_IPFDC           23
 388 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 389 #define INTCTLB_IPPCI           26
 390 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 391 #define INTCTLB_IPTI            29
 392 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 393
 394 /*
 395  * Bitfields and bit numbers in the coprocessor 0 cause register.
 396  *
 397  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 398  */
 399 #define CAUSEB_EXCCODE          2
 400 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 401 #define CAUSEB_IP               8
 402 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 403 #define  CAUSEB_IP0             8
 404 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 405 #define  CAUSEB_IP1             9
 406 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 407 #define  CAUSEB_IP2             10
 408 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 409 #define  CAUSEB_IP3             11
 410 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 411 #define  CAUSEB_IP4             12
 412 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 413 #define  CAUSEB_IP5             13
 414 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 415 #define  CAUSEB_IP6             14
 416 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 417 #define  CAUSEB_IP7             15
 418 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 419 #define CAUSEB_FDCI             21
 420 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 421 #define CAUSEB_WP               22
 422 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 423 #define CAUSEB_IV               23
 424 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 425 #define CAUSEB_PCI              26
 426 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 427 #define CAUSEB_DC               27
 428 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 429 #define CAUSEB_CE               28
 430 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 431 #define CAUSEB_TI               30
 432 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 433 #define CAUSEB_BD               31
 434 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 435
 436 /*
 437  * Cause.ExcCode trap codes.
 438  */
 439 #define EXCCODE_INT             0       /* Interrupt pending */
 440 #define EXCCODE_MOD             1       /* TLB modified fault */
 441 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 442 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 443 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 444 #define EXCCODE_ADES            5       /* Address error on a store */
 445 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 446 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 447 #define EXCCODE_SYS             8       /* System call */
 448 #define EXCCODE_BP              9       /* Breakpoint */
 449 #define EXCCODE_RI              10      /* Reserved instruction exception */
 450 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 451 #define EXCCODE_OV              12      /* Arithmetic overflow */
 452 #define EXCCODE_TR              13      /* Trap instruction */
 453 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 454 #define EXCCODE_FPE             15      /* Floating point exception */
 455 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 456 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 457 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 458 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 459 #define EXCCODE_WATCH           23      /* Watch address reference */
 460 #define EXCCODE_MCHECK          24      /* Machine check */
 461 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 462 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 463 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 464 #define EXCCODE_CACHEERR        30      /* Parity/ECC occured on a core */
 465
 466 /* Implementation specific trap codes used by MIPS cores */
 467 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 468
 469 /* Implementation specific trap codes used by Loongson cores */
 470 #define LOONGSON_EXCCODE_GSEXC  16      /* Loongson-specific exception */
 471
 472 /*
 473  * Bits in the coprocessor 0 config register.
 474  */
 475 /* Generic bits.  */
 476 #define CONF_CM_CACHABLE_NO_WA          0
 477 #define CONF_CM_CACHABLE_WA             1
 478 #define CONF_CM_UNCACHED                2
 479 #define CONF_CM_CACHABLE_NONCOHERENT    3
 480 #define CONF_CM_CACHABLE_CE             4
 481 #define CONF_CM_CACHABLE_COW            5
 482 #define CONF_CM_CACHABLE_CUW            6
 483 #define CONF_CM_CACHABLE_ACCELERATED    7
 484 #define CONF_CM_CMASK                   7
 485 #define CONF_BE                 (_ULCAST_(1) << 15)
 486
 487 /* Bits common to various processors.  */
 488 #define CONF_CU                 (_ULCAST_(1) <<  3)
 489 #define CONF_DB                 (_ULCAST_(1) <<  4)
 490 #define CONF_IB                 (_ULCAST_(1) <<  5)
 491 #define CONF_DC                 (_ULCAST_(7) <<  6)
 492 #define CONF_IC                 (_ULCAST_(7) <<  9)
 493 #define CONF_EB                 (_ULCAST_(1) << 13)
 494 #define CONF_EM                 (_ULCAST_(1) << 14)
 495 #define CONF_SM                 (_ULCAST_(1) << 16)
 496 #define CONF_SC                 (_ULCAST_(1) << 17)
 497 #define CONF_EW                 (_ULCAST_(3) << 18)
 498 #define CONF_EP                 (_ULCAST_(15)<< 24)
 499 #define CONF_EC                 (_ULCAST_(7) << 28)
 500 #define CONF_CM                 (_ULCAST_(1) << 31)
 501
 502 /* Bits specific to the R4xx0.  */
 503 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 504 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 505 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 506
 507 /* Bits specific to the R5000.  */
 508 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 509 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 510
 511 /* Bits specific to the RM7000.  */
 512 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 513 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 514 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 515 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 516 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 517 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 518
 519 /* Bits specific to the R10000.  */
 520 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 521 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 522 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 523 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 524 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 525 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 526 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 527 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 528 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 529 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 530 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 531
 532 /* Bits specific to the VR41xx.  */
 533 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 534 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 535 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 536 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 537 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 538
 539 /* Bits specific to the R30xx.  */
 540 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 541 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 542 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 543 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 544 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 545 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 546 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 547 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 548 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 549
 550 /* Bits specific to the TX49.  */
 551 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 552 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 553 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 554 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 555
 556 /* Bits specific to the MIPS32/64 PRA.  */
 557 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 558 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 559 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 560 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 561 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 562 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 563 #define MIPS_CONF_BE            (_ULCAST_(1) << 15)
 564 #define MIPS_CONF_BM            (_ULCAST_(1) << 16)
 565 #define MIPS_CONF_MM            (_ULCAST_(3) << 17)
 566 #define MIPS_CONF_MM_SYSAD      (_ULCAST_(1) << 17)
 567 #define MIPS_CONF_MM_FULL       (_ULCAST_(2) << 17)
 568 #define MIPS_CONF_SB            (_ULCAST_(1) << 21)
 569 #define MIPS_CONF_UDI           (_ULCAST_(1) << 22)
 570 #define MIPS_CONF_DSP           (_ULCAST_(1) << 23)
 571 #define MIPS_CONF_ISP           (_ULCAST_(1) << 24)
 572 #define MIPS_CONF_KU            (_ULCAST_(3) << 25)
 573 #define MIPS_CONF_K23           (_ULCAST_(3) << 28)
 574 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 575
 576 /*
 577  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 578  */
 579 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 580 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 581 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 582 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 583 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 584 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 585 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 586 #define MIPS_CONF1_DA_SHF       7
 587 #define MIPS_CONF1_DA_SZ        3
 588 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 589 #define MIPS_CONF1_DL_SHF       10
 590 #define MIPS_CONF1_DL_SZ        3
 591 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 592 #define MIPS_CONF1_DS_SHF       13
 593 #define MIPS_CONF1_DS_SZ        3
 594 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 595 #define MIPS_CONF1_IA_SHF       16
 596 #define MIPS_CONF1_IA_SZ        3
 597 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 598 #define MIPS_CONF1_IL_SHF       19
 599 #define MIPS_CONF1_IL_SZ        3
 600 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 601 #define MIPS_CONF1_IS_SHF       22
 602 #define MIPS_CONF1_IS_SZ        3
 603 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 604 #define MIPS_CONF1_TLBS_SHIFT   (25)
 605 #define MIPS_CONF1_TLBS_SIZE    (6)
 606 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 607
 608 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 609 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 610 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 611 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 612 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 613 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 614 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 615 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 616
 617 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 618 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 619 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 620 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 621 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 622 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 623 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 624 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 625 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 626 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 627 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 628 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 629 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 630 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 631 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 632 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 633 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 634 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 635 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 636 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 637 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 638 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 639 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 640 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 641 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 642 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 643 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 644
 645 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 646 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 647 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 648 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 649 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 650 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 651 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 652 /* bits 10:8 in FTLB-only configurations */
 653 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 654 /* bits 12:8 in VTLB-FTLB only configurations */
 655 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 656 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 657 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 658 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 659 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 660 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 661 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 662 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 663 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 664 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 665 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 666 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 667
 668 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 669 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 670 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 671 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 672 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 673 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 674 #define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
 675 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 676 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 677 #define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
 678 #define MIPS_CONF5_MI           (_ULCAST_(1) << 17)
 679 #define MIPS_CONF5_CRCP         (_ULCAST_(1) << 18)
 680 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 681 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 682 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 683 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 684
 685 /* Config6 feature bits for proAptiv/P5600 */
 686
 687 /* Jump register cache prediction disable */
 688 #define MTI_CONF6_JRCD          (_ULCAST_(1) << 0)
 689 /* MIPSr6 extensions enable */
 690 #define MTI_CONF6_R6            (_ULCAST_(1) << 2)
 691 /* IFU Performance Control */
 692 #define MTI_CONF6_IFUPERFCTL    (_ULCAST_(3) << 10)
 693 #define MTI_CONF6_SYND          (_ULCAST_(1) << 13)
 694 /* Sleep state performance counter disable */
 695 #define MTI_CONF6_SPCD          (_ULCAST_(1) << 14)
 696 /* proAptiv FTLB on/off bit */
 697 #define MTI_CONF6_FTLBEN        (_ULCAST_(1) << 15)
 698 /* Disable load/store bonding */
 699 #define MTI_CONF6_DLSB          (_ULCAST_(1) << 21)
 700 /* FTLB probability bits */
 701 #define MTI_CONF6_FTLBP_SHIFT   (16)
 702
 703 /* Config6 feature bits for Loongson-3 */
 704
 705 /* Loongson-3 internal timer bit */
 706 #define LOONGSON_CONF6_INTIMER  (_ULCAST_(1) << 6)
 707 /* Loongson-3 external timer bit */
 708 #define LOONGSON_CONF6_EXTIMER  (_ULCAST_(1) << 7)
 709 /* Loongson-3 SFB on/off bit, STFill in manual */
 710 #define LOONGSON_CONF6_SFBEN    (_ULCAST_(1) << 8)
 711 /* Loongson-3's LL on exclusive cacheline */
 712 #define LOONGSON_CONF6_LLEXC    (_ULCAST_(1) << 16)
 713 /* Loongson-3's SC has a random delay */
 714 #define LOONGSON_CONF6_SCRAND   (_ULCAST_(1) << 17)
 715 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
 716 #define LOONGSON_CONF6_FTLBDIS  (_ULCAST_(1) << 22)
 717
 718 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 719
 720 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 721
 722 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 723 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 724
 725 /* Ingenic HPTLB off bits */
 726 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
 727
 728 /* Ingenic Config7 bits */
 729 #define MIPS_CONF7_BTB_LOOP_EN  (_ULCAST_(1) << 4)
 730
 731 /* Config7 Bits specific to MIPS Technologies. */
 732
 733 /* Performance counters implemented Per TC */
 734 #define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
 735
 736 /* WatchLo* register definitions */
 737 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 738
 739 /* WatchHi* register definitions */
 740 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 741 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 742 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 743 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 744 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 745 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 746 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 747 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 748 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 749 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 750 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 751 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 752 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 753
 754 /* PerfCnt control register definitions */
 755 #define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
 756 #define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
 757 #define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
 758 #define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
 759 #define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
 760 #define MIPS_PERFCTRL_EVENT_S   5
 761 #define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 762 #define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
 763 #define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
 764 #define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
 765 #define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
 766 #define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
 767 #define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
 768 #define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
 769 #define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
 770
 771 /* PerfCnt control register MT extensions used by MIPS cores */
 772 #define MIPS_PERFCTRL_VPEID_S   16
 773 #define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 774 #define MIPS_PERFCTRL_TCID_S    22
 775 #define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 776 #define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
 777 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
 778 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
 779 #define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
 780
 781 /* PerfCnt control register MT extensions used by BMIPS5000 */
 782 #define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
 783
 784 /* PerfCnt control register MT extensions used by Netlogic XLR */
 785 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
 786
 787 /* MAAR bit definitions */
 788 #define MIPS_MAAR_VH            (_U64CAST_(1) << 63)
 789 #define MIPS_MAAR_ADDR          GENMASK_ULL(55, 12)
 790 #define MIPS_MAAR_ADDR_SHIFT    12
 791 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 792 #define MIPS_MAAR_VL            (_ULCAST_(1) << 0)
 793 #ifdef CONFIG_XPA
 794 #define MIPS_MAAR_V             (MIPS_MAAR_VH | MIPS_MAAR_VL)
 795 #else
 796 #define MIPS_MAAR_V             MIPS_MAAR_VL
 797 #endif
 798 #define MIPS_MAARX_VH           (_ULCAST_(1) << 31)
 799 #define MIPS_MAARX_ADDR         0xF
 800 #define MIPS_MAARX_ADDR_SHIFT   32
 801
 802 /* MAARI bit definitions */
 803 #define MIPS_MAARI_INDEX        (_ULCAST_(0x3f) << 0)
 804
 805 /* EBase bit definitions */
 806 #define MIPS_EBASE_CPUNUM_SHIFT 0
 807 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 808 #define MIPS_EBASE_WG_SHIFT     11
 809 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 810 #define MIPS_EBASE_BASE_SHIFT   12
 811 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 812
 813 /* CMGCRBase bit definitions */
 814 #define MIPS_CMGCRB_BASE        11
 815 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 816
 817 /* LLAddr bit definitions */
 818 #define MIPS_LLADDR_LLB_SHIFT   0
 819 #define MIPS_LLADDR_LLB         (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 820
 821 /*
 822  * Bits in the MIPS32 Memory Segmentation registers.
 823  */
 824 #define MIPS_SEGCFG_PA_SHIFT    9
 825 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 826 #define MIPS_SEGCFG_AM_SHIFT    4
 827 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 828 #define MIPS_SEGCFG_EU_SHIFT    3
 829 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 830 #define MIPS_SEGCFG_C_SHIFT     0
 831 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 832
 833 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 834 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 835 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 836 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 837 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 838 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 839 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 840
 841 #define MIPS_PWFIELD_GDI_SHIFT  24
 842 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 843 #define MIPS_PWFIELD_UDI_SHIFT  18
 844 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 845 #define MIPS_PWFIELD_MDI_SHIFT  12
 846 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 847 #define MIPS_PWFIELD_PTI_SHIFT  6
 848 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 849 #define MIPS_PWFIELD_PTEI_SHIFT 0
 850 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 851
 852 #define MIPS_PWSIZE_PS_SHIFT    30
 853 #define MIPS_PWSIZE_PS_MASK     0x40000000
 854 #define MIPS_PWSIZE_GDW_SHIFT   24
 855 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 856 #define MIPS_PWSIZE_UDW_SHIFT   18
 857 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 858 #define MIPS_PWSIZE_MDW_SHIFT   12
 859 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 860 #define MIPS_PWSIZE_PTW_SHIFT   6
 861 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 862 #define MIPS_PWSIZE_PTEW_SHIFT  0
 863 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 864
 865 #define MIPS_PWCTL_PWEN_SHIFT   31
 866 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 867 #define MIPS_PWCTL_XK_SHIFT     28
 868 #define MIPS_PWCTL_XK_MASK      0x10000000
 869 #define MIPS_PWCTL_XS_SHIFT     27
 870 #define MIPS_PWCTL_XS_MASK      0x08000000
 871 #define MIPS_PWCTL_XU_SHIFT     26
 872 #define MIPS_PWCTL_XU_MASK      0x04000000
 873 #define MIPS_PWCTL_DPH_SHIFT    7
 874 #define MIPS_PWCTL_DPH_MASK     0x00000080
 875 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 876 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 877 #define MIPS_PWCTL_PSN_SHIFT    0
 878 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 879
 880 /* GuestCtl0 fields */
 881 #define MIPS_GCTL0_GM_SHIFT     31
 882 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 883 #define MIPS_GCTL0_RI_SHIFT     30
 884 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 885 #define MIPS_GCTL0_MC_SHIFT     29
 886 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 887 #define MIPS_GCTL0_CP0_SHIFT    28
 888 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 889 #define MIPS_GCTL0_AT_SHIFT     26
 890 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 891 #define MIPS_GCTL0_GT_SHIFT     25
 892 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 893 #define MIPS_GCTL0_CG_SHIFT     24
 894 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 895 #define MIPS_GCTL0_CF_SHIFT     23
 896 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 897 #define MIPS_GCTL0_G1_SHIFT     22
 898 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 899 #define MIPS_GCTL0_G0E_SHIFT    19
 900 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 901 #define MIPS_GCTL0_PT_SHIFT     18
 902 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 903 #define MIPS_GCTL0_RAD_SHIFT    9
 904 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 905 #define MIPS_GCTL0_DRG_SHIFT    8
 906 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 907 #define MIPS_GCTL0_G2_SHIFT     7
 908 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 909 #define MIPS_GCTL0_GEXC_SHIFT   2
 910 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 911 #define MIPS_GCTL0_SFC2_SHIFT   1
 912 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 913 #define MIPS_GCTL0_SFC1_SHIFT   0
 914 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 915
 916 /* GuestCtl0.AT Guest address translation control */
 917 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 918 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 919
 920 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 921 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 922 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 923 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 924 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 925 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 926 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 927 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 928
 929 /* GuestCtl0Ext fields */
 930 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 931 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 932 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 933 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 934 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 935 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 936 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 937 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 938 #define MIPS_GCTL0EXT_OG_SHIFT  2
 939 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 940 #define MIPS_GCTL0EXT_BG_SHIFT  1
 941 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 942 #define MIPS_GCTL0EXT_MG_SHIFT  0
 943 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 944
 945 /* GuestCtl0Ext.RPW Root page walk configuration */
 946 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 947 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 948 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 949
 950 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 951 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 952 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 953
 954 /* GuestCtl1 fields */
 955 #define MIPS_GCTL1_ID_SHIFT     0
 956 #define MIPS_GCTL1_ID_WIDTH     8
 957 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 958 #define MIPS_GCTL1_RID_SHIFT    16
 959 #define MIPS_GCTL1_RID_WIDTH    8
 960 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 961 #define MIPS_GCTL1_EID_SHIFT    24
 962 #define MIPS_GCTL1_EID_WIDTH    8
 963 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 964
 965 /* GuestID reserved for root context */
 966 #define MIPS_GCTL1_ROOT_GUESTID 0
 967
 968 /* CDMMBase register bit definitions */
 969 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 970 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 971 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 972 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 973 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 974 #define MIPS_CDMMBASE_ADDR_START 15
 975
 976 /* RDHWR register numbers */
 977 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 978 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 979 #define MIPS_HWR_CC             2       /* Cycle counter */
 980 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 981 #define MIPS_HWR_ULR            29      /* UserLocal */
 982 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 983 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 984
 985 /* Bits in HWREna register */
 986 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 987 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 988 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 989 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 990 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 991 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 992 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 993
 994 /*
 995  * Bitfields in the TX39 family CP0 Configuration Register 3
 996  */
 997 #define TX39_CONF_ICS_SHIFT     19
 998 #define TX39_CONF_ICS_MASK      0x00380000
 999 #define TX39_CONF_ICS_1KB       0x00000000
1000 #define TX39_CONF_ICS_2KB       0x00080000
1001 #define TX39_CONF_ICS_4KB       0x00100000
1002 #define TX39_CONF_ICS_8KB       0x00180000
1003 #define TX39_CONF_ICS_16KB      0x00200000
1004
1005 #define TX39_CONF_DCS_SHIFT     16
1006 #define TX39_CONF_DCS_MASK      0x00070000
1007 #define TX39_CONF_DCS_1KB       0x00000000
1008 #define TX39_CONF_DCS_2KB       0x00010000
1009 #define TX39_CONF_DCS_4KB       0x00020000
1010 #define TX39_CONF_DCS_8KB       0x00030000
1011 #define TX39_CONF_DCS_16KB      0x00040000
1012
1013 #define TX39_CONF_CWFON         0x00004000
1014 #define TX39_CONF_WBON          0x00002000
1015 #define TX39_CONF_RF_SHIFT      10
1016 #define TX39_CONF_RF_MASK       0x00000c00
1017 #define TX39_CONF_DOZE          0x00000200
1018 #define TX39_CONF_HALT          0x00000100
1019 #define TX39_CONF_LOCK          0x00000080
1020 #define TX39_CONF_ICE           0x00000020
1021 #define TX39_CONF_DCE           0x00000010
1022 #define TX39_CONF_IRSIZE_SHIFT  2
1023 #define TX39_CONF_IRSIZE_MASK   0x0000000c
1024 #define TX39_CONF_DRSIZE_SHIFT  0
1025 #define TX39_CONF_DRSIZE_MASK   0x00000003
1026
1027 /*
1028  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1029  */
1030 /* Disable Branch Target Address Cache */
1031 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
1032 /* Enable Branch Prediction Global History */
1033 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
1034 /* Disable Branch Return Cache */
1035 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
1036
1037 /* Flush BTB */
1038 #define LOONGSON_DIAG_BTB       (_ULCAST_(1) << 1)
1039 /* Flush ITLB */
1040 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
1041 /* Flush DTLB */
1042 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
1043 /* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1044 #define LOONGSON_DIAG_UCAC      (_ULCAST_(1) << 8)
1045 /* Flush VTLB */
1046 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
1047 /* Flush FTLB */
1048 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
1049
1050 /*
1051  * Diag1 (GSCause in Loongson-speak) fields
1052  */
1053 /* Loongson-specific exception code (GSExcCode) */
1054 #define LOONGSON_DIAG1_EXCCODE_SHIFT    2
1055 #define LOONGSON_DIAG1_EXCCODE          GENMASK(6, 2)
1056
1057 /* CvmCtl register field definitions */
1058 #define CVMCTL_IPPCI_SHIFT      7
1059 #define CVMCTL_IPPCI            (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1060 #define CVMCTL_IPTI_SHIFT       4
1061 #define CVMCTL_IPTI             (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1062
1063 /* CvmMemCtl2 register field definitions */
1064 #define CVMMEMCTL2_INHIBITTS    (_U64CAST_(1) << 17)
1065
1066 /* CvmVMConfig register field definitions */
1067 #define CVMVMCONF_DGHT          (_U64CAST_(1) << 60)
1068 #define CVMVMCONF_MMUSIZEM1_S   12
1069 #define CVMVMCONF_MMUSIZEM1     (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1070 #define CVMVMCONF_RMMUSIZEM1_S  0
1071 #define CVMVMCONF_RMMUSIZEM1    (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1072
1073 /* Debug register field definitions */
1074 #define MIPS_DEBUG_DBP_SHIFT    1
1075 #define MIPS_DEBUG_DBP          (_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT)
1076
1077 /*
1078  * Coprocessor 1 (FPU) register names
1079  */
1080 #define CP1_REVISION    $0
1081 #define CP1_UFR         $1
1082 #define CP1_UNFR        $4
1083 #define CP1_FCCR        $25
1084 #define CP1_FEXR        $26
1085 #define CP1_FENR        $28
1086 #define CP1_STATUS      $31
1087
1088
1089 /*
1090  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1091  */
1092 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
1093 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
1094 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
1095 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
1096 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
1097 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
1098 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
1099 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
1100 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
1101 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
1102
1103 /*
1104  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1105  */
1106 #define MIPS_FCCR_CONDX_S       0
1107 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1108 #define MIPS_FCCR_COND0_S       0
1109 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1110 #define MIPS_FCCR_COND1_S       1
1111 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1112 #define MIPS_FCCR_COND2_S       2
1113 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1114 #define MIPS_FCCR_COND3_S       3
1115 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1116 #define MIPS_FCCR_COND4_S       4
1117 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1118 #define MIPS_FCCR_COND5_S       5
1119 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1120 #define MIPS_FCCR_COND6_S       6
1121 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1122 #define MIPS_FCCR_COND7_S       7
1123 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1124
1125 /*
1126  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1127  */
1128 #define MIPS_FENR_FS_S          2
1129 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
1130
1131 /*
1132  * FPU Status Register Values
1133  */
1134 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
1135 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
1136
1137 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
1138 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
1139
1140 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
1141 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
1142 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
1143 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
1144 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
1145 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
1146 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
1147 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
1148 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
1149 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1150 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1151 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1152 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1153 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1154 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1155 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1156
1157 /*
1158  * Bits 22:20 of the FPU Status Register will be read as 0,
1159  * and should be written as zero.
1160  * MAC2008 was removed in Release 5 so we still treat it as
1161  * reserved.
1162  */
1163 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1164
1165 #define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1166 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1167 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1168
1169 /*
1170  * X the exception cause indicator
1171  * E the exception enable
1172  * S the sticky/flag bit
1173 */
1174 #define FPU_CSR_ALL_X   0x0003f000
1175 #define FPU_CSR_UNI_X   0x00020000
1176 #define FPU_CSR_INV_X   0x00010000
1177 #define FPU_CSR_DIV_X   0x00008000
1178 #define FPU_CSR_OVF_X   0x00004000
1179 #define FPU_CSR_UDF_X   0x00002000
1180 #define FPU_CSR_INE_X   0x00001000
1181
1182 #define FPU_CSR_ALL_E   0x00000f80
1183 #define FPU_CSR_INV_E   0x00000800
1184 #define FPU_CSR_DIV_E   0x00000400
1185 #define FPU_CSR_OVF_E   0x00000200
1186 #define FPU_CSR_UDF_E   0x00000100
1187 #define FPU_CSR_INE_E   0x00000080
1188
1189 #define FPU_CSR_ALL_S   0x0000007c
1190 #define FPU_CSR_INV_S   0x00000040
1191 #define FPU_CSR_DIV_S   0x00000020
1192 #define FPU_CSR_OVF_S   0x00000010
1193 #define FPU_CSR_UDF_S   0x00000008
1194 #define FPU_CSR_INE_S   0x00000004
1195
1196 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1197 #define FPU_CSR_RM      0x00000003
1198 #define FPU_CSR_RN      0x0     /* nearest */
1199 #define FPU_CSR_RZ      0x1     /* towards zero */
1200 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1201 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1202
1203
1204 #ifndef __ASSEMBLY__
1205
1206 /*
1207  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1208  */
1209 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1210     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1211 #define get_isa16_mode(x)               ((x) & 0x1)
1212 #define msk_isa16_mode(x)               ((x) & ~0x1)
1213 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1214 #else
1215 #define get_isa16_mode(x)               0
1216 #define msk_isa16_mode(x)               (x)
1217 #define set_isa16_mode(x)               do { } while(0)
1218 #endif
1219
1220 /*
1221  * microMIPS instructions can be 16-bit or 32-bit in length. This
1222  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1223  */
1224 static inline int mm_insn_16bit(u16 insn)
1225 {
1226         u16 opcode = (insn >> 10) & 0x7;
1227
1228         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1229 }
1230
1231 /*
1232  * Helper macros for generating raw instruction encodings in inline asm.
1233  */
1234 #ifdef CONFIG_CPU_MICROMIPS
1235 #define _ASM_INSN16_IF_MM(_enc)                 \
1236         ".insn\n\t"                             \
1237         ".hword (" #_enc ")\n\t"
1238 #define _ASM_INSN32_IF_MM(_enc)                 \
1239         ".insn\n\t"                             \
1240         ".hword ((" #_enc ") >> 16)\n\t"        \
1241         ".hword ((" #_enc ") & 0xffff)\n\t"
1242 #else
1243 #define _ASM_INSN_IF_MIPS(_enc)                 \
1244         ".insn\n\t"                             \
1245         ".word (" #_enc ")\n\t"
1246 #endif
1247
1248 #ifndef _ASM_INSN16_IF_MM
1249 #define _ASM_INSN16_IF_MM(_enc)
1250 #endif
1251 #ifndef _ASM_INSN32_IF_MM
1252 #define _ASM_INSN32_IF_MM(_enc)
1253 #endif
1254 #ifndef _ASM_INSN_IF_MIPS
1255 #define _ASM_INSN_IF_MIPS(_enc)
1256 #endif
1257
1258 /*
1259  * parse_r var, r - Helper assembler macro for parsing register names.
1260  *
1261  * This converts the register name in $n form provided in \r to the
1262  * corresponding register number, which is assigned to the variable \var. It is
1263  * needed to allow explicit encoding of instructions in inline assembly where
1264  * registers are chosen by the compiler in $n form, allowing us to avoid using
1265  * fixed register numbers.
1266  *
1267  * It also allows newer instructions (not implemented by the assembler) to be
1268  * transparently implemented using assembler macros, instead of needing separate
1269  * cases depending on toolchain support.
1270  *
1271  * Simple usage example:
1272  * __asm__ __volatile__("parse_r __rt, %0\n\t"
1273  *                      ".insn\n\t"
1274  *                      "# di    %0\n\t"
1275  *                      ".word   (0x41606000 | (__rt << 16))"
1276  *                      : "=r" (status);
1277  */
1278
1279 /* Match an individual register number and assign to \var */
1280 #define _IFC_REG(n)                             \
1281         ".ifc   \\r, $" #n "\n\t"               \
1282         "\\var  = " #n "\n\t"                   \
1283         ".endif\n\t"
1284
1285 #define _ASM_SET_PARSE_R                                                \
1286         ".macro parse_r var r\n\t"                                      \
1287         "\\var  = -1\n\t"                                               \
1288         _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)              \
1289         _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)              \
1290         _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)             \
1291         _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)             \
1292         _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)             \
1293         _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)             \
1294         _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)             \
1295         _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)             \
1296         ".iflt  \\var\n\t"                                              \
1297         ".error \"Unable to parse register name \\r\"\n\t"              \
1298         ".endif\n\t"                                                    \
1299         ".endm\n\t"
1300 #define _ASM_UNSET_PARSE_R ".purgem parse_r\n\t"
1301
1302 /*
1303  * C macros for generating assembler macros for common instruction formats.
1304  *
1305  * The names of the operands can be chosen by the caller, and the encoding of
1306  * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1307  * the ENC encodings.
1308  */
1309
1310 /* Instructions with 1 register operand & 1 immediate operand */
1311 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC)                                \
1312                 ".macro " #OP " " #R1 ", " #I2 "\n\t"                   \
1313                 _ASM_SET_PARSE_R                                        \
1314                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1315                 ENC                                                     \
1316                 _ASM_UNSET_PARSE_R                                      \
1317                 ".endm\n\t"
1318
1319 /* Instructions with 2 register operands */
1320 #define _ASM_MACRO_2R(OP, R1, R2, ENC)                                  \
1321                 ".macro " #OP " " #R1 ", " #R2 "\n\t"                   \
1322                 _ASM_SET_PARSE_R                                        \
1323                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1324                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1325                 ENC                                                     \
1326                 _ASM_UNSET_PARSE_R                                      \
1327                 ".endm\n\t"
1328
1329 /* Instructions with 3 register operands */
1330 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)                              \
1331                 ".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t"          \
1332                 _ASM_SET_PARSE_R                                        \
1333                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1334                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1335                 "parse_r __" #R3 ", \\" #R3 "\n\t"                      \
1336                 ENC                                                     \
1337                 _ASM_UNSET_PARSE_R                                      \
1338                 ".endm\n\t"
1339
1340 /* Instructions with 2 register operands and 1 optional select operand */
1341 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)                         \
1342                 ".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"    \
1343                 _ASM_SET_PARSE_R                                        \
1344                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1345                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1346                 ENC                                                     \
1347                 _ASM_UNSET_PARSE_R                                      \
1348                 ".endm\n\t"
1349
1350 /*
1351  * TLB Invalidate Flush
1352  */
1353 static inline void tlbinvf(void)
1354 {
1355         __asm__ __volatile__(
1356                 ".set push\n\t"
1357                 ".set noreorder\n\t"
1358                 "# tlbinvf\n\t"
1359                 _ASM_INSN_IF_MIPS(0x42000004)
1360                 _ASM_INSN32_IF_MM(0x0000537c)
1361                 ".set pop");
1362 }
1363
1364
1365 /*
1366  * Functions to access the R10000 performance counters.  These are basically
1367  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1368  * performance counter number encoded into bits 1 ... 5 of the instruction.
1369  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1370  * disassembler these will look like an access to sel 0 or 1.
1371  */
1372 #define read_r10k_perf_cntr(counter)                            \
1373 ({                                                              \
1374         unsigned int __res;                                     \
1375         __asm__ __volatile__(                                   \
1376         "mfpc\t%0, %1"                                          \
1377         : "=r" (__res)                                          \
1378         : "i" (counter));                                       \
1379                                                                 \
1380         __res;                                                  \
1381 })
1382
1383 #define write_r10k_perf_cntr(counter,val)                       \
1384 do {                                                            \
1385         __asm__ __volatile__(                                   \
1386         "mtpc\t%0, %1"                                          \
1387         :                                                       \
1388         : "r" (val), "i" (counter));                            \
1389 } while (0)
1390
1391 #define read_r10k_perf_event(counter)                           \
1392 ({                                                              \
1393         unsigned int __res;                                     \
1394         __asm__ __volatile__(                                   \
1395         "mfps\t%0, %1"                                          \
1396         : "=r" (__res)                                          \
1397         : "i" (counter));                                       \
1398                                                                 \
1399         __res;                                                  \
1400 })
1401
1402 #define write_r10k_perf_cntl(counter,val)                       \
1403 do {                                                            \
1404         __asm__ __volatile__(                                   \
1405         "mtps\t%0, %1"                                          \
1406         :                                                       \
1407         : "r" (val), "i" (counter));                            \
1408 } while (0)
1409
1410
1411 /*
1412  * Macros to access the system control coprocessor
1413  */
1414
1415 #define ___read_32bit_c0_register(source, sel, vol)                     \
1416 ({ unsigned int __res;                                                  \
1417         if (sel == 0)                                                   \
1418                 __asm__ vol(                                            \
1419                         "mfc0\t%0, " #source "\n\t"                     \
1420                         : "=r" (__res));                                \
1421         else                                                            \
1422                 __asm__ vol(                                            \
1423                         ".set\tpush\n\t"                                \
1424                         ".set\tmips32\n\t"                              \
1425                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1426                         ".set\tpop\n\t"                                 \
1427                         : "=r" (__res));                                \
1428         __res;                                                          \
1429 })
1430
1431 #define ___read_64bit_c0_register(source, sel, vol)                     \
1432 ({ unsigned long long __res;                                            \
1433         if (sizeof(unsigned long) == 4)                                 \
1434                 __res = __read_64bit_c0_split(source, sel, vol);        \
1435         else if (sel == 0)                                              \
1436                 __asm__ vol(                                            \
1437                         ".set\tpush\n\t"                                \
1438                         ".set\tmips3\n\t"                               \
1439                         "dmfc0\t%0, " #source "\n\t"                    \
1440                         ".set\tpop"                                     \
1441                         : "=r" (__res));                                \
1442         else                                                            \
1443                 __asm__ vol(                                            \
1444                         ".set\tpush\n\t"                                \
1445                         ".set\tmips64\n\t"                              \
1446                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1447                         ".set\tpop"                                     \
1448                         : "=r" (__res));                                \
1449         __res;                                                          \
1450 })
1451
1452 #define __read_32bit_c0_register(source, sel)                           \
1453         ___read_32bit_c0_register(source, sel, __volatile__)
1454
1455 #define __read_const_32bit_c0_register(source, sel)                     \
1456         ___read_32bit_c0_register(source, sel,)
1457
1458 #define __read_64bit_c0_register(source, sel)                           \
1459         ___read_64bit_c0_register(source, sel, __volatile__)
1460
1461 #define __read_const_64bit_c0_register(source, sel)                     \
1462         ___read_64bit_c0_register(source, sel,)
1463
1464 #define __write_32bit_c0_register(register, sel, value)                 \
1465 do {                                                                    \
1466         if (sel == 0)                                                   \
1467                 __asm__ __volatile__(                                   \
1468                         "mtc0\t%z0, " #register "\n\t"                  \
1469                         : : "Jr" ((unsigned int)(value)));              \
1470         else                                                            \
1471                 __asm__ __volatile__(                                   \
1472                         ".set\tpush\n\t"                                \
1473                         ".set\tmips32\n\t"                              \
1474                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1475                         ".set\tpop"                                     \
1476                         : : "Jr" ((unsigned int)(value)));              \
1477 } while (0)
1478
1479 #define __write_64bit_c0_register(register, sel, value)                 \
1480 do {                                                                    \
1481         if (sizeof(unsigned long) == 4)                                 \
1482                 __write_64bit_c0_split(register, sel, value);           \
1483         else if (sel == 0)                                              \
1484                 __asm__ __volatile__(                                   \
1485                         ".set\tpush\n\t"                                \
1486                         ".set\tmips3\n\t"                               \
1487                         "dmtc0\t%z0, " #register "\n\t"                 \
1488                         ".set\tpop"                                     \
1489                         : : "Jr" (value));                              \
1490         else                                                            \
1491                 __asm__ __volatile__(                                   \
1492                         ".set\tpush\n\t"                                \
1493                         ".set\tmips64\n\t"                              \
1494                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1495                         ".set\tpop"                                     \
1496                         : : "Jr" (value));                              \
1497 } while (0)
1498
1499 #define __read_ulong_c0_register(reg, sel)                              \
1500         ((sizeof(unsigned long) == 4) ?                                 \
1501         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1502         (unsigned long) __read_64bit_c0_register(reg, sel))
1503
1504 #define __read_const_ulong_c0_register(reg, sel)                        \
1505         ((sizeof(unsigned long) == 4) ?                                 \
1506         (unsigned long) __read_const_32bit_c0_register(reg, sel) :      \
1507         (unsigned long) __read_const_64bit_c0_register(reg, sel))
1508
1509 #define __write_ulong_c0_register(reg, sel, val)                        \
1510 do {                                                                    \
1511         if (sizeof(unsigned long) == 4)                                 \
1512                 __write_32bit_c0_register(reg, sel, val);               \
1513         else                                                            \
1514                 __write_64bit_c0_register(reg, sel, val);               \
1515 } while (0)
1516
1517 /*
1518  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1519  */
1520 #define __read_32bit_c0_ctrl_register(source)                           \
1521 ({ unsigned int __res;                                                  \
1522         __asm__ __volatile__(                                           \
1523                 "cfc0\t%0, " #source "\n\t"                             \
1524                 : "=r" (__res));                                        \
1525         __res;                                                          \
1526 })
1527
1528 #define __write_32bit_c0_ctrl_register(register, value)                 \
1529 do {                                                                    \
1530         __asm__ __volatile__(                                           \
1531                 "ctc0\t%z0, " #register "\n\t"                          \
1532                 : : "Jr" ((unsigned int)(value)));                      \
1533 } while (0)
1534
1535 /*
1536  * These versions are only needed for systems with more than 38 bits of
1537  * physical address space running the 32-bit kernel.  That's none atm :-)
1538  */
1539 #define __read_64bit_c0_split(source, sel, vol)                         \
1540 ({                                                                      \
1541         unsigned long long __val;                                       \
1542         unsigned long __flags;                                          \
1543                                                                         \
1544         local_irq_save(__flags);                                        \
1545         if (sel == 0)                                                   \
1546                 __asm__ vol(                                            \
1547                         ".set\tpush\n\t"                                \
1548                         ".set\tmips64\n\t"                              \
1549                         "dmfc0\t%L0, " #source "\n\t"                   \
1550                         "dsra\t%M0, %L0, 32\n\t"                        \
1551                         "sll\t%L0, %L0, 0\n\t"                          \
1552                         ".set\tpop"                                     \
1553                         : "=r" (__val));                                \
1554         else                                                            \
1555                 __asm__ vol(                                            \
1556                         ".set\tpush\n\t"                                \
1557                         ".set\tmips64\n\t"                              \
1558                         "dmfc0\t%L0, " #source ", " #sel "\n\t"         \
1559                         "dsra\t%M0, %L0, 32\n\t"                        \
1560                         "sll\t%L0, %L0, 0\n\t"                          \
1561                         ".set\tpop"                                     \
1562                         : "=r" (__val));                                \
1563         local_irq_restore(__flags);                                     \
1564                                                                         \
1565         __val;                                                          \
1566 })
1567
1568 #define __write_64bit_c0_split(source, sel, val)                        \
1569 do {                                                                    \
1570         unsigned long long __tmp = (val);                               \
1571         unsigned long __flags;                                          \
1572                                                                         \
1573         local_irq_save(__flags);                                        \
1574         if (MIPS_ISA_REV >= 2)                                          \
1575                 __asm__ __volatile__(                                   \
1576                         ".set\tpush\n\t"                                \
1577                         ".set\t" MIPS_ISA_LEVEL "\n\t"                  \
1578                         "dins\t%L0, %M0, 32, 32\n\t"                    \
1579                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1580                         ".set\tpop"                                     \
1581                         : "+r" (__tmp));                                \
1582         else if (sel == 0)                                              \
1583                 __asm__ __volatile__(                                   \
1584                         ".set\tpush\n\t"                                \
1585                         ".set\tmips64\n\t"                              \
1586                         "dsll\t%L0, %L0, 32\n\t"                        \
1587                         "dsrl\t%L0, %L0, 32\n\t"                        \
1588                         "dsll\t%M0, %M0, 32\n\t"                        \
1589                         "or\t%L0, %L0, %M0\n\t"                         \
1590                         "dmtc0\t%L0, " #source "\n\t"                   \
1591                         ".set\tpop"                                     \
1592                         : "+r" (__tmp));                                \
1593         else                                                            \
1594                 __asm__ __volatile__(                                   \
1595                         ".set\tpush\n\t"                                \
1596                         ".set\tmips64\n\t"                              \
1597                         "dsll\t%L0, %L0, 32\n\t"                        \
1598                         "dsrl\t%L0, %L0, 32\n\t"                        \
1599                         "dsll\t%M0, %M0, 32\n\t"                        \
1600                         "or\t%L0, %L0, %M0\n\t"                         \
1601                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1602                         ".set\tpop"                                     \
1603                         : "+r" (__tmp));                                \
1604         local_irq_restore(__flags);                                     \
1605 } while (0)
1606
1607 #ifndef TOOLCHAIN_SUPPORTS_XPA
1608 #define _ASM_SET_MFHC0                                                  \
1609         _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,                            \
1610                          _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)        \
1611                          _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11))
1612 #define _ASM_UNSET_MFHC0 ".purgem mfhc0\n\t"
1613 #define _ASM_SET_MTHC0                                                  \
1614         _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,                            \
1615                          _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)        \
1616                          _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
1617 #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
1618 #else   /* !TOOLCHAIN_SUPPORTS_XPA */
1619 #define _ASM_SET_MFHC0 ".set\txpa\n\t"
1620 #define _ASM_SET_MTHC0 ".set\txpa\n\t"
1621 #define _ASM_UNSET_MFHC0
1622 #define _ASM_UNSET_MTHC0
1623 #endif
1624
1625 #define __readx_32bit_c0_register(source, sel)                          \
1626 ({                                                                      \
1627         unsigned int __res;                                             \
1628                                                                         \
1629         __asm__ __volatile__(                                           \
1630         "       .set    push                                    \n"     \
1631         "       .set    mips32r2                                \n"     \
1632         _ASM_SET_MFHC0                                                  \
1633         "       mfhc0   %0, " #source ", %1                     \n"     \
1634         _ASM_UNSET_MFHC0                                                \
1635         "       .set    pop                                     \n"     \
1636         : "=r" (__res)                                                  \
1637         : "i" (sel));                                                   \
1638         __res;                                                          \
1639 })
1640
1641 #define __writex_32bit_c0_register(register, sel, value)                \
1642 do {                                                                    \
1643         __asm__ __volatile__(                                           \
1644         "       .set    push                                    \n"     \
1645         "       .set    mips32r2                                \n"     \
1646         _ASM_SET_MTHC0                                                  \
1647         "       mthc0   %z0, " #register ", %1                  \n"     \
1648         _ASM_UNSET_MTHC0                                                \
1649         "       .set    pop                                     \n"     \
1650         :                                                               \
1651         : "Jr" (value), "i" (sel));                                     \
1652 } while (0)
1653
1654 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1655 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1656
1657 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1658 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1659
1660 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1661 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1662
1663 #define readx_c0_entrylo0()     __readx_32bit_c0_register($2, 0)
1664 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1665
1666 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1667 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1668
1669 #define readx_c0_entrylo1()     __readx_32bit_c0_register($3, 0)
1670 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1671
1672 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1673 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1674
1675 #define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
1676
1677 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1678 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1679
1680 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1681 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1682
1683 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1684 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1685
1686 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1687 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1688
1689 #define read_c0_memorymapid()           __read_32bit_c0_register($4, 5)
1690 #define write_c0_memorymapid(val)       __write_32bit_c0_register($4, 5, val)
1691
1692 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1693 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1694
1695 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1696 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1697
1698 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1699 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1700
1701 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1702
1703 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1704 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1705
1706 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1707 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1708
1709 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1710 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1711
1712 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1713 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1714
1715 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1716 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1717
1718 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1719 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1720
1721 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1722 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1723
1724 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1725 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1726
1727 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1728 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1729
1730 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1731 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1732
1733 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1734
1735 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1736
1737 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1738 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1739
1740 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1741 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1742
1743 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1744 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1745
1746 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1747 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1748
1749 #define read_c0_prid()          __read_const_32bit_c0_register($15, 0)
1750
1751 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1752
1753 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1754 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1755 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1756 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1757 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1758 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1759 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1760 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1761 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1762 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1763 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1764 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1765 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1766 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1767 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1768 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1769
1770 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1771 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1772 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1773 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1774 #define readx_c0_maar()         __readx_32bit_c0_register($17, 1)
1775 #define writex_c0_maar(val)     __writex_32bit_c0_register($17, 1, val)
1776 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1777 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1778
1779 /*
1780  * The WatchLo register.  There may be up to 8 of them.
1781  */
1782 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1783 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1784 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1785 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1786 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1787 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1788 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1789 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1790 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1791 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1792 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1793 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1794 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1795 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1796 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1797 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1798
1799 /*
1800  * The WatchHi register.  There may be up to 8 of them.
1801  */
1802 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1803 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1804 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1805 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1806 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1807 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1808 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1809 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1810
1811 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1812 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1813 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1814 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1815 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1816 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1817 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1818 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1819
1820 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1821 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1822
1823 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1824 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1825
1826 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1827 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1828
1829 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1830 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1831
1832 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1833 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1834 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1835
1836 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1837 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1838
1839 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1840 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1841
1842 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1843 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1844
1845 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1846 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1847
1848 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1849 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1850
1851 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1852 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1853
1854 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1855 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1856
1857 /*
1858  * MIPS32 / MIPS64 performance counters
1859  */
1860 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1861 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1862 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1863 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1864 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1865 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1866 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1867 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1868 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1869 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1870 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1871 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1872 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1873 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1874 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1875 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1876 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1877 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1878 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1879 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1880 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1881 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1882 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1883 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1884
1885 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1886 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1887
1888 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1889 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1890
1891 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1892
1893 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1894 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1895
1896 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1897 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1898
1899 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1900 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1901
1902 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1903 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1904
1905 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1906 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1907
1908 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1909 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1910
1911 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1912 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1913
1914 /* MIPSR2 */
1915 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1916 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1917
1918 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1919 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1920
1921 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1922 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1923
1924 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1925 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1926
1927 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1928 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1929
1930 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1931 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1932
1933 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1934 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1935
1936 /* MIPSR3 */
1937 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1938 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1939
1940 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1941 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1942
1943 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1944 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1945
1946 /* Hardware Page Table Walker */
1947 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1948 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1949
1950 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1951 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1952
1953 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1954 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1955
1956 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1957 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1958
1959 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1960 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1961
1962 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1963 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1964
1965 /* Cavium OCTEON (cnMIPS) */
1966 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1967 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1968
1969 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1970 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1971
1972 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1973 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1974
1975 #define read_c0_cvmmemctl2()    __read_64bit_c0_register($16, 6)
1976 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1977
1978 #define read_c0_cvmvmconfig()   __read_64bit_c0_register($16, 7)
1979 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1980
1981 /*
1982  * The cacheerr registers are not standardized.  On OCTEON, they are
1983  * 64 bits wide.
1984  */
1985 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1986 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1987
1988 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1989 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1990
1991 /* BMIPS3300 */
1992 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1993 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1994
1995 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1996 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1997
1998 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1999 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
2000
2001 /* BMIPS43xx */
2002 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
2003 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
2004
2005 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
2006 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
2007
2008 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
2009 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
2010
2011 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
2012 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
2013
2014 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
2015 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
2016
2017 /* BMIPS5000 */
2018 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
2019 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
2020
2021 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
2022 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
2023
2024 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
2025 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
2026
2027 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
2028 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
2029
2030 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
2031 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
2032
2033 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
2034 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
2035
2036 /* Ingenic page ctrl register */
2037 #define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
2038
2039 /*
2040  * Macros to access the guest system control coprocessor
2041  */
2042
2043 #ifndef TOOLCHAIN_SUPPORTS_VIRT
2044 #define _ASM_SET_MFGC0                                                  \
2045         _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,                            \
2046                          _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)        \
2047                          _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2048 #define _ASM_UNSET_MFGC0 ".purgem mfgc0\n\t"
2049 #define _ASM_SET_DMFGC0                                                 \
2050         _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,                           \
2051                          _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)        \
2052                          _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2053 #define _ASM_UNSET_DMFGC0 ".purgem dmfgc0\n\t"
2054 #define _ASM_SET_MTGC0                                                  \
2055         _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,                            \
2056                          _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)        \
2057                          _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2058 #define _ASM_UNSET_MTGC0 ".purgem mtgc0\n\t"
2059 #define _ASM_SET_DMTGC0                                                 \
2060         _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,                           \
2061                          _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)        \
2062                          _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2063 #define _ASM_UNSET_DMTGC0 ".purgem dmtgc0\n\t"
2064
2065 #define __tlbgp()                                                       \
2066                 _ASM_INSN_IF_MIPS(0x42000010)                           \
2067                 _ASM_INSN32_IF_MM(0x0000017c)
2068 #define __tlbgr()                                                       \
2069                 _ASM_INSN_IF_MIPS(0x42000009)                           \
2070                 _ASM_INSN32_IF_MM(0x0000117c)
2071 #define __tlbgwi()                                                      \
2072                 _ASM_INSN_IF_MIPS(0x4200000a)                           \
2073                 _ASM_INSN32_IF_MM(0x0000217c)
2074 #define __tlbgwr()                                                      \
2075                 _ASM_INSN_IF_MIPS(0x4200000e)                           \
2076                 _ASM_INSN32_IF_MM(0x0000317c)
2077 #define __tlbginvf()                                                    \
2078                 _ASM_INSN_IF_MIPS(0x4200000c)                           \
2079                 _ASM_INSN32_IF_MM(0x0000517c)
2080 #else   /* !TOOLCHAIN_SUPPORTS_VIRT */
2081 #define _ASM_SET_VIRT ".set\tvirt\n\t"
2082 #define _ASM_SET_MFGC0  _ASM_SET_VIRT
2083 #define _ASM_SET_DMFGC0 _ASM_SET_VIRT
2084 #define _ASM_SET_MTGC0  _ASM_SET_VIRT
2085 #define _ASM_SET_DMTGC0 _ASM_SET_VIRT
2086 #define _ASM_UNSET_MFGC0
2087 #define _ASM_UNSET_DMFGC0
2088 #define _ASM_UNSET_MTGC0
2089 #define _ASM_UNSET_DMTGC0
2090
2091 #define __tlbgp()       _ASM_SET_VIRT "tlbgp\n\t"
2092 #define __tlbgr()       _ASM_SET_VIRT "tlbgr\n\t"
2093 #define __tlbgwi()      _ASM_SET_VIRT "tlbgwi\n\t"
2094 #define __tlbgwr()      _ASM_SET_VIRT "tlbgwr\n\t"
2095 #define __tlbginvf()    _ASM_SET_VIRT "tlbginvf\n\t"
2096 #endif
2097
2098 #define __read_32bit_gc0_register(source, sel)                          \
2099 ({ int __res;                                                           \
2100         __asm__ __volatile__(                                           \
2101                 ".set\tpush\n\t"                                        \
2102                 ".set\tmips32r5\n\t"                                    \
2103                 _ASM_SET_MFGC0                                          \
2104                 "mfgc0\t%0, " #source ", %1\n\t"                        \
2105                 _ASM_UNSET_MFGC0                                        \
2106                 ".set\tpop"                                             \
2107                 : "=r" (__res)                                          \
2108                 : "i" (sel));                                           \
2109         __res;                                                          \
2110 })
2111
2112 #define __read_64bit_gc0_register(source, sel)                          \
2113 ({ unsigned long long __res;                                            \
2114         __asm__ __volatile__(                                           \
2115                 ".set\tpush\n\t"                                        \
2116                 ".set\tmips64r5\n\t"                                    \
2117                 _ASM_SET_DMFGC0                                         \
2118                 "dmfgc0\t%0, " #source ", %1\n\t"                       \
2119                 _ASM_UNSET_DMFGC0                                       \
2120                 ".set\tpop"                                             \
2121                 : "=r" (__res)                                          \
2122                 : "i" (sel));                                           \
2123         __res;                                                          \
2124 })
2125
2126 #define __write_32bit_gc0_register(register, sel, value)                \
2127 do {                                                                    \
2128         __asm__ __volatile__(                                           \
2129                 ".set\tpush\n\t"                                        \
2130                 ".set\tmips32r5\n\t"                                    \
2131                 _ASM_SET_MTGC0                                          \
2132                 "mtgc0\t%z0, " #register ", %1\n\t"                     \
2133                 _ASM_UNSET_MTGC0                                        \
2134                 ".set\tpop"                                             \
2135                 : : "Jr" ((unsigned int)(value)),                       \
2136                     "i" (sel));                                         \
2137 } while (0)
2138
2139 #define __write_64bit_gc0_register(register, sel, value)                \
2140 do {                                                                    \
2141         __asm__ __volatile__(                                           \
2142                 ".set\tpush\n\t"                                        \
2143                 ".set\tmips64r5\n\t"                                    \
2144                 _ASM_SET_DMTGC0                                         \
2145                 "dmtgc0\t%z0, " #register ", %1\n\t"                    \
2146                 _ASM_UNSET_DMTGC0                                       \
2147                 ".set\tpop"                                             \
2148                 : : "Jr" (value),                                       \
2149                     "i" (sel));                                         \
2150 } while (0)
2151
2152 #define __read_ulong_gc0_register(reg, sel)                             \
2153         ((sizeof(unsigned long) == 4) ?                                 \
2154         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
2155         (unsigned long) __read_64bit_gc0_register(reg, sel))
2156
2157 #define __write_ulong_gc0_register(reg, sel, val)                       \
2158 do {                                                                    \
2159         if (sizeof(unsigned long) == 4)                                 \
2160                 __write_32bit_gc0_register(reg, sel, val);              \
2161         else                                                            \
2162                 __write_64bit_gc0_register(reg, sel, val);              \
2163 } while (0)
2164
2165 #define read_gc0_index()                __read_32bit_gc0_register($0, 0)
2166 #define write_gc0_index(val)            __write_32bit_gc0_register($0, 0, val)
2167
2168 #define read_gc0_entrylo0()             __read_ulong_gc0_register($2, 0)
2169 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register($2, 0, val)
2170
2171 #define read_gc0_entrylo1()             __read_ulong_gc0_register($3, 0)
2172 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register($3, 0, val)
2173
2174 #define read_gc0_context()              __read_ulong_gc0_register($4, 0)
2175 #define write_gc0_context(val)          __write_ulong_gc0_register($4, 0, val)
2176
2177 #define read_gc0_contextconfig()        __read_32bit_gc0_register($4, 1)
2178 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register($4, 1, val)
2179
2180 #define read_gc0_userlocal()            __read_ulong_gc0_register($4, 2)
2181 #define write_gc0_userlocal(val)        __write_ulong_gc0_register($4, 2, val)
2182
2183 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register($4, 3)
2184 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register($4, 3, val)
2185
2186 #define read_gc0_pagemask()             __read_32bit_gc0_register($5, 0)
2187 #define write_gc0_pagemask(val)         __write_32bit_gc0_register($5, 0, val)
2188
2189 #define read_gc0_pagegrain()            __read_32bit_gc0_register($5, 1)
2190 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register($5, 1, val)
2191
2192 #define read_gc0_segctl0()              __read_ulong_gc0_register($5, 2)
2193 #define write_gc0_segctl0(val)          __write_ulong_gc0_register($5, 2, val)
2194
2195 #define read_gc0_segctl1()              __read_ulong_gc0_register($5, 3)
2196 #define write_gc0_segctl1(val)          __write_ulong_gc0_register($5, 3, val)
2197
2198 #define read_gc0_segctl2()              __read_ulong_gc0_register($5, 4)
2199 #define write_gc0_segctl2(val)          __write_ulong_gc0_register($5, 4, val)
2200
2201 #define read_gc0_pwbase()               __read_ulong_gc0_register($5, 5)
2202 #define write_gc0_pwbase(val)           __write_ulong_gc0_register($5, 5, val)
2203
2204 #define read_gc0_pwfield()              __read_ulong_gc0_register($5, 6)
2205 #define write_gc0_pwfield(val)          __write_ulong_gc0_register($5, 6, val)
2206
2207 #define read_gc0_pwsize()               __read_ulong_gc0_register($5, 7)
2208 #define write_gc0_pwsize(val)           __write_ulong_gc0_register($5, 7, val)
2209
2210 #define read_gc0_wired()                __read_32bit_gc0_register($6, 0)
2211 #define write_gc0_wired(val)            __write_32bit_gc0_register($6, 0, val)
2212
2213 #define read_gc0_pwctl()                __read_32bit_gc0_register($6, 6)
2214 #define write_gc0_pwctl(val)            __write_32bit_gc0_register($6, 6, val)
2215
2216 #define read_gc0_hwrena()               __read_32bit_gc0_register($7, 0)
2217 #define write_gc0_hwrena(val)           __write_32bit_gc0_register($7, 0, val)
2218
2219 #define read_gc0_badvaddr()             __read_ulong_gc0_register($8, 0)
2220 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register($8, 0, val)
2221
2222 #define read_gc0_badinstr()             __read_32bit_gc0_register($8, 1)
2223 #define write_gc0_badinstr(val)         __write_32bit_gc0_register($8, 1, val)
2224
2225 #define read_gc0_badinstrp()            __read_32bit_gc0_register($8, 2)
2226 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register($8, 2, val)
2227
2228 #define read_gc0_count()                __read_32bit_gc0_register($9, 0)
2229
2230 #define read_gc0_entryhi()              __read_ulong_gc0_register($10, 0)
2231 #define write_gc0_entryhi(val)          __write_ulong_gc0_register($10, 0, val)
2232
2233 #define read_gc0_compare()              __read_32bit_gc0_register($11, 0)
2234 #define write_gc0_compare(val)          __write_32bit_gc0_register($11, 0, val)
2235
2236 #define read_gc0_status()               __read_32bit_gc0_register($12, 0)
2237 #define write_gc0_status(val)           __write_32bit_gc0_register($12, 0, val)
2238
2239 #define read_gc0_intctl()               __read_32bit_gc0_register($12, 1)
2240 #define write_gc0_intctl(val)           __write_32bit_gc0_register($12, 1, val)
2241
2242 #define read_gc0_cause()                __read_32bit_gc0_register($13, 0)
2243 #define write_gc0_cause(val)            __write_32bit_gc0_register($13, 0, val)
2244
2245 #define read_gc0_epc()                  __read_ulong_gc0_register($14, 0)
2246 #define write_gc0_epc(val)              __write_ulong_gc0_register($14, 0, val)
2247
2248 #define read_gc0_prid()                 __read_32bit_gc0_register($15, 0)
2249
2250 #define read_gc0_ebase()                __read_32bit_gc0_register($15, 1)
2251 #define write_gc0_ebase(val)            __write_32bit_gc0_register($15, 1, val)
2252
2253 #define read_gc0_ebase_64()             __read_64bit_gc0_register($15, 1)
2254 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register($15, 1, val)
2255
2256 #define read_gc0_config()               __read_32bit_gc0_register($16, 0)
2257 #define read_gc0_config1()              __read_32bit_gc0_register($16, 1)
2258 #define read_gc0_config2()              __read_32bit_gc0_register($16, 2)
2259 #define read_gc0_config3()              __read_32bit_gc0_register($16, 3)
2260 #define read_gc0_config4()              __read_32bit_gc0_register($16, 4)
2261 #define read_gc0_config5()              __read_32bit_gc0_register($16, 5)
2262 #define read_gc0_config6()              __read_32bit_gc0_register($16, 6)
2263 #define read_gc0_config7()              __read_32bit_gc0_register($16, 7)
2264 #define write_gc0_config(val)           __write_32bit_gc0_register($16, 0, val)
2265 #define write_gc0_config1(val)          __write_32bit_gc0_register($16, 1, val)
2266 #define write_gc0_config2(val)          __write_32bit_gc0_register($16, 2, val)
2267 #define write_gc0_config3(val)          __write_32bit_gc0_register($16, 3, val)
2268 #define write_gc0_config4(val)          __write_32bit_gc0_register($16, 4, val)
2269 #define write_gc0_config5(val)          __write_32bit_gc0_register($16, 5, val)
2270 #define write_gc0_config6(val)          __write_32bit_gc0_register($16, 6, val)
2271 #define write_gc0_config7(val)          __write_32bit_gc0_register($16, 7, val)
2272
2273 #define read_gc0_lladdr()               __read_ulong_gc0_register($17, 0)
2274 #define write_gc0_lladdr(val)           __write_ulong_gc0_register($17, 0, val)
2275
2276 #define read_gc0_watchlo0()             __read_ulong_gc0_register($18, 0)
2277 #define read_gc0_watchlo1()             __read_ulong_gc0_register($18, 1)
2278 #define read_gc0_watchlo2()             __read_ulong_gc0_register($18, 2)
2279 #define read_gc0_watchlo3()             __read_ulong_gc0_register($18, 3)
2280 #define read_gc0_watchlo4()             __read_ulong_gc0_register($18, 4)
2281 #define read_gc0_watchlo5()             __read_ulong_gc0_register($18, 5)
2282 #define read_gc0_watchlo6()             __read_ulong_gc0_register($18, 6)
2283 #define read_gc0_watchlo7()             __read_ulong_gc0_register($18, 7)
2284 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register($18, 0, val)
2285 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register($18, 1, val)
2286 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register($18, 2, val)
2287 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register($18, 3, val)
2288 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register($18, 4, val)
2289 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register($18, 5, val)
2290 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register($18, 6, val)
2291 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register($18, 7, val)
2292
2293 #define read_gc0_watchhi0()             __read_32bit_gc0_register($19, 0)
2294 #define read_gc0_watchhi1()             __read_32bit_gc0_register($19, 1)
2295 #define read_gc0_watchhi2()             __read_32bit_gc0_register($19, 2)
2296 #define read_gc0_watchhi3()             __read_32bit_gc0_register($19, 3)
2297 #define read_gc0_watchhi4()             __read_32bit_gc0_register($19, 4)
2298 #define read_gc0_watchhi5()             __read_32bit_gc0_register($19, 5)
2299 #define read_gc0_watchhi6()             __read_32bit_gc0_register($19, 6)
2300 #define read_gc0_watchhi7()             __read_32bit_gc0_register($19, 7)
2301 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register($19, 0, val)
2302 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register($19, 1, val)
2303 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register($19, 2, val)
2304 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register($19, 3, val)
2305 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register($19, 4, val)
2306 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register($19, 5, val)
2307 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register($19, 6, val)
2308 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register($19, 7, val)
2309
2310 #define read_gc0_xcontext()             __read_ulong_gc0_register($20, 0)
2311 #define write_gc0_xcontext(val)         __write_ulong_gc0_register($20, 0, val)
2312
2313 #define read_gc0_perfctrl0()            __read_32bit_gc0_register($25, 0)
2314 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register($25, 0, val)
2315 #define read_gc0_perfcntr0()            __read_32bit_gc0_register($25, 1)
2316 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register($25, 1, val)
2317 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register($25, 1)
2318 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register($25, 1, val)
2319 #define read_gc0_perfctrl1()            __read_32bit_gc0_register($25, 2)
2320 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register($25, 2, val)
2321 #define read_gc0_perfcntr1()            __read_32bit_gc0_register($25, 3)
2322 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register($25, 3, val)
2323 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register($25, 3)
2324 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register($25, 3, val)
2325 #define read_gc0_perfctrl2()            __read_32bit_gc0_register($25, 4)
2326 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register($25, 4, val)
2327 #define read_gc0_perfcntr2()            __read_32bit_gc0_register($25, 5)
2328 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register($25, 5, val)
2329 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register($25, 5)
2330 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register($25, 5, val)
2331 #define read_gc0_perfctrl3()            __read_32bit_gc0_register($25, 6)
2332 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register($25, 6, val)
2333 #define read_gc0_perfcntr3()            __read_32bit_gc0_register($25, 7)
2334 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register($25, 7, val)
2335 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register($25, 7)
2336 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register($25, 7, val)
2337
2338 #define read_gc0_errorepc()             __read_ulong_gc0_register($30, 0)
2339 #define write_gc0_errorepc(val)         __write_ulong_gc0_register($30, 0, val)
2340
2341 #define read_gc0_kscratch1()            __read_ulong_gc0_register($31, 2)
2342 #define read_gc0_kscratch2()            __read_ulong_gc0_register($31, 3)
2343 #define read_gc0_kscratch3()            __read_ulong_gc0_register($31, 4)
2344 #define read_gc0_kscratch4()            __read_ulong_gc0_register($31, 5)
2345 #define read_gc0_kscratch5()            __read_ulong_gc0_register($31, 6)
2346 #define read_gc0_kscratch6()            __read_ulong_gc0_register($31, 7)
2347 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register($31, 2, val)
2348 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register($31, 3, val)
2349 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register($31, 4, val)
2350 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register($31, 5, val)
2351 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register($31, 6, val)
2352 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register($31, 7, val)
2353
2354 /* Cavium OCTEON (cnMIPS) */
2355 #define read_gc0_cvmcount()             __read_ulong_gc0_register($9, 6)
2356 #define write_gc0_cvmcount(val)         __write_ulong_gc0_register($9, 6, val)
2357
2358 #define read_gc0_cvmctl()               __read_64bit_gc0_register($9, 7)
2359 #define write_gc0_cvmctl(val)           __write_64bit_gc0_register($9, 7, val)
2360
2361 #define read_gc0_cvmmemctl()            __read_64bit_gc0_register($11, 7)
2362 #define write_gc0_cvmmemctl(val)        __write_64bit_gc0_register($11, 7, val)
2363
2364 #define read_gc0_cvmmemctl2()           __read_64bit_gc0_register($16, 6)
2365 #define write_gc0_cvmmemctl2(val)       __write_64bit_gc0_register($16, 6, val)
2366
2367 /*
2368  * Macros to access the floating point coprocessor control registers
2369  */
2370 #define read_32bit_cp1_register(source)                                 \
2371 ({                                                                      \
2372         unsigned int __res;                                             \
2373                                                                         \
2374         __asm__ __volatile__(                                           \
2375         "       .set    push                                    \n"     \
2376         "       .set    reorder                                 \n"     \
2377         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2378         "       # like Octeon.                                  \n"     \
2379         "       .set    mips1                                   \n"     \
2380         "       .set hardfloat                                  \n"     \
2381         "       cfc1    %0,"STR(source)"                        \n"     \
2382         "       .set    pop                                     \n"     \
2383         : "=r" (__res));                                                \
2384         __res;                                                          \
2385 })
2386
2387 #define write_32bit_cp1_register(dest, val)                             \
2388 do {                                                                    \
2389         __asm__ __volatile__(                                           \
2390         "       .set    push                                    \n"     \
2391         "       .set    reorder                                 \n"     \
2392         "       .set hardfloat                                  \n"     \
2393         "       ctc1    %0,"STR(dest)"                          \n"     \
2394         "       .set    pop                                     \n"     \
2395         : : "r" (val));                                                 \
2396 } while (0)
2397
2398 #ifdef TOOLCHAIN_SUPPORTS_DSP
2399 #define rddsp(mask)                                                     \
2400 ({                                                                      \
2401         unsigned int __dspctl;                                          \
2402                                                                         \
2403         __asm__ __volatile__(                                           \
2404         "       .set push                                       \n"     \
2405         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2406         "       .set dsp                                        \n"     \
2407         "       rddsp   %0, %x1                                 \n"     \
2408         "       .set pop                                        \n"     \
2409         : "=r" (__dspctl)                                               \
2410         : "i" (mask));                                                  \
2411         __dspctl;                                                       \
2412 })
2413
2414 #define wrdsp(val, mask)                                                \
2415 do {                                                                    \
2416         __asm__ __volatile__(                                           \
2417         "       .set push                                       \n"     \
2418         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2419         "       .set dsp                                        \n"     \
2420         "       wrdsp   %0, %x1                                 \n"     \
2421         "       .set pop                                        \n"     \
2422         :                                                               \
2423         : "r" (val), "i" (mask));                                       \
2424 } while (0)
2425
2426 #define mflo0()                                                         \
2427 ({                                                                      \
2428         long mflo0;                                                     \
2429         __asm__(                                                        \
2430         "       .set push                                       \n"     \
2431         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2432         "       .set dsp                                        \n"     \
2433         "       mflo %0, $ac0                                   \n"     \
2434         "       .set pop                                        \n"     \
2435         : "=r" (mflo0));                                                \
2436         mflo0;                                                          \
2437 })
2438
2439 #define mflo1()                                                         \
2440 ({                                                                      \
2441         long mflo1;                                                     \
2442         __asm__(                                                        \
2443         "       .set push                                       \n"     \
2444         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2445         "       .set dsp                                        \n"     \
2446         "       mflo %0, $ac1                                   \n"     \
2447         "       .set pop                                        \n"     \
2448         : "=r" (mflo1));                                                \
2449         mflo1;                                                          \
2450 })
2451
2452 #define mflo2()                                                         \
2453 ({                                                                      \
2454         long mflo2;                                                     \
2455         __asm__(                                                        \
2456         "       .set push                                       \n"     \
2457         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2458         "       .set dsp                                        \n"     \
2459         "       mflo %0, $ac2                                   \n"     \
2460         "       .set pop                                        \n"     \
2461         : "=r" (mflo2));                                                \
2462         mflo2;                                                          \
2463 })
2464
2465 #define mflo3()                                                         \
2466 ({                                                                      \
2467         long mflo3;                                                     \
2468         __asm__(                                                        \
2469         "       .set push                                       \n"     \
2470         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2471         "       .set dsp                                        \n"     \
2472         "       mflo %0, $ac3                                   \n"     \
2473         "       .set pop                                        \n"     \
2474         : "=r" (mflo3));                                                \
2475         mflo3;                                                          \
2476 })
2477
2478 #define mfhi0()                                                         \
2479 ({                                                                      \
2480         long mfhi0;                                                     \
2481         __asm__(                                                        \
2482         "       .set push                                       \n"     \
2483         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2484         "       .set dsp                                        \n"     \
2485         "       mfhi %0, $ac0                                   \n"     \
2486         "       .set pop                                        \n"     \
2487         : "=r" (mfhi0));                                                \
2488         mfhi0;                                                          \
2489 })
2490
2491 #define mfhi1()                                                         \
2492 ({                                                                      \
2493         long mfhi1;                                                     \
2494         __asm__(                                                        \
2495         "       .set push                                       \n"     \
2496         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2497         "       .set dsp                                        \n"     \
2498         "       mfhi %0, $ac1                                   \n"     \
2499         "       .set pop                                        \n"     \
2500         : "=r" (mfhi1));                                                \
2501         mfhi1;                                                          \
2502 })
2503
2504 #define mfhi2()                                                         \
2505 ({                                                                      \
2506         long mfhi2;                                                     \
2507         __asm__(                                                        \
2508         "       .set push                                       \n"     \
2509         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2510         "       .set dsp                                        \n"     \
2511         "       mfhi %0, $ac2                                   \n"     \
2512         "       .set pop                                        \n"     \
2513         : "=r" (mfhi2));                                                \
2514         mfhi2;                                                          \
2515 })
2516
2517 #define mfhi3()                                                         \
2518 ({                                                                      \
2519         long mfhi3;                                                     \
2520         __asm__(                                                        \
2521         "       .set push                                       \n"     \
2522         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2523         "       .set dsp                                        \n"     \
2524         "       mfhi %0, $ac3                                   \n"     \
2525         "       .set pop                                        \n"     \
2526         : "=r" (mfhi3));                                                \
2527         mfhi3;                                                          \
2528 })
2529
2530
2531 #define mtlo0(x)                                                        \
2532 ({                                                                      \
2533         __asm__(                                                        \
2534         "       .set push                                       \n"     \
2535         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2536         "       .set dsp                                        \n"     \
2537         "       mtlo %0, $ac0                                   \n"     \
2538         "       .set pop                                        \n"     \
2539         :                                                               \
2540         : "r" (x));                                                     \
2541 })
2542
2543 #define mtlo1(x)                                                        \
2544 ({                                                                      \
2545         __asm__(                                                        \
2546         "       .set push                                       \n"     \
2547         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2548         "       .set dsp                                        \n"     \
2549         "       mtlo %0, $ac1                                   \n"     \
2550         "       .set pop                                        \n"     \
2551         :                                                               \
2552         : "r" (x));                                                     \
2553 })
2554
2555 #define mtlo2(x)                                                        \
2556 ({                                                                      \
2557         __asm__(                                                        \
2558         "       .set push                                       \n"     \
2559         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2560         "       .set dsp                                        \n"     \
2561         "       mtlo %0, $ac2                                   \n"     \
2562         "       .set pop                                        \n"     \
2563         :                                                               \
2564         : "r" (x));                                                     \
2565 })
2566
2567 #define mtlo3(x)                                                        \
2568 ({                                                                      \
2569         __asm__(                                                        \
2570         "       .set push                                       \n"     \
2571         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2572         "       .set dsp                                        \n"     \
2573         "       mtlo %0, $ac3                                   \n"     \
2574         "       .set pop                                        \n"     \
2575         :                                                               \
2576         : "r" (x));                                                     \
2577 })
2578
2579 #define mthi0(x)                                                        \
2580 ({                                                                      \
2581         __asm__(                                                        \
2582         "       .set push                                       \n"     \
2583         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2584         "       .set dsp                                        \n"     \
2585         "       mthi %0, $ac0                                   \n"     \
2586         "       .set pop                                        \n"     \
2587         :                                                               \
2588         : "r" (x));                                                     \
2589 })
2590
2591 #define mthi1(x)                                                        \
2592 ({                                                                      \
2593         __asm__(                                                        \
2594         "       .set push                                       \n"     \
2595         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2596         "       .set dsp                                        \n"     \
2597         "       mthi %0, $ac1                                   \n"     \
2598         "       .set pop                                        \n"     \
2599         :                                                               \
2600         : "r" (x));                                                     \
2601 })
2602
2603 #define mthi2(x)                                                        \
2604 ({                                                                      \
2605         __asm__(                                                        \
2606         "       .set push                                       \n"     \
2607         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2608         "       .set dsp                                        \n"     \
2609         "       mthi %0, $ac2                                   \n"     \
2610         "       .set pop                                        \n"     \
2611         :                                                               \
2612         : "r" (x));                                                     \
2613 })
2614
2615 #define mthi3(x)                                                        \
2616 ({                                                                      \
2617         __asm__(                                                        \
2618         "       .set push                                       \n"     \
2619         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2620         "       .set dsp                                        \n"     \
2621         "       mthi %0, $ac3                                   \n"     \
2622         "       .set pop                                        \n"     \
2623         :                                                               \
2624         : "r" (x));                                                     \
2625 })
2626
2627 #else
2628
2629 #define rddsp(mask)                                                     \
2630 ({                                                                      \
2631         unsigned int __res;                                             \
2632                                                                         \
2633         __asm__ __volatile__(                                           \
2634         "       .set    push                                    \n"     \
2635         "       .set    noat                                    \n"     \
2636         "       # rddsp $1, %x1                                 \n"     \
2637         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2638         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2639         "       move    %0, $1                                  \n"     \
2640         "       .set    pop                                     \n"     \
2641         : "=r" (__res)                                                  \
2642         : "i" (mask));                                                  \
2643         __res;                                                          \
2644 })
2645
2646 #define wrdsp(val, mask)                                                \
2647 do {                                                                    \
2648         __asm__ __volatile__(                                           \
2649         "       .set    push                                    \n"     \
2650         "       .set    noat                                    \n"     \
2651         "       move    $1, %0                                  \n"     \
2652         "       # wrdsp $1, %x1                                 \n"     \
2653         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2654         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2655         "       .set    pop                                     \n"     \
2656         :                                                               \
2657         : "r" (val), "i" (mask));                                       \
2658 } while (0)
2659
2660 #define _dsp_mfxxx(ins)                                                 \
2661 ({                                                                      \
2662         unsigned long __treg;                                           \
2663                                                                         \
2664         __asm__ __volatile__(                                           \
2665         "       .set    push                                    \n"     \
2666         "       .set    noat                                    \n"     \
2667         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2668         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2669         "       move    %0, $1                                  \n"     \
2670         "       .set    pop                                     \n"     \
2671         : "=r" (__treg)                                                 \
2672         : "i" (ins));                                                   \
2673         __treg;                                                         \
2674 })
2675
2676 #define _dsp_mtxxx(val, ins)                                            \
2677 do {                                                                    \
2678         __asm__ __volatile__(                                           \
2679         "       .set    push                                    \n"     \
2680         "       .set    noat                                    \n"     \
2681         "       move    $1, %0                                  \n"     \
2682         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2683         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2684         "       .set    pop                                     \n"     \
2685         :                                                               \
2686         : "r" (val), "i" (ins));                                        \
2687 } while (0)
2688
2689 #ifdef CONFIG_CPU_MICROMIPS
2690
2691 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2692 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2693
2694 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2695 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2696
2697 #else  /* !CONFIG_CPU_MICROMIPS */
2698
2699 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2700 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2701
2702 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2703 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2704
2705 #endif /* CONFIG_CPU_MICROMIPS */
2706
2707 #define mflo0() _dsp_mflo(0)
2708 #define mflo1() _dsp_mflo(1)
2709 #define mflo2() _dsp_mflo(2)
2710 #define mflo3() _dsp_mflo(3)
2711
2712 #define mfhi0() _dsp_mfhi(0)
2713 #define mfhi1() _dsp_mfhi(1)
2714 #define mfhi2() _dsp_mfhi(2)
2715 #define mfhi3() _dsp_mfhi(3)
2716
2717 #define mtlo0(x) _dsp_mtlo(x, 0)
2718 #define mtlo1(x) _dsp_mtlo(x, 1)
2719 #define mtlo2(x) _dsp_mtlo(x, 2)
2720 #define mtlo3(x) _dsp_mtlo(x, 3)
2721
2722 #define mthi0(x) _dsp_mthi(x, 0)
2723 #define mthi1(x) _dsp_mthi(x, 1)
2724 #define mthi2(x) _dsp_mthi(x, 2)
2725 #define mthi3(x) _dsp_mthi(x, 3)
2726
2727 #endif
2728
2729 /*
2730  * TLB operations.
2731  *
2732  * It is responsibility of the caller to take care of any TLB hazards.
2733  */
2734 static inline void tlb_probe(void)
2735 {
2736         __asm__ __volatile__(
2737                 ".set noreorder\n\t"
2738                 "tlbp\n\t"
2739                 ".set reorder");
2740 }
2741
2742 static inline void tlb_read(void)
2743 {
2744 #ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2745         int res = 0;
2746
2747         __asm__ __volatile__(
2748         "       .set    push                                    \n"
2749         "       .set    noreorder                               \n"
2750         "       .set    noat                                    \n"
2751         "       .set    mips32r2                                \n"
2752         "       .word   0x41610001              # dvpe $1       \n"
2753         "       move    %0, $1                                  \n"
2754         "       ehb                                             \n"
2755         "       .set    pop                                     \n"
2756         : "=r" (res));
2757
2758         instruction_hazard();
2759 #endif
2760
2761         __asm__ __volatile__(
2762                 ".set noreorder\n\t"
2763                 "tlbr\n\t"
2764                 ".set reorder");
2765
2766 #ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2767         if ((res & _ULCAST_(1)))
2768                 __asm__ __volatile__(
2769                 "       .set    push                            \n"
2770                 "       .set    noreorder                       \n"
2771                 "       .set    noat                            \n"
2772                 "       .set    mips32r2                        \n"
2773                 "       .word   0x41600021      # evpe          \n"
2774                 "       ehb                                     \n"
2775                 "       .set    pop                             \n");
2776 #endif
2777 }
2778
2779 static inline void tlb_write_indexed(void)
2780 {
2781         __asm__ __volatile__(
2782                 ".set noreorder\n\t"
2783                 "tlbwi\n\t"
2784                 ".set reorder");
2785 }
2786
2787 static inline void tlb_write_random(void)
2788 {
2789         __asm__ __volatile__(
2790                 ".set noreorder\n\t"
2791                 "tlbwr\n\t"
2792                 ".set reorder");
2793 }
2794
2795 /*
2796  * Guest TLB operations.
2797  *
2798  * It is responsibility of the caller to take care of any TLB hazards.
2799  */
2800 static inline void guest_tlb_probe(void)
2801 {
2802         __asm__ __volatile__(
2803                 ".set push\n\t"
2804                 ".set noreorder\n\t"
2805                 __tlbgp()
2806                 ".set pop");
2807 }
2808
2809 static inline void guest_tlb_read(void)
2810 {
2811         __asm__ __volatile__(
2812                 ".set push\n\t"
2813                 ".set noreorder\n\t"
2814                 __tlbgr()
2815                 ".set pop");
2816 }
2817
2818 static inline void guest_tlb_write_indexed(void)
2819 {
2820         __asm__ __volatile__(
2821                 ".set push\n\t"
2822                 ".set noreorder\n\t"
2823                 __tlbgwi()
2824                 ".set pop");
2825 }
2826
2827 static inline void guest_tlb_write_random(void)
2828 {
2829         __asm__ __volatile__(
2830                 ".set push\n\t"
2831                 ".set noreorder\n\t"
2832                 __tlbgwr()
2833                 ".set pop");
2834 }
2835
2836 /*
2837  * Guest TLB Invalidate Flush
2838  */
2839 static inline void guest_tlbinvf(void)
2840 {
2841         __asm__ __volatile__(
2842                 ".set push\n\t"
2843                 ".set noreorder\n\t"
2844                 __tlbginvf()
2845                 ".set pop");
2846 }
2847
2848 /*
2849  * Manipulate bits in a register.
2850  */
2851 #define __BUILD_SET_COMMON(name)                                \
2852 static inline unsigned int                                      \
2853 set_##name(unsigned int set)                                    \
2854 {                                                               \
2855         unsigned int res, new;                                  \
2856                                                                 \
2857         res = read_##name();                                    \
2858         new = res | set;                                        \
2859         write_##name(new);                                      \
2860                                                                 \
2861         return res;                                             \
2862 }                                                               \
2863                                                                 \
2864 static inline unsigned int                                      \
2865 clear_##name(unsigned int clear)                                \
2866 {                                                               \
2867         unsigned int res, new;                                  \
2868                                                                 \
2869         res = read_##name();                                    \
2870         new = res & ~clear;                                     \
2871         write_##name(new);                                      \
2872                                                                 \
2873         return res;                                             \
2874 }                                                               \
2875                                                                 \
2876 static inline unsigned int                                      \
2877 change_##name(unsigned int change, unsigned int val)            \
2878 {                                                               \
2879         unsigned int res, new;                                  \
2880                                                                 \
2881         res = read_##name();                                    \
2882         new = res & ~change;                                    \
2883         new |= (val & change);                                  \
2884         write_##name(new);                                      \
2885                                                                 \
2886         return res;                                             \
2887 }
2888
2889 /*
2890  * Manipulate bits in a c0 register.
2891  */
2892 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2893
2894 __BUILD_SET_C0(status)
2895 __BUILD_SET_C0(cause)
2896 __BUILD_SET_C0(config)
2897 __BUILD_SET_C0(config5)
2898 __BUILD_SET_C0(config6)
2899 __BUILD_SET_C0(config7)
2900 __BUILD_SET_C0(diag)
2901 __BUILD_SET_C0(intcontrol)
2902 __BUILD_SET_C0(intctl)
2903 __BUILD_SET_C0(srsmap)
2904 __BUILD_SET_C0(pagegrain)
2905 __BUILD_SET_C0(guestctl0)
2906 __BUILD_SET_C0(guestctl0ext)
2907 __BUILD_SET_C0(guestctl1)
2908 __BUILD_SET_C0(guestctl2)
2909 __BUILD_SET_C0(guestctl3)
2910 __BUILD_SET_C0(brcm_config_0)
2911 __BUILD_SET_C0(brcm_bus_pll)
2912 __BUILD_SET_C0(brcm_reset)
2913 __BUILD_SET_C0(brcm_cmt_intr)
2914 __BUILD_SET_C0(brcm_cmt_ctrl)
2915 __BUILD_SET_C0(brcm_config)
2916 __BUILD_SET_C0(brcm_mode)
2917
2918 /*
2919  * Manipulate bits in a guest c0 register.
2920  */
2921 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2922
2923 __BUILD_SET_GC0(wired)
2924 __BUILD_SET_GC0(status)
2925 __BUILD_SET_GC0(cause)
2926 __BUILD_SET_GC0(ebase)
2927 __BUILD_SET_GC0(config1)
2928
2929 /*
2930  * Return low 10 bits of ebase.
2931  * Note that under KVM (MIPSVZ) this returns vcpu id.
2932  */
2933 static inline unsigned int get_ebase_cpunum(void)
2934 {
2935         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2936 }
2937
2938 #endif /* !__ASSEMBLY__ */
2939
2940 #endif /* _ASM_MIPSREGS_H */