1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Ralink SoC register definitions
5 * Copyright (C) 2013 John Crispin <john@phrozen.org>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 #ifndef _RALINK_REGS_H_
11 #define _RALINK_REGS_H_
15 enum ralink_soc_type {
30 extern enum ralink_soc_type ralink_soc;
32 extern __iomem void *rt_sysc_membase;
33 extern __iomem void *rt_memc_membase;
35 static inline void rt_sysc_w32(u32 val, unsigned reg)
37 __raw_writel(val, rt_sysc_membase + reg);
40 static inline u32 rt_sysc_r32(unsigned reg)
42 return __raw_readl(rt_sysc_membase + reg);
45 static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
47 u32 val = rt_sysc_r32(reg) & ~clr;
49 __raw_writel(val | set, rt_sysc_membase + reg);
52 static inline void rt_memc_w32(u32 val, unsigned reg)
54 __raw_writel(val, rt_memc_membase + reg);
57 static inline u32 rt_memc_r32(unsigned reg)
59 return __raw_readl(rt_memc_membase + reg);
62 #endif /* _RALINK_REGS_H_ */