1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Parts of this file are based on Ralink's 2.6.21 BSP
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
11 #ifndef _MT7620_REGS_H_
12 #define _MT7620_REGS_H_
14 #define MT7620_SYSC_BASE 0x10000000
16 #define SYSC_REG_CHIP_NAME0 0x00
17 #define SYSC_REG_CHIP_NAME1 0x04
18 #define SYSC_REG_EFUSE_CFG 0x08
19 #define SYSC_REG_CHIP_REV 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
22 #define SYSC_REG_CLKCFG0 0x2c
23 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c
24 #define SYSC_REG_CPLL_CONFIG0 0x54
25 #define SYSC_REG_CPLL_CONFIG1 0x58
27 #define MT7620_CHIP_NAME0 0x3637544d
28 #define MT7620_CHIP_NAME1 0x20203032
29 #define MT7628_CHIP_NAME1 0x20203832
31 #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
33 #define CHIP_REV_PKG_MASK 0x1
34 #define CHIP_REV_PKG_SHIFT 16
35 #define CHIP_REV_VER_MASK 0xf
36 #define CHIP_REV_VER_SHIFT 8
37 #define CHIP_REV_ECO_MASK 0xf
39 #define CLKCFG0_PERI_CLK_SEL BIT(4)
41 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
42 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
43 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
44 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
45 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
46 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
47 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
48 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
49 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
50 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
51 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
52 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
53 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
54 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
55 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
57 #define CPLL_CFG0_SW_CFG BIT(31)
58 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
59 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
60 #define CPLL_CFG0_LC_CURFCK BIT(15)
61 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
62 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
63 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
65 #define CPLL_CFG1_CPU_AUX1 BIT(25)
66 #define CPLL_CFG1_CPU_AUX0 BIT(24)
68 #define SYSCFG0_DRAM_TYPE_MASK 0x3
69 #define SYSCFG0_DRAM_TYPE_SHIFT 4
70 #define SYSCFG0_DRAM_TYPE_SDRAM 0
71 #define SYSCFG0_DRAM_TYPE_DDR1 1
72 #define SYSCFG0_DRAM_TYPE_DDR2 2
73 #define SYSCFG0_DRAM_TYPE_UNKNOWN 3
75 #define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
76 #define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
78 #define MT7620_DRAM_BASE 0x0
79 #define MT7620_SDRAM_SIZE_MIN 2
80 #define MT7620_SDRAM_SIZE_MAX 64
81 #define MT7620_DDR1_SIZE_MIN 32
82 #define MT7620_DDR1_SIZE_MAX 128
83 #define MT7620_DDR2_SIZE_MIN 32
84 #define MT7620_DDR2_SIZE_MAX 256
86 extern enum ralink_soc_type ralink_soc;
88 static inline int is_mt76x8(void)
90 return ralink_soc == MT762X_SOC_MT7628AN ||
91 ralink_soc == MT762X_SOC_MT7688;
94 static inline int mt7620_get_eco(void)
96 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;