2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
13 #include <linux/futex.h>
14 #include <linux/uaccess.h>
15 #include <asm/asm-eva.h>
16 #include <asm/barrier.h>
17 #include <asm/compiler.h>
18 #include <asm/errno.h>
21 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
23 if (cpu_has_llsc && R10000_LLSC_WAR) { \
24 __asm__ __volatile__( \
28 " .set arch=r4000 \n" \
29 "1: ll %1, %4 # __futex_atomic_op \n" \
32 " .set arch=r4000 \n" \
39 " .section .fixup,\"ax\" \n" \
43 " .section __ex_table,\"a\" \n" \
44 " "__UA_ADDR "\t1b, 4b \n" \
45 " "__UA_ADDR "\t2b, 4b \n" \
47 : "=r" (ret), "=&r" (oldval), \
48 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
49 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
52 } else if (cpu_has_llsc) { \
54 __asm__ __volatile__( \
58 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
59 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
62 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
63 "2: "user_sc("$1", "%2")" \n" \
69 " .section .fixup,\"ax\" \n" \
73 " .section __ex_table,\"a\" \n" \
74 " "__UA_ADDR "\t1b, 4b \n" \
75 " "__UA_ADDR "\t2b, 4b \n" \
77 : "=r" (ret), "=&r" (oldval), \
78 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
79 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
87 arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
95 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
99 __futex_atomic_op("addu $1, %1, %z5",
100 ret, oldval, uaddr, oparg);
103 __futex_atomic_op("or $1, %1, %z5",
104 ret, oldval, uaddr, oparg);
107 __futex_atomic_op("and $1, %1, %z5",
108 ret, oldval, uaddr, ~oparg);
111 __futex_atomic_op("xor $1, %1, %z5",
112 ret, oldval, uaddr, oparg);
127 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
128 u32 oldval, u32 newval)
133 if (!access_ok(uaddr, sizeof(u32)))
136 if (cpu_has_llsc && R10000_LLSC_WAR) {
137 __asm__ __volatile__(
138 "# futex_atomic_cmpxchg_inatomic \n"
142 " .set arch=r4000 \n"
144 " bne %1, %z4, 3f \n"
147 " .set arch=r4000 \n"
154 " .section .fixup,\"ax\" \n"
158 " .section __ex_table,\"a\" \n"
159 " "__UA_ADDR "\t1b, 4b \n"
160 " "__UA_ADDR "\t2b, 4b \n"
162 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
163 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
166 } else if (cpu_has_llsc) {
168 __asm__ __volatile__(
169 "# futex_atomic_cmpxchg_inatomic \n"
173 " .set "MIPS_ISA_ARCH_LEVEL" \n"
174 "1: "user_ll("%1", "%3")" \n"
175 " bne %1, %z4, 3f \n"
178 " .set "MIPS_ISA_ARCH_LEVEL" \n"
179 "2: "user_sc("$1", "%2")" \n"
185 " .section .fixup,\"ax\" \n"
189 " .section __ex_table,\"a\" \n"
190 " "__UA_ADDR "\t1b, 4b \n"
191 " "__UA_ADDR "\t2b, 4b \n"
193 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
194 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
206 #endif /* _ASM_FUTEX_H */