2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
13 #include <linux/sched.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/ptrace.h>
16 #include <linux/thread_info.h>
17 #include <linux/bitops.h>
19 #include <asm/mipsregs.h>
21 #include <asm/cpu-features.h>
22 #include <asm/fpu_emulator.h>
23 #include <asm/hazards.h>
24 #include <asm/ptrace.h>
25 #include <asm/processor.h>
26 #include <asm/current.h>
29 #ifdef CONFIG_MIPS_MT_FPAFF
30 #include <asm/mips_mt.h>
36 extern void _init_fpu(unsigned int);
37 extern void _save_fp(struct task_struct *);
38 extern void _restore_fp(struct task_struct *);
41 * This enum specifies a mode in which we want the FPU to operate, for cores
42 * which implement the Status.FR bit. Note that the bottom bit of the value
43 * purposefully matches the desired value of the Status.FR bit.
46 FPU_32BIT = 0, /* FR = 0 */
47 FPU_64BIT, /* FR = 1, FRE = 0 */
49 FPU_HYBRID, /* FR = 1, FRE = 1 */
51 #define FPU_FR_MASK 0x1
54 #define __disable_fpu() \
56 clear_c0_status(ST0_CU1); \
57 disable_fpu_hazard(); \
60 static inline int __enable_fpu(enum fpu_mode mode)
66 /* just enable the FPU in its current mode */
67 set_c0_status(ST0_CU1);
76 set_c0_config5(MIPS_CONF5_FRE);
80 #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
81 || defined(CONFIG_64BIT))
82 /* we only have a 32-bit FPU */
89 clear_c0_config5(MIPS_CONF5_FRE);
92 /* set CU1 & change FR appropriately */
93 fr = (int)mode & FPU_FR_MASK;
94 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
97 /* check FR has the desired value */
98 if (!!(read_c0_status() & ST0_FR) == !!fr)
101 /* unsupported FR value */
112 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
114 static inline int __is_fpu_owner(void)
116 return test_thread_flag(TIF_USEDFPU);
119 static inline int is_fpu_owner(void)
121 return cpu_has_fpu && __is_fpu_owner();
124 static inline int __own_fpu(void)
129 if (test_thread_flag(TIF_HYBRID_FPREGS))
132 mode = !test_thread_flag(TIF_32BIT_FPREGS);
134 ret = __enable_fpu(mode);
138 KSTK_STATUS(current) |= ST0_CU1;
139 if (mode == FPU_64BIT || mode == FPU_HYBRID)
140 KSTK_STATUS(current) |= ST0_FR;
141 else /* mode == FPU_32BIT */
142 KSTK_STATUS(current) &= ~ST0_FR;
144 set_thread_flag(TIF_USEDFPU);
148 static inline int own_fpu_inatomic(int restore)
152 if (cpu_has_fpu && !__is_fpu_owner()) {
155 _restore_fp(current);
160 static inline int own_fpu(int restore)
165 ret = own_fpu_inatomic(restore);
170 static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
172 if (is_msa_enabled()) {
175 tsk->thread.fpu.fcr31 =
176 read_32bit_cp1_register(CP1_STATUS);
179 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
181 } else if (is_fpu_owner()) {
186 /* FPU should not have been left enabled with no owner */
187 WARN(read_c0_status() & ST0_CU1,
188 "Orphaned FPU left enabled");
190 KSTK_STATUS(tsk) &= ~ST0_CU1;
191 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
194 static inline void lose_fpu(int save)
197 lose_fpu_inatomic(save, current);
201 static inline int init_fpu(void)
203 unsigned int fcr31 = current->thread.fpu.fcr31;
207 unsigned int config5;
220 * Ensure FRE is clear whilst running _init_fpu, since
221 * single precision FP instructions are used. If FRE
222 * was set then we'll just end up initialising all 32
225 config5 = clear_c0_config5(MIPS_CONF5_FRE);
231 write_c0_config5(config5);
234 fpu_emulator_init_fpu();
239 static inline void save_fp(struct task_struct *tsk)
245 static inline void restore_fp(struct task_struct *tsk)
251 static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
253 if (tsk == current) {
260 return tsk->thread.fpu.fpr;
263 #endif /* _ASM_FPU_H */