2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
13 #include <asm/cpu-info.h>
14 #include <asm/isa-rev.h>
15 #include <cpu-feature-overrides.h>
18 * SMP assumption: Options of CPU 0 are a superset of all processors.
19 * This is true for all known MIPS systems.
22 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
25 #define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB)
27 #ifndef cpu_has_tlbinv
28 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
30 #ifndef cpu_has_segments
31 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
34 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
37 #define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
40 #define cpu_has_ldpte (cpu_data[0].options & MIPS_CPU_LDPTE)
42 #ifndef cpu_has_rixiex
43 #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
46 #define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
48 #ifndef cpu_has_rw_llb
49 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
53 * For the moment we don't consider R6000 and R8000 so we can assume that
54 * anything that doesn't support R4000-style exceptions and interrupts is
55 * R3000-like. Users should still treat these two macro definitions as
59 #define cpu_has_3kex (!cpu_has_4kex)
62 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
64 #ifndef cpu_has_3k_cache
65 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
67 #define cpu_has_6k_cache 0
68 #define cpu_has_8k_cache 0
69 #ifndef cpu_has_4k_cache
70 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
72 #ifndef cpu_has_tx39_cache
73 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
75 #ifndef cpu_has_octeon_cache
76 #define cpu_has_octeon_cache 0
78 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
80 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
81 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
83 #define raw_cpu_has_fpu cpu_has_fpu
86 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
88 #ifndef cpu_has_counter
89 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
92 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
95 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
98 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
100 #ifndef cpu_has_cache_cdex_p
101 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
103 #ifndef cpu_has_cache_cdex_s
104 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
106 #ifndef cpu_has_prefetch
107 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
109 #ifndef cpu_has_mcheck
110 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
112 #ifndef cpu_has_ejtag
113 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
116 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
118 #ifndef cpu_has_bp_ghist
119 #define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
121 #ifndef kernel_uses_llsc
122 #define kernel_uses_llsc cpu_has_llsc
124 #ifndef cpu_has_guestctl0ext
125 #define cpu_has_guestctl0ext (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT)
127 #ifndef cpu_has_guestctl1
128 #define cpu_has_guestctl1 (cpu_data[0].options & MIPS_CPU_GUESTCTL1)
130 #ifndef cpu_has_guestctl2
131 #define cpu_has_guestctl2 (cpu_data[0].options & MIPS_CPU_GUESTCTL2)
133 #ifndef cpu_has_guestid
134 #define cpu_has_guestid (cpu_data[0].options & MIPS_CPU_GUESTID)
137 #define cpu_has_drg (cpu_data[0].options & MIPS_CPU_DRG)
139 #ifndef cpu_has_mips16
140 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
142 #ifndef cpu_has_mips16e2
143 #define cpu_has_mips16e2 (cpu_data[0].ases & MIPS_ASE_MIPS16E2)
146 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
148 #ifndef cpu_has_mips3d
149 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
151 #ifndef cpu_has_smartmips
152 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
156 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
159 #ifndef cpu_has_mmips
160 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
161 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
163 # define cpu_has_mmips 0
168 #define cpu_has_lpa (cpu_data[0].options & MIPS_CPU_LPA)
171 #define cpu_has_mvh (cpu_data[0].options & MIPS_CPU_MVH)
174 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh)
176 #ifndef cpu_has_vtag_icache
177 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
179 #ifndef cpu_has_dc_aliases
180 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
182 #ifndef cpu_has_ic_fills_f_dc
183 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
185 #ifndef cpu_has_pindexed_dcache
186 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
188 #ifndef cpu_has_local_ebase
189 #define cpu_has_local_ebase 1
193 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
194 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
195 * don't. For maintaining I-cache coherency this means we need to flush the
196 * D-cache all the way back to whever the I-cache does refills from, so the
197 * I-cache has a chance to see the new data at all. Then we have to flush the
199 * Note we may have been rescheduled and may no longer be running on the CPU
200 * that did the store so we can't optimize this into only doing the flush on
203 #ifndef cpu_icache_snoops_remote_store
205 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
207 #define cpu_icache_snoops_remote_store 1
211 /* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
212 #if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
213 (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
214 (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
215 (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
216 (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
217 (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
218 #define CPU_NO_EFFICIENT_FFS 1
221 #ifndef cpu_has_mips_1
222 # define cpu_has_mips_1 (!cpu_has_mips_r6)
224 #ifndef cpu_has_mips_2
225 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
227 #ifndef cpu_has_mips_3
228 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
230 #ifndef cpu_has_mips_4
231 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
233 #ifndef cpu_has_mips_5
234 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
236 #ifndef cpu_has_mips32r1
237 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
239 #ifndef cpu_has_mips32r2
240 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
242 #ifndef cpu_has_mips32r6
243 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
245 #ifndef cpu_has_mips64r1
246 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
248 #ifndef cpu_has_mips64r2
249 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
251 #ifndef cpu_has_mips64r6
252 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
258 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
259 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
260 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
262 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
263 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
264 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
265 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
267 #define cpu_has_mips_3_4_5_64_r2_r6 \
268 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
269 #define cpu_has_mips_4_5_64_r2_r6 \
270 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
271 cpu_has_mips_r2 | cpu_has_mips_r6)
273 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
274 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
275 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
276 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
277 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
278 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
279 cpu_has_mips32r6 | cpu_has_mips64r1 | \
280 cpu_has_mips64r2 | cpu_has_mips64r6)
282 /* MIPSR2 and MIPSR6 have a lot of similarities */
283 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
286 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
288 * Returns non-zero value if the current processor implementation requires
289 * an IHB instruction to deal with an instruction hazard as per MIPS R2
290 * architecture specification, zero otherwise.
292 #ifndef cpu_has_mips_r2_exec_hazard
293 #define cpu_has_mips_r2_exec_hazard \
297 switch (current_cpu_type()) { \
304 case CPU_QEMU_GENERIC: \
305 case CPU_CAVIUM_OCTEON: \
306 case CPU_CAVIUM_OCTEON_PLUS: \
307 case CPU_CAVIUM_OCTEON2: \
308 case CPU_CAVIUM_OCTEON3: \
321 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
322 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
323 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
324 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
326 #ifndef cpu_has_clo_clz
327 #define cpu_has_clo_clz cpu_has_mips_r
331 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
332 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
333 * This indicates the availability of WSBH and in case of 64 bit CPUs also
337 #define cpu_has_wsbh cpu_has_mips_r2
341 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
345 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
349 #define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3)
352 #ifndef cpu_has_mipsmt
353 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
357 #define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP)
360 #ifndef cpu_has_userlocal
361 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
365 # ifndef cpu_has_nofpuex
366 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
368 # ifndef cpu_has_64bits
369 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
371 # ifndef cpu_has_64bit_zero_reg
372 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
374 # ifndef cpu_has_64bit_gp_regs
375 # define cpu_has_64bit_gp_regs 0
377 # ifndef cpu_has_64bit_addresses
378 # define cpu_has_64bit_addresses 0
381 # define cpu_vmbits 31
386 # ifndef cpu_has_nofpuex
387 # define cpu_has_nofpuex 0
389 # ifndef cpu_has_64bits
390 # define cpu_has_64bits 1
392 # ifndef cpu_has_64bit_zero_reg
393 # define cpu_has_64bit_zero_reg 1
395 # ifndef cpu_has_64bit_gp_regs
396 # define cpu_has_64bit_gp_regs 1
398 # ifndef cpu_has_64bit_addresses
399 # define cpu_has_64bit_addresses 1
402 # define cpu_vmbits cpu_data[0].vmbits
403 # define __NEED_VMBITS_PROBE
407 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
408 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
409 #elif !defined(cpu_has_vint)
410 # define cpu_has_vint 0
413 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
414 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
415 #elif !defined(cpu_has_veic)
416 # define cpu_has_veic 0
419 #ifndef cpu_has_inclusive_pcaches
420 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
423 #ifndef cpu_dcache_line_size
424 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
426 #ifndef cpu_icache_line_size
427 #define cpu_icache_line_size() cpu_data[0].icache.linesz
429 #ifndef cpu_scache_line_size
430 #define cpu_scache_line_size() cpu_data[0].scache.linesz
432 #ifndef cpu_tcache_line_size
433 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz
436 #ifndef cpu_hwrena_impl_bits
437 #define cpu_hwrena_impl_bits 0
440 #ifndef cpu_has_perf_cntr_intr_bit
441 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
445 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
448 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
449 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
450 #elif !defined(cpu_has_msa)
451 # define cpu_has_msa 0
455 # define cpu_has_ufr (cpu_data[0].options & MIPS_CPU_UFR)
459 # define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
463 # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
466 #ifndef cpu_has_small_pages
467 # define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP)
470 #ifndef cpu_has_nan_legacy
471 #define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY)
473 #ifndef cpu_has_nan_2008
474 #define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008)
477 #ifndef cpu_has_ebase_wg
478 # define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG)
481 #ifndef cpu_has_badinstr
482 # define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR)
485 #ifndef cpu_has_badinstrp
486 # define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP)
489 #ifndef cpu_has_contextconfig
490 # define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC)
494 # define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
497 #if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6)
499 * Some systems share FTLB RAMs between threads within a core (siblings in
500 * kernel parlance). This means that FTLB entries may become invalid at almost
501 * any point when an entry is evicted due to a sibling thread writing an entry
502 * to the shared FTLB RAM.
504 * This is only relevant to SMP systems, and the only systems that exhibit this
505 * property implement MIPSr6 or higher so we constrain support for this to
506 * kernels that will run on such systems.
508 # ifndef cpu_has_shared_ftlb_ram
509 # define cpu_has_shared_ftlb_ram \
510 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_RAM)
514 * Some systems take this a step further & share FTLB entries between siblings.
515 * This is implemented as TLB writes happening as usual, but if an entry
516 * written by a sibling exists in the shared FTLB for a translation which would
517 * otherwise cause a TLB refill exception then the CPU will use the entry
518 * written by its sibling rather than triggering a refill & writing a matching
519 * TLB entry for itself.
521 * This is naturally only valid if a TLB entry is known to be suitable for use
522 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
523 * rather than ASIDs or when a TLB entry is marked global.
525 # ifndef cpu_has_shared_ftlb_entries
526 # define cpu_has_shared_ftlb_entries \
527 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
529 #endif /* SMP && MIPS_ISA_REV >= 6 */
531 #ifndef cpu_has_shared_ftlb_ram
532 # define cpu_has_shared_ftlb_ram 0
534 #ifndef cpu_has_shared_ftlb_entries
535 # define cpu_has_shared_ftlb_entries 0
541 #ifndef cpu_guest_has_conf1
542 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1))
544 #ifndef cpu_guest_has_conf2
545 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2))
547 #ifndef cpu_guest_has_conf3
548 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3))
550 #ifndef cpu_guest_has_conf4
551 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4))
553 #ifndef cpu_guest_has_conf5
554 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5))
556 #ifndef cpu_guest_has_conf6
557 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6))
559 #ifndef cpu_guest_has_conf7
560 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7))
562 #ifndef cpu_guest_has_fpu
563 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU)
565 #ifndef cpu_guest_has_watch
566 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH)
568 #ifndef cpu_guest_has_contextconfig
569 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
571 #ifndef cpu_guest_has_segments
572 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
574 #ifndef cpu_guest_has_badinstr
575 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
577 #ifndef cpu_guest_has_badinstrp
578 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
580 #ifndef cpu_guest_has_htw
581 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW)
583 #ifndef cpu_guest_has_mvh
584 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH)
586 #ifndef cpu_guest_has_msa
587 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA)
589 #ifndef cpu_guest_has_kscr
590 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n)))
592 #ifndef cpu_guest_has_rw_llb
593 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
595 #ifndef cpu_guest_has_perf
596 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF)
598 #ifndef cpu_guest_has_maar
599 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR)
601 #ifndef cpu_guest_has_userlocal
602 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI)
606 * Guest dynamic capabilities
608 #ifndef cpu_guest_has_dyn_fpu
609 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
611 #ifndef cpu_guest_has_dyn_watch
612 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
614 #ifndef cpu_guest_has_dyn_contextconfig
615 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
617 #ifndef cpu_guest_has_dyn_perf
618 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
620 #ifndef cpu_guest_has_dyn_msa
621 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
623 #ifndef cpu_guest_has_dyn_maar
624 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
627 #endif /* __ASM_CPU_FEATURES_H */