2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Ralf Baechle
8 #ifndef _ASM_ASMMACRO_H
9 #define _ASM_ASMMACRO_H
11 #include <asm/hazards.h>
12 #include <asm/asm-offsets.h>
16 #include <asm/asmmacro-32.h>
19 #include <asm/asmmacro-64.h>
22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
26 * Helper macros for generating raw instruction encodings.
28 #ifdef CONFIG_CPU_MICROMIPS
29 .macro insn32_if_mm enc
32 .hword ((\enc) & 0xffff)
35 .macro insn_if_mips enc
38 .macro insn32_if_mm enc
41 .macro insn_if_mips enc
47 #ifdef CONFIG_CPU_HAS_DIEI
48 .macro local_irq_enable
53 .macro local_irq_disable
57 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
58 .macro local_irq_enable reg=t0
65 .macro local_irq_disable reg=t0
66 #ifdef CONFIG_PREEMPTION
67 lw \reg, TI_PRE_COUNT($28)
69 sw \reg, TI_PRE_COUNT($28)
76 #ifdef CONFIG_PREEMPTION
77 lw \reg, TI_PRE_COUNT($28)
79 sw \reg, TI_PRE_COUNT($28)
82 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
84 .macro fpu_save_16even thread tmp=t0
88 sdc1 $f0, THREAD_FPR0(\thread)
89 sdc1 $f2, THREAD_FPR2(\thread)
90 sdc1 $f4, THREAD_FPR4(\thread)
91 sdc1 $f6, THREAD_FPR6(\thread)
92 sdc1 $f8, THREAD_FPR8(\thread)
93 sdc1 $f10, THREAD_FPR10(\thread)
94 sdc1 $f12, THREAD_FPR12(\thread)
95 sdc1 $f14, THREAD_FPR14(\thread)
96 sdc1 $f16, THREAD_FPR16(\thread)
97 sdc1 $f18, THREAD_FPR18(\thread)
98 sdc1 $f20, THREAD_FPR20(\thread)
99 sdc1 $f22, THREAD_FPR22(\thread)
100 sdc1 $f24, THREAD_FPR24(\thread)
101 sdc1 $f26, THREAD_FPR26(\thread)
102 sdc1 $f28, THREAD_FPR28(\thread)
103 sdc1 $f30, THREAD_FPR30(\thread)
104 sw \tmp, THREAD_FCR31(\thread)
108 .macro fpu_save_16odd thread
113 sdc1 $f1, THREAD_FPR1(\thread)
114 sdc1 $f3, THREAD_FPR3(\thread)
115 sdc1 $f5, THREAD_FPR5(\thread)
116 sdc1 $f7, THREAD_FPR7(\thread)
117 sdc1 $f9, THREAD_FPR9(\thread)
118 sdc1 $f11, THREAD_FPR11(\thread)
119 sdc1 $f13, THREAD_FPR13(\thread)
120 sdc1 $f15, THREAD_FPR15(\thread)
121 sdc1 $f17, THREAD_FPR17(\thread)
122 sdc1 $f19, THREAD_FPR19(\thread)
123 sdc1 $f21, THREAD_FPR21(\thread)
124 sdc1 $f23, THREAD_FPR23(\thread)
125 sdc1 $f25, THREAD_FPR25(\thread)
126 sdc1 $f27, THREAD_FPR27(\thread)
127 sdc1 $f29, THREAD_FPR29(\thread)
128 sdc1 $f31, THREAD_FPR31(\thread)
132 .macro fpu_save_double thread status tmp
133 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
134 defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
137 fpu_save_16odd \thread
140 fpu_save_16even \thread \tmp
143 .macro fpu_restore_16even thread tmp=t0
146 lw \tmp, THREAD_FCR31(\thread)
147 ldc1 $f0, THREAD_FPR0(\thread)
148 ldc1 $f2, THREAD_FPR2(\thread)
149 ldc1 $f4, THREAD_FPR4(\thread)
150 ldc1 $f6, THREAD_FPR6(\thread)
151 ldc1 $f8, THREAD_FPR8(\thread)
152 ldc1 $f10, THREAD_FPR10(\thread)
153 ldc1 $f12, THREAD_FPR12(\thread)
154 ldc1 $f14, THREAD_FPR14(\thread)
155 ldc1 $f16, THREAD_FPR16(\thread)
156 ldc1 $f18, THREAD_FPR18(\thread)
157 ldc1 $f20, THREAD_FPR20(\thread)
158 ldc1 $f22, THREAD_FPR22(\thread)
159 ldc1 $f24, THREAD_FPR24(\thread)
160 ldc1 $f26, THREAD_FPR26(\thread)
161 ldc1 $f28, THREAD_FPR28(\thread)
162 ldc1 $f30, THREAD_FPR30(\thread)
167 .macro fpu_restore_16odd thread
172 ldc1 $f1, THREAD_FPR1(\thread)
173 ldc1 $f3, THREAD_FPR3(\thread)
174 ldc1 $f5, THREAD_FPR5(\thread)
175 ldc1 $f7, THREAD_FPR7(\thread)
176 ldc1 $f9, THREAD_FPR9(\thread)
177 ldc1 $f11, THREAD_FPR11(\thread)
178 ldc1 $f13, THREAD_FPR13(\thread)
179 ldc1 $f15, THREAD_FPR15(\thread)
180 ldc1 $f17, THREAD_FPR17(\thread)
181 ldc1 $f19, THREAD_FPR19(\thread)
182 ldc1 $f21, THREAD_FPR21(\thread)
183 ldc1 $f23, THREAD_FPR23(\thread)
184 ldc1 $f25, THREAD_FPR25(\thread)
185 ldc1 $f27, THREAD_FPR27(\thread)
186 ldc1 $f29, THREAD_FPR29(\thread)
187 ldc1 $f31, THREAD_FPR31(\thread)
191 .macro fpu_restore_double thread status tmp
192 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
193 defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
195 bgez \tmp, 10f # 16 register mode?
197 fpu_restore_16odd \thread
200 fpu_restore_16even \thread \tmp
203 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
204 defined(CONFIG_CPU_MIPSR6)
205 .macro _EXT rd, rs, p, s
208 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
209 .macro _EXT rd, rs, p, s
211 andi \rd, \rd, (1 << \s) - 1
213 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
216 * Temporary until all gas have MT ASE support
219 .word 0x41600bc1 | (\reg << 16)
223 .word 0x41600be1 | (\reg << 16)
227 .word 0x41600001 | (\reg << 16)
231 .word 0x41600021 | (\reg << 16)
234 .macro MFTR rt=0, rd=0, u=0, sel=0
235 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
238 .macro MTTR rt=0, rd=0, u=0, sel=0
239 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
242 #ifdef TOOLCHAIN_SUPPORTS_MSA
243 .macro _cfcmsa rd, cs
252 .macro _ctcmsa cd, rs
261 .macro ld_b wd, off, base
266 ld.b $w\wd, \off(\base)
270 .macro ld_h wd, off, base
275 ld.h $w\wd, \off(\base)
279 .macro ld_w wd, off, base
284 ld.w $w\wd, \off(\base)
288 .macro ld_d wd, off, base
293 ld.d $w\wd, \off(\base)
297 .macro st_b wd, off, base
302 st.b $w\wd, \off(\base)
306 .macro st_h wd, off, base
311 st.h $w\wd, \off(\base)
315 .macro st_w wd, off, base
320 st.w $w\wd, \off(\base)
324 .macro st_d wd, off, base
329 st.d $w\wd, \off(\base)
333 .macro copy_s_w ws, n
338 copy_s.w $1, $w\ws[\n]
342 .macro copy_s_d ws, n
347 copy_s.d $1, $w\ws[\n]
351 .macro insert_w wd, n
356 insert.w $w\wd[\n], $1
360 .macro insert_d wd, n
365 insert.d $w\wd[\n], $1
371 * Temporary until all toolchains in use include MSA support.
373 .macro _cfcmsa rd, cs
377 insn_if_mips 0x787e0059 | (\cs << 11)
378 insn32_if_mm 0x587e0056 | (\cs << 11)
383 .macro _ctcmsa cd, rs
388 insn_if_mips 0x783e0819 | (\cd << 6)
389 insn32_if_mm 0x583e0816 | (\cd << 6)
393 .macro ld_b wd, off, base
397 PTR_ADDU $1, \base, \off
398 insn_if_mips 0x78000820 | (\wd << 6)
399 insn32_if_mm 0x58000807 | (\wd << 6)
403 .macro ld_h wd, off, base
407 PTR_ADDU $1, \base, \off
408 insn_if_mips 0x78000821 | (\wd << 6)
409 insn32_if_mm 0x58000817 | (\wd << 6)
413 .macro ld_w wd, off, base
417 PTR_ADDU $1, \base, \off
418 insn_if_mips 0x78000822 | (\wd << 6)
419 insn32_if_mm 0x58000827 | (\wd << 6)
423 .macro ld_d wd, off, base
427 PTR_ADDU $1, \base, \off
428 insn_if_mips 0x78000823 | (\wd << 6)
429 insn32_if_mm 0x58000837 | (\wd << 6)
433 .macro st_b wd, off, base
437 PTR_ADDU $1, \base, \off
438 insn_if_mips 0x78000824 | (\wd << 6)
439 insn32_if_mm 0x5800080f | (\wd << 6)
443 .macro st_h wd, off, base
447 PTR_ADDU $1, \base, \off
448 insn_if_mips 0x78000825 | (\wd << 6)
449 insn32_if_mm 0x5800081f | (\wd << 6)
453 .macro st_w wd, off, base
457 PTR_ADDU $1, \base, \off
458 insn_if_mips 0x78000826 | (\wd << 6)
459 insn32_if_mm 0x5800082f | (\wd << 6)
463 .macro st_d wd, off, base
467 PTR_ADDU $1, \base, \off
468 insn_if_mips 0x78000827 | (\wd << 6)
469 insn32_if_mm 0x5800083f | (\wd << 6)
473 .macro copy_s_w ws, n
477 insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
478 insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
482 .macro copy_s_d ws, n
486 insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
487 insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
491 .macro insert_w wd, n
495 insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
496 insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
500 .macro insert_d wd, n
504 insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
505 insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
510 #ifdef TOOLCHAIN_SUPPORTS_MSA
511 #define FPR_BASE_OFFS THREAD_FPR0
514 #define FPR_BASE_OFFS 0
515 #define FPR_BASE \thread
518 .macro msa_save_all thread
521 #ifdef TOOLCHAIN_SUPPORTS_MSA
522 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
524 st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
525 st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
526 st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
527 st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
528 st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
529 st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
530 st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
531 st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
532 st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
533 st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
534 st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
535 st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
536 st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
537 st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
538 st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
539 st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
540 st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
541 st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
542 st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
543 st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
544 st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
545 st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
546 st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
547 st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
548 st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
549 st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
550 st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
551 st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
552 st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
553 st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
554 st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
555 st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
558 sw $1, THREAD_MSA_CSR(\thread)
562 .macro msa_restore_all thread
566 lw $1, THREAD_MSA_CSR(\thread)
568 #ifdef TOOLCHAIN_SUPPORTS_MSA
569 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
571 ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
572 ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
573 ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
574 ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
575 ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
576 ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
577 ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
578 ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
579 ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
580 ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
581 ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
582 ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
583 ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
584 ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
585 ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
586 ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
587 ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
588 ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
589 ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
590 ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
591 ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
592 ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
593 ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
594 ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
595 ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
596 ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
597 ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
598 ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
599 ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
600 ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
601 ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
602 ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
609 .macro msa_init_upper wd
618 .macro msa_init_all_upper
658 #endif /* _ASM_ASMMACRO_H */