2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 * Some useful macros for MIPS assembler code
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
20 #include <asm/sgidefs.h>
21 #include <asm/asm-eva.h>
25 #define __CAT(str1, str2) str1##str2
27 #define __CAT(str1, str2) str1/**/str2
29 #define CAT(str1, str2) __CAT(str1, str2)
33 * PIC specific declarations
34 * Not used for the kernel but here seems to be the right place.
37 #define CPRESTORE(register) \
39 #define CPADD(register) \
41 #define CPLOAD(register) \
44 #define CPRESTORE(register)
45 #define CPADD(register)
46 #define CPLOAD(register)
50 * LEAF - declare leaf routine
52 #define LEAF(symbol) \
55 .type symbol, @function; \
57 symbol: .frame sp, 0, ra; \
61 * NESTED - declare nested routine entry point
63 #define NESTED(symbol, framesize, rpc) \
66 .type symbol, @function; \
68 symbol: .frame sp, framesize, rpc; \
72 * END - mark end of function
74 #define END(function) \
76 .size function, .-function
79 * EXPORT - export definition of symbol
81 #define EXPORT(symbol) \
86 * FEXPORT - export definition of a function symbol
88 #define FEXPORT(symbol) \
90 .type symbol, @function; \
94 * ABS - export absolute symbol
96 #define ABS(symbol,value) \
110 * Print formatted string
113 #define PRINT(string) \
121 #define PRINT(string)
125 .pushsection .data; \
132 #define TTABLE(string) \
133 .pushsection .text; \
136 .pushsection .data; \
141 * MIPS IV pref instruction.
142 * Use with .set noreorder only!
144 * MIPS IV implementations are free to treat this as a nop. The R5000
145 * is one of them. So we should have an option not to use this instruction.
147 #ifdef CONFIG_CPU_HAS_PREFETCH
149 #define PREF(hint,addr) \
155 #define PREFE(hint, addr) \
162 #define PREFX(hint,addr) \
168 #else /* !CONFIG_CPU_HAS_PREFETCH */
170 #define PREF(hint, addr)
171 #define PREFE(hint, addr)
172 #define PREFX(hint, addr)
174 #endif /* !CONFIG_CPU_HAS_PREFETCH */
177 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
179 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
180 #define MOVN(rd, rs, rt) \
187 #define MOVZ(rd, rs, rt) \
194 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
195 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
196 #define MOVN(rd, rs, rt) \
203 #define MOVZ(rd, rs, rt) \
210 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
211 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
212 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
213 #define MOVN(rd, rs, rt) \
215 #define MOVZ(rd, rs, rt) \
217 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
222 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
226 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
232 * Macros to handle different pointer/register sizes for 32/64-bit code
245 * Use the following macros in assemblercode to load/store registers,
248 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
251 #define REG_SUBU subu
252 #define REG_ADDU addu
254 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
257 #define REG_SUBU dsubu
258 #define REG_ADDU daddu
262 * How to add/sub/load/store/shift C int variables.
264 #if (_MIPS_SZINT == 32)
266 #define INT_ADDU addu
267 #define INT_ADDI addi
268 #define INT_ADDIU addiu
270 #define INT_SUBU subu
274 #define INT_SLLV sllv
276 #define INT_SRLV srlv
278 #define INT_SRAV srav
281 #if (_MIPS_SZINT == 64)
283 #define INT_ADDU daddu
284 #define INT_ADDI daddi
285 #define INT_ADDIU daddiu
287 #define INT_SUBU dsubu
291 #define INT_SLLV dsllv
293 #define INT_SRLV dsrlv
295 #define INT_SRAV dsrav
299 * How to add/sub/load/store/shift C long variables.
301 #if (_MIPS_SZLONG == 32)
303 #define LONG_ADDU addu
304 #define LONG_ADDI addi
305 #define LONG_ADDIU addiu
307 #define LONG_SUBU subu
312 #define LONG_SLLV sllv
314 #define LONG_SRLV srlv
316 #define LONG_SRAV srav
324 #if (_MIPS_SZLONG == 64)
325 #define LONG_ADD dadd
326 #define LONG_ADDU daddu
327 #define LONG_ADDI daddi
328 #define LONG_ADDIU daddiu
329 #define LONG_SUB dsub
330 #define LONG_SUBU dsubu
334 #define LONG_SLL dsll
335 #define LONG_SLLV dsllv
336 #define LONG_SRL dsrl
337 #define LONG_SRLV dsrlv
338 #define LONG_SRA dsra
339 #define LONG_SRAV dsrav
348 * How to add/sub/load/store/shift pointers.
350 #if (_MIPS_SZPTR == 32)
352 #define PTR_ADDU addu
353 #define PTR_ADDI addi
354 #define PTR_ADDIU addiu
356 #define PTR_SUBU subu
362 #define PTR_SLLV sllv
364 #define PTR_SRLV srlv
366 #define PTR_SRAV srav
368 #define PTR_SCALESHIFT 2
375 #if (_MIPS_SZPTR == 64)
377 #define PTR_ADDU daddu
378 #define PTR_ADDI daddi
379 #define PTR_ADDIU daddiu
381 #define PTR_SUBU dsubu
387 #define PTR_SLLV dsllv
389 #define PTR_SRLV dsrlv
391 #define PTR_SRAV dsrav
393 #define PTR_SCALESHIFT 3
401 * Some cp0 registers were extended to 64bit for MIPS III.
403 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
407 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
412 #define SSNOP sll zero, zero, 1
414 #ifdef CONFIG_SGI_IP28
415 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
416 #include <asm/cacheops.h>
417 #define R10KCBARRIER(addr) cache Cache_Barrier, addr;
419 #define R10KCBARRIER(addr)
422 #endif /* __ASM_ASM_H */