2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 * Some useful macros for MIPS assembler code
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
20 #include <asm/sgidefs.h>
21 #include <asm/asm-eva.h>
22 #include <asm/isa-rev.h>
26 * Emit CFI data in .debug_frame sections, not .eh_frame sections.
27 * We don't do DWARF unwinding at runtime, so only the offline DWARF
28 * information is useful to anyone. Note we should change this if we
29 * ever decide to enable DWARF unwinding at runtime.
31 #define CFI_SECTIONS .cfi_sections .debug_frame
34 * For the vDSO, emit both runtime unwind information and debug
35 * symbols for the .dbg file.
41 * LEAF - declare leaf routine
43 #define LEAF(symbol) \
47 .type symbol, @function; \
49 symbol: .frame sp, 0, ra; \
54 * NESTED - declare nested routine entry point
56 #define NESTED(symbol, framesize, rpc) \
60 .type symbol, @function; \
62 symbol: .frame sp, framesize, rpc; \
67 * END - mark end of function
69 #define END(function) \
72 .size function, .-function
75 * EXPORT - export definition of symbol
77 #define EXPORT(symbol) \
82 * FEXPORT - export definition of a function symbol
84 #define FEXPORT(symbol) \
86 .type symbol, @function; \
90 * ABS - export absolute symbol
92 #define ABS(symbol,value) \
101 #define ASM_PANIC(msg) \
111 * Print formatted string
114 #define ASM_PRINT(string) \
122 #define ASM_PRINT(string)
128 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
132 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
138 * Macros to handle different pointer/register sizes for 32/64-bit code
151 * Use the following macros in assemblercode to load/store registers,
154 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
157 #define REG_SUBU subu
158 #define REG_ADDU addu
160 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
163 #define REG_SUBU dsubu
164 #define REG_ADDU daddu
168 * How to add/sub/load/store/shift C int variables.
170 #if (_MIPS_SZINT == 32)
172 #define INT_ADDU addu
173 #define INT_ADDI addi
174 #define INT_ADDIU addiu
176 #define INT_SUBU subu
180 #define INT_SLLV sllv
182 #define INT_SRLV srlv
184 #define INT_SRAV srav
187 #if (_MIPS_SZINT == 64)
189 #define INT_ADDU daddu
190 #define INT_ADDI daddi
191 #define INT_ADDIU daddiu
193 #define INT_SUBU dsubu
197 #define INT_SLLV dsllv
199 #define INT_SRLV dsrlv
201 #define INT_SRAV dsrav
205 * How to add/sub/load/store/shift C long variables.
207 #if (_MIPS_SZLONG == 32)
209 #define LONG_ADDU addu
210 #define LONG_ADDI addi
211 #define LONG_ADDIU addiu
213 #define LONG_SUBU subu
220 #define LONG_SLLV sllv
222 #define LONG_SRLV srlv
224 #define LONG_SRAV srav
236 #if (_MIPS_SZLONG == 64)
237 #define LONG_ADD dadd
238 #define LONG_ADDU daddu
239 #define LONG_ADDI daddi
240 #define LONG_ADDIU daddiu
241 #define LONG_SUB dsub
242 #define LONG_SUBU dsubu
248 #define LONG_SLL dsll
249 #define LONG_SLLV dsllv
250 #define LONG_SRL dsrl
251 #define LONG_SRLV dsrlv
252 #define LONG_SRA dsra
253 #define LONG_SRAV dsrav
254 #define LONG_INS dins
255 #define LONG_EXT dext
266 * How to add/sub/load/store/shift pointers.
268 #if (_MIPS_SZPTR == 32)
270 #define PTR_ADDU addu
271 #define PTR_ADDI addi
272 #define PTR_ADDIU addiu
274 #define PTR_SUBU subu
280 #define PTR_SLLV sllv
282 #define PTR_SRLV srlv
284 #define PTR_SRAV srav
286 #define PTR_SCALESHIFT 2
293 #if (_MIPS_SZPTR == 64)
295 #define PTR_ADDU daddu
296 #define PTR_ADDI daddi
297 #define PTR_ADDIU daddiu
299 #define PTR_SUBU dsubu
305 #define PTR_SLLV dsllv
307 #define PTR_SRLV dsrlv
309 #define PTR_SRAV dsrav
311 #define PTR_SCALESHIFT 3
313 #define PTR_WD .dword
319 * Some cp0 registers were extended to 64bit for MIPS III.
321 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
325 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
330 #define SSNOP sll zero, zero, 1
333 * Using a branch-likely instruction to check the result of an sc instruction
334 * works around a bug present in R10000 CPUs prior to revision 3.0 that could
335 * cause ll-sc sequences to execute non-atomically.
337 #ifdef CONFIG_WAR_R10000_LLSC
338 # define SC_BEQZ beqzl
339 #elif !defined(CONFIG_CC_HAS_BROKEN_INLINE_COMPAT_BRANCH) && MIPS_ISA_REV >= 6
340 # define SC_BEQZ beqzc
342 # define SC_BEQZ beqz
345 #ifdef CONFIG_SGI_IP28
346 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
347 #include <asm/cacheops.h>
348 #define R10KCBARRIER(addr) cache Cache_Barrier, addr;
350 #define R10KCBARRIER(addr)
353 #endif /* __ASM_ASM_H */