arch/mips/dec/setup.c

   1 /*
   2  * System-specific setup, especially interrupts.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1998 Harald Koerfgen
   9  * Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020  Maciej W. Rozycki
  10  */
  11 #include <linux/console.h>
  12 #include <linux/export.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ioport.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqnr.h>
  18 #include <linux/memblock.h>
  19 #include <linux/param.h>
  20 #include <linux/percpu-defs.h>
  21 #include <linux/sched.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/types.h>
  24 #include <linux/pm.h>
  25
  26 #include <asm/addrspace.h>
  27 #include <asm/bootinfo.h>
  28 #include <asm/cpu.h>
  29 #include <asm/cpu-features.h>
  30 #include <asm/cpu-type.h>
  31 #include <asm/irq.h>
  32 #include <asm/irq_cpu.h>
  33 #include <asm/mipsregs.h>
  34 #include <asm/page.h>
  35 #include <asm/reboot.h>
  36 #include <asm/sections.h>
  37 #include <asm/time.h>
  38 #include <asm/traps.h>
  39 #include <asm/wbflush.h>
  40
  41 #include <asm/dec/interrupts.h>
  42 #include <asm/dec/ioasic.h>
  43 #include <asm/dec/ioasic_addrs.h>
  44 #include <asm/dec/ioasic_ints.h>
  45 #include <asm/dec/kn01.h>
  46 #include <asm/dec/kn02.h>
  47 #include <asm/dec/kn02ba.h>
  48 #include <asm/dec/kn02ca.h>
  49 #include <asm/dec/kn03.h>
  50 #include <asm/dec/kn230.h>
  51 #include <asm/dec/system.h>
  52
  53
  54 extern void dec_machine_restart(char *command);
  55 extern void dec_machine_halt(void);
  56 extern void dec_machine_power_off(void);
  57 extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
  58
  59 unsigned long dec_kn_slot_base, dec_kn_slot_size;
  60
  61 EXPORT_SYMBOL(dec_kn_slot_base);
  62 EXPORT_SYMBOL(dec_kn_slot_size);
  63
  64 int dec_tc_bus;
  65
  66 DEFINE_SPINLOCK(ioasic_ssr_lock);
  67 EXPORT_SYMBOL(ioasic_ssr_lock);
  68
  69 volatile u32 *ioasic_base;
  70
  71 EXPORT_SYMBOL(ioasic_base);
  72
  73 /*
  74  * IRQ routing and priority tables.  Priorites are set as follows:
  75  *
  76  *              KN01    KN230   KN02    KN02-BA KN02-CA KN03
  77  *
  78  * MEMORY       CPU     CPU     CPU     ASIC    CPU     CPU
  79  * RTC          CPU     CPU     CPU     ASIC    CPU     CPU
  80  * DMA          -       -       -       ASIC    ASIC    ASIC
  81  * SERIAL0      CPU     CPU     CSR     ASIC    ASIC    ASIC
  82  * SERIAL1      -       -       -       ASIC    -       ASIC
  83  * SCSI         CPU     CPU     CSR     ASIC    ASIC    ASIC
  84  * ETHERNET     CPU     *       CSR     ASIC    ASIC    ASIC
  85  * other        -       -       -       ASIC    -       -
  86  * TC2          -       -       CSR     CPU     ASIC    ASIC
  87  * TC1          -       -       CSR     CPU     ASIC    ASIC
  88  * TC0          -       -       CSR     CPU     ASIC    ASIC
  89  * other        -       CPU     -       CPU     ASIC    ASIC
  90  * other        -       -       -       -       CPU     CPU
  91  *
  92  * * -- shared with SCSI
  93  */
  94
  95 int dec_interrupt[DEC_NR_INTS] = {
  96         [0 ... DEC_NR_INTS - 1] = -1
  97 };
  98
  99 EXPORT_SYMBOL(dec_interrupt);
 100
 101 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
 102         { { .i = ~0 }, { .p = dec_intr_unimplemented } },
 103 };
 104 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
 105         { { .i = ~0 }, { .p = asic_intr_unimplemented } },
 106 };
 107 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
 108 int *fpu_kstat_irq;
 109
 110 static struct irqaction ioirq = {
 111         .handler = no_action,
 112         .name = "cascade",
 113         .flags = IRQF_NO_THREAD,
 114 };
 115 static struct irqaction fpuirq = {
 116         .handler = no_action,
 117         .name = "fpu",
 118         .flags = IRQF_NO_THREAD,
 119 };
 120
 121 static struct irqaction busirq = {
 122         .name = "bus error",
 123         .flags = IRQF_NO_THREAD,
 124 };
 125
 126 static struct irqaction haltirq = {
 127         .handler = dec_intr_halt,
 128         .name = "halt",
 129         .flags = IRQF_NO_THREAD,
 130 };
 131
 132
 133 /*
 134  * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
 135  */
 136 static void __init dec_be_init(void)
 137 {
 138         switch (mips_machtype) {
 139         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 140                 board_be_handler = dec_kn01_be_handler;
 141                 busirq.handler = dec_kn01_be_interrupt;
 142                 busirq.flags |= IRQF_SHARED;
 143                 dec_kn01_be_init();
 144                 break;
 145         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 146         case MACH_DS5000_XX:    /* DS5000/xx Maxine */
 147                 board_be_handler = dec_kn02xa_be_handler;
 148                 busirq.handler = dec_kn02xa_be_interrupt;
 149                 dec_kn02xa_be_init();
 150                 break;
 151         case MACH_DS5000_200:   /* DS5000/200 3max */
 152         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 153         case MACH_DS5900:       /* DS5900 bigmax */
 154                 board_be_handler = dec_ecc_be_handler;
 155                 busirq.handler = dec_ecc_be_interrupt;
 156                 dec_ecc_be_init();
 157                 break;
 158         }
 159 }
 160
 161 void __init plat_mem_setup(void)
 162 {
 163         board_be_init = dec_be_init;
 164
 165         wbflush_setup();
 166
 167         _machine_restart = dec_machine_restart;
 168         _machine_halt = dec_machine_halt;
 169         pm_power_off = dec_machine_power_off;
 170
 171         ioport_resource.start = ~0UL;
 172         ioport_resource.end = 0UL;
 173
 174         /* Stay away from the firmware working memory area for now. */
 175         memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET);
 176 }
 177
 178 /*
 179  * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
 180  * or DS3100 (aka Pmax).
 181  */
 182 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
 183         [DEC_IRQ_CASCADE]       = -1,
 184         [DEC_IRQ_AB_RECV]       = -1,
 185         [DEC_IRQ_AB_XMIT]       = -1,
 186         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
 187         [DEC_IRQ_ASC]           = -1,
 188         [DEC_IRQ_FLOPPY]        = -1,
 189         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 190         [DEC_IRQ_HALT]          = -1,
 191         [DEC_IRQ_ISDN]          = -1,
 192         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
 193         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
 194         [DEC_IRQ_PSU]           = -1,
 195         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
 196         [DEC_IRQ_SCC0]          = -1,
 197         [DEC_IRQ_SCC1]          = -1,
 198         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
 199         [DEC_IRQ_TC0]           = -1,
 200         [DEC_IRQ_TC1]           = -1,
 201         [DEC_IRQ_TC2]           = -1,
 202         [DEC_IRQ_TIMER]         = -1,
 203         [DEC_IRQ_VIDEO]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
 204         [DEC_IRQ_ASC_MERR]      = -1,
 205         [DEC_IRQ_ASC_ERR]       = -1,
 206         [DEC_IRQ_ASC_DMA]       = -1,
 207         [DEC_IRQ_FLOPPY_ERR]    = -1,
 208         [DEC_IRQ_ISDN_ERR]      = -1,
 209         [DEC_IRQ_ISDN_RXDMA]    = -1,
 210         [DEC_IRQ_ISDN_TXDMA]    = -1,
 211         [DEC_IRQ_LANCE_MERR]    = -1,
 212         [DEC_IRQ_SCC0A_RXERR]   = -1,
 213         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 214         [DEC_IRQ_SCC0A_TXERR]   = -1,
 215         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 216         [DEC_IRQ_AB_RXERR]      = -1,
 217         [DEC_IRQ_AB_RXDMA]      = -1,
 218         [DEC_IRQ_AB_TXERR]      = -1,
 219         [DEC_IRQ_AB_TXDMA]      = -1,
 220         [DEC_IRQ_SCC1A_RXERR]   = -1,
 221         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 222         [DEC_IRQ_SCC1A_TXERR]   = -1,
 223         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 224 };
 225
 226 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
 227         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
 228                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
 229         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
 230                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
 231         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
 232                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
 233         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
 234                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
 235         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
 236                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
 237         { { .i = DEC_CPU_IRQ_ALL },
 238                 { .p = cpu_all_int } },
 239 };
 240
 241 static void __init dec_init_kn01(void)
 242 {
 243         /* IRQ routing. */
 244         memcpy(&dec_interrupt, &kn01_interrupt,
 245                 sizeof(kn01_interrupt));
 246
 247         /* CPU IRQ priorities. */
 248         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
 249                 sizeof(kn01_cpu_mask_nr_tbl));
 250
 251         mips_cpu_irq_init();
 252
 253 }                               /* dec_init_kn01 */
 254
 255
 256 /*
 257  * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
 258  */
 259 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
 260         [DEC_IRQ_CASCADE]       = -1,
 261         [DEC_IRQ_AB_RECV]       = -1,
 262         [DEC_IRQ_AB_XMIT]       = -1,
 263         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
 264         [DEC_IRQ_ASC]           = -1,
 265         [DEC_IRQ_FLOPPY]        = -1,
 266         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 267         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
 268         [DEC_IRQ_ISDN]          = -1,
 269         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
 270         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
 271         [DEC_IRQ_PSU]           = -1,
 272         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
 273         [DEC_IRQ_SCC0]          = -1,
 274         [DEC_IRQ_SCC1]          = -1,
 275         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
 276         [DEC_IRQ_TC0]           = -1,
 277         [DEC_IRQ_TC1]           = -1,
 278         [DEC_IRQ_TC2]           = -1,
 279         [DEC_IRQ_TIMER]         = -1,
 280         [DEC_IRQ_VIDEO]         = -1,
 281         [DEC_IRQ_ASC_MERR]      = -1,
 282         [DEC_IRQ_ASC_ERR]       = -1,
 283         [DEC_IRQ_ASC_DMA]       = -1,
 284         [DEC_IRQ_FLOPPY_ERR]    = -1,
 285         [DEC_IRQ_ISDN_ERR]      = -1,
 286         [DEC_IRQ_ISDN_RXDMA]    = -1,
 287         [DEC_IRQ_ISDN_TXDMA]    = -1,
 288         [DEC_IRQ_LANCE_MERR]    = -1,
 289         [DEC_IRQ_SCC0A_RXERR]   = -1,
 290         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 291         [DEC_IRQ_SCC0A_TXERR]   = -1,
 292         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 293         [DEC_IRQ_AB_RXERR]      = -1,
 294         [DEC_IRQ_AB_RXDMA]      = -1,
 295         [DEC_IRQ_AB_TXERR]      = -1,
 296         [DEC_IRQ_AB_TXDMA]      = -1,
 297         [DEC_IRQ_SCC1A_RXERR]   = -1,
 298         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 299         [DEC_IRQ_SCC1A_TXERR]   = -1,
 300         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 301 };
 302
 303 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
 304         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
 305                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
 306         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
 307                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
 308         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
 309                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
 310         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
 311                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
 312         { { .i = DEC_CPU_IRQ_ALL },
 313                 { .p = cpu_all_int } },
 314 };
 315
 316 static void __init dec_init_kn230(void)
 317 {
 318         /* IRQ routing. */
 319         memcpy(&dec_interrupt, &kn230_interrupt,
 320                 sizeof(kn230_interrupt));
 321
 322         /* CPU IRQ priorities. */
 323         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
 324                 sizeof(kn230_cpu_mask_nr_tbl));
 325
 326         mips_cpu_irq_init();
 327
 328 }                               /* dec_init_kn230 */
 329
 330
 331 /*
 332  * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
 333  */
 334 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
 335         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
 336         [DEC_IRQ_AB_RECV]       = -1,
 337         [DEC_IRQ_AB_XMIT]       = -1,
 338         [DEC_IRQ_DZ11]          = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
 339         [DEC_IRQ_ASC]           = KN02_IRQ_NR(KN02_CSR_INR_ASC),
 340         [DEC_IRQ_FLOPPY]        = -1,
 341         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 342         [DEC_IRQ_HALT]          = -1,
 343         [DEC_IRQ_ISDN]          = -1,
 344         [DEC_IRQ_LANCE]         = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
 345         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
 346         [DEC_IRQ_PSU]           = -1,
 347         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
 348         [DEC_IRQ_SCC0]          = -1,
 349         [DEC_IRQ_SCC1]          = -1,
 350         [DEC_IRQ_SII]           = -1,
 351         [DEC_IRQ_TC0]           = KN02_IRQ_NR(KN02_CSR_INR_TC0),
 352         [DEC_IRQ_TC1]           = KN02_IRQ_NR(KN02_CSR_INR_TC1),
 353         [DEC_IRQ_TC2]           = KN02_IRQ_NR(KN02_CSR_INR_TC2),
 354         [DEC_IRQ_TIMER]         = -1,
 355         [DEC_IRQ_VIDEO]         = -1,
 356         [DEC_IRQ_ASC_MERR]      = -1,
 357         [DEC_IRQ_ASC_ERR]       = -1,
 358         [DEC_IRQ_ASC_DMA]       = -1,
 359         [DEC_IRQ_FLOPPY_ERR]    = -1,
 360         [DEC_IRQ_ISDN_ERR]      = -1,
 361         [DEC_IRQ_ISDN_RXDMA]    = -1,
 362         [DEC_IRQ_ISDN_TXDMA]    = -1,
 363         [DEC_IRQ_LANCE_MERR]    = -1,
 364         [DEC_IRQ_SCC0A_RXERR]   = -1,
 365         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 366         [DEC_IRQ_SCC0A_TXERR]   = -1,
 367         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 368         [DEC_IRQ_AB_RXERR]      = -1,
 369         [DEC_IRQ_AB_RXDMA]      = -1,
 370         [DEC_IRQ_AB_TXERR]      = -1,
 371         [DEC_IRQ_AB_TXDMA]      = -1,
 372         [DEC_IRQ_SCC1A_RXERR]   = -1,
 373         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 374         [DEC_IRQ_SCC1A_TXERR]   = -1,
 375         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 376 };
 377
 378 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
 379         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
 380                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
 381         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
 382                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
 383         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
 384                 { .p = kn02_io_int } },
 385         { { .i = DEC_CPU_IRQ_ALL },
 386                 { .p = cpu_all_int } },
 387 };
 388
 389 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
 390         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
 391                 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
 392         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
 393                 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
 394         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
 395                 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
 396         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
 397                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
 398         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
 399                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
 400         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
 401                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
 402         { { .i = KN02_IRQ_ALL },
 403                 { .p = kn02_all_int } },
 404 };
 405
 406 static void __init dec_init_kn02(void)
 407 {
 408         /* IRQ routing. */
 409         memcpy(&dec_interrupt, &kn02_interrupt,
 410                 sizeof(kn02_interrupt));
 411
 412         /* CPU IRQ priorities. */
 413         memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
 414                 sizeof(kn02_cpu_mask_nr_tbl));
 415
 416         /* KN02 CSR IRQ priorities. */
 417         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
 418                 sizeof(kn02_asic_mask_nr_tbl));
 419
 420         mips_cpu_irq_init();
 421         init_kn02_irqs(KN02_IRQ_BASE);
 422
 423 }                               /* dec_init_kn02 */
 424
 425
 426 /*
 427  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 428  * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
 429  * DS5000/150, aka 4min.
 430  */
 431 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
 432         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
 433         [DEC_IRQ_AB_RECV]       = -1,
 434         [DEC_IRQ_AB_XMIT]       = -1,
 435         [DEC_IRQ_DZ11]          = -1,
 436         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02BA_IO_INR_ASC),
 437         [DEC_IRQ_FLOPPY]        = -1,
 438         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 439         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
 440         [DEC_IRQ_ISDN]          = -1,
 441         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
 442         [DEC_IRQ_BUS]           = IO_IRQ_NR(KN02BA_IO_INR_BUS),
 443         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN02BA_IO_INR_PSU),
 444         [DEC_IRQ_RTC]           = IO_IRQ_NR(KN02BA_IO_INR_RTC),
 445         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
 446         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
 447         [DEC_IRQ_SII]           = -1,
 448         [DEC_IRQ_TC0]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
 449         [DEC_IRQ_TC1]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
 450         [DEC_IRQ_TC2]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
 451         [DEC_IRQ_TIMER]         = -1,
 452         [DEC_IRQ_VIDEO]         = -1,
 453         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 454         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 455         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 456         [DEC_IRQ_FLOPPY_ERR]    = -1,
 457         [DEC_IRQ_ISDN_ERR]      = -1,
 458         [DEC_IRQ_ISDN_RXDMA]    = -1,
 459         [DEC_IRQ_ISDN_TXDMA]    = -1,
 460         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 461         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 462         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 463         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 464         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 465         [DEC_IRQ_AB_RXERR]      = -1,
 466         [DEC_IRQ_AB_RXDMA]      = -1,
 467         [DEC_IRQ_AB_TXERR]      = -1,
 468         [DEC_IRQ_AB_TXDMA]      = -1,
 469         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 470         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 471         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 472         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 473 };
 474
 475 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
 476         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
 477                 { .p = kn02xa_io_int } },
 478         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
 479                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
 480         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
 481                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
 482         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
 483                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
 484         { { .i = DEC_CPU_IRQ_ALL },
 485                 { .p = cpu_all_int } },
 486 };
 487
 488 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
 489         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
 490                 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
 491         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
 492                 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
 493         { { .i = IO_IRQ_DMA },
 494                 { .p = asic_dma_int } },
 495         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
 496                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
 497         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
 498                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
 499         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
 500                 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
 501         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
 502                 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
 503         { { .i = IO_IRQ_ALL },
 504                 { .p = asic_all_int } },
 505 };
 506
 507 static void __init dec_init_kn02ba(void)
 508 {
 509         /* IRQ routing. */
 510         memcpy(&dec_interrupt, &kn02ba_interrupt,
 511                 sizeof(kn02ba_interrupt));
 512
 513         /* CPU IRQ priorities. */
 514         memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
 515                 sizeof(kn02ba_cpu_mask_nr_tbl));
 516
 517         /* I/O ASIC IRQ priorities. */
 518         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
 519                 sizeof(kn02ba_asic_mask_nr_tbl));
 520
 521         mips_cpu_irq_init();
 522         init_ioasic_irqs(IO_IRQ_BASE);
 523
 524 }                               /* dec_init_kn02ba */
 525
 526
 527 /*
 528  * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
 529  * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
 530  * DS5000/50, aka 4MAXine.
 531  */
 532 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
 533         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
 534         [DEC_IRQ_AB_RECV]       = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
 535         [DEC_IRQ_AB_XMIT]       = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
 536         [DEC_IRQ_DZ11]          = -1,
 537         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02CA_IO_INR_ASC),
 538         [DEC_IRQ_FLOPPY]        = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
 539         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 540         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
 541         [DEC_IRQ_ISDN]          = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
 542         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
 543         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
 544         [DEC_IRQ_PSU]           = -1,
 545         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
 546         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
 547         [DEC_IRQ_SCC1]          = -1,
 548         [DEC_IRQ_SII]           = -1,
 549         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN02CA_IO_INR_TC0),
 550         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN02CA_IO_INR_TC1),
 551         [DEC_IRQ_TC2]           = -1,
 552         [DEC_IRQ_TIMER]         = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
 553         [DEC_IRQ_VIDEO]         = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
 554         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 555         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 556         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 557         [DEC_IRQ_FLOPPY_ERR]    = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
 558         [DEC_IRQ_ISDN_ERR]      = IO_IRQ_NR(IO_INR_ISDN_ERR),
 559         [DEC_IRQ_ISDN_RXDMA]    = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
 560         [DEC_IRQ_ISDN_TXDMA]    = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
 561         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 562         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 563         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 564         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 565         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 566         [DEC_IRQ_AB_RXERR]      = IO_IRQ_NR(IO_INR_AB_RXERR),
 567         [DEC_IRQ_AB_RXDMA]      = IO_IRQ_NR(IO_INR_AB_RXDMA),
 568         [DEC_IRQ_AB_TXERR]      = IO_IRQ_NR(IO_INR_AB_TXERR),
 569         [DEC_IRQ_AB_TXDMA]      = IO_IRQ_NR(IO_INR_AB_TXDMA),
 570         [DEC_IRQ_SCC1A_RXERR]   = -1,
 571         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 572         [DEC_IRQ_SCC1A_TXERR]   = -1,
 573         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 574 };
 575
 576 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
 577         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
 578                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
 579         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
 580                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
 581         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
 582                 { .p = kn02xa_io_int } },
 583         { { .i = DEC_CPU_IRQ_ALL },
 584                 { .p = cpu_all_int } },
 585 };
 586
 587 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
 588         { { .i = IO_IRQ_DMA },
 589                 { .p = asic_dma_int } },
 590         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
 591                 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
 592         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
 593                 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
 594         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
 595                 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
 596         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
 597                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
 598         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
 599                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
 600         { { .i = IO_IRQ_ALL },
 601                 { .p = asic_all_int } },
 602 };
 603
 604 static void __init dec_init_kn02ca(void)
 605 {
 606         /* IRQ routing. */
 607         memcpy(&dec_interrupt, &kn02ca_interrupt,
 608                 sizeof(kn02ca_interrupt));
 609
 610         /* CPU IRQ priorities. */
 611         memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
 612                 sizeof(kn02ca_cpu_mask_nr_tbl));
 613
 614         /* I/O ASIC IRQ priorities. */
 615         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
 616                 sizeof(kn02ca_asic_mask_nr_tbl));
 617
 618         mips_cpu_irq_init();
 619         init_ioasic_irqs(IO_IRQ_BASE);
 620
 621 }                               /* dec_init_kn02ca */
 622
 623
 624 /*
 625  * Machine-specific initialisation for KN03, aka DS5000/240,
 626  * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
 627  * DS5000/260, aka 4max+ and DS5900/260.
 628  */
 629 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
 630         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
 631         [DEC_IRQ_AB_RECV]       = -1,
 632         [DEC_IRQ_AB_XMIT]       = -1,
 633         [DEC_IRQ_DZ11]          = -1,
 634         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN03_IO_INR_ASC),
 635         [DEC_IRQ_FLOPPY]        = -1,
 636         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 637         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
 638         [DEC_IRQ_ISDN]          = -1,
 639         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN03_IO_INR_LANCE),
 640         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
 641         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN03_IO_INR_PSU),
 642         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
 643         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN03_IO_INR_SCC0),
 644         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN03_IO_INR_SCC1),
 645         [DEC_IRQ_SII]           = -1,
 646         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN03_IO_INR_TC0),
 647         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN03_IO_INR_TC1),
 648         [DEC_IRQ_TC2]           = IO_IRQ_NR(KN03_IO_INR_TC2),
 649         [DEC_IRQ_TIMER]         = -1,
 650         [DEC_IRQ_VIDEO]         = -1,
 651         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 652         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 653         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 654         [DEC_IRQ_FLOPPY_ERR]    = -1,
 655         [DEC_IRQ_ISDN_ERR]      = -1,
 656         [DEC_IRQ_ISDN_RXDMA]    = -1,
 657         [DEC_IRQ_ISDN_TXDMA]    = -1,
 658         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 659         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 660         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 661         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 662         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 663         [DEC_IRQ_AB_RXERR]      = -1,
 664         [DEC_IRQ_AB_RXDMA]      = -1,
 665         [DEC_IRQ_AB_TXERR]      = -1,
 666         [DEC_IRQ_AB_TXDMA]      = -1,
 667         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 668         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 669         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 670         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 671 };
 672
 673 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
 674         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
 675                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
 676         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
 677                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
 678         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
 679                 { .p = kn03_io_int } },
 680         { { .i = DEC_CPU_IRQ_ALL },
 681                 { .p = cpu_all_int } },
 682 };
 683
 684 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
 685         { { .i = IO_IRQ_DMA },
 686                 { .p = asic_dma_int } },
 687         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
 688                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
 689         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
 690                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
 691         { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
 692                 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
 693         { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
 694                 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
 695         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
 696                 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
 697         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
 698                 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
 699         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
 700                 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
 701         { { .i = IO_IRQ_ALL },
 702                 { .p = asic_all_int } },
 703 };
 704
 705 static void __init dec_init_kn03(void)
 706 {
 707         /* IRQ routing. */
 708         memcpy(&dec_interrupt, &kn03_interrupt,
 709                 sizeof(kn03_interrupt));
 710
 711         /* CPU IRQ priorities. */
 712         memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
 713                 sizeof(kn03_cpu_mask_nr_tbl));
 714
 715         /* I/O ASIC IRQ priorities. */
 716         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
 717                 sizeof(kn03_asic_mask_nr_tbl));
 718
 719         mips_cpu_irq_init();
 720         init_ioasic_irqs(IO_IRQ_BASE);
 721
 722 }                               /* dec_init_kn03 */
 723
 724
 725 void __init arch_init_irq(void)
 726 {
 727         switch (mips_machtype) {
 728         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 729                 dec_init_kn01();
 730                 break;
 731         case MACH_DS5100:       /* DS5100 MIPSmate */
 732                 dec_init_kn230();
 733                 break;
 734         case MACH_DS5000_200:   /* DS5000/200 3max */
 735                 dec_init_kn02();
 736                 break;
 737         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 738                 dec_init_kn02ba();
 739                 break;
 740         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 741         case MACH_DS5900:       /* DS5900 bigmax */
 742                 dec_init_kn03();
 743                 break;
 744         case MACH_DS5000_XX:    /* Personal DS5000/xx */
 745                 dec_init_kn02ca();
 746                 break;
 747         case MACH_DS5800:       /* DS5800 Isis */
 748                 panic("Don't know how to set this up!");
 749                 break;
 750         case MACH_DS5400:       /* DS5400 MIPSfair */
 751                 panic("Don't know how to set this up!");
 752                 break;
 753         case MACH_DS5500:       /* DS5500 MIPSfair-2 */
 754                 panic("Don't know how to set this up!");
 755                 break;
 756         }
 757
 758         /* Free the FPU interrupt if the exception is present. */
 759         if (!cpu_has_nofpuex) {
 760                 cpu_fpu_mask = 0;
 761                 dec_interrupt[DEC_IRQ_FPU] = -1;
 762         }
 763         /* Free the halt interrupt unused on R4k systems.  */
 764         if (current_cpu_type() == CPU_R4000SC ||
 765             current_cpu_type() == CPU_R4400SC)
 766                 dec_interrupt[DEC_IRQ_HALT] = -1;
 767
 768         /* Register board interrupts: FPU and cascade. */
 769         if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) &&
 770             dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
 771                 struct irq_desc *desc_fpu;
 772                 int irq_fpu;
 773
 774                 irq_fpu = dec_interrupt[DEC_IRQ_FPU];
 775                 setup_irq(irq_fpu, &fpuirq);
 776                 desc_fpu = irq_to_desc(irq_fpu);
 777                 fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
 778         }
 779         if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
 780                 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
 781
 782         /* Register the bus error interrupt. */
 783         if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
 784                 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
 785
 786         /* Register the HALT interrupt. */
 787         if (dec_interrupt[DEC_IRQ_HALT] >= 0)
 788                 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
 789 }
 790
 791 asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
 792 {
 793         do_IRQ(irq);
 794         return 0;
 795 }