arch/mips/cavium-octeon/octeon-platform.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2017 Cavium, Inc.
   7  * Copyright (C) 2008 Wind River Systems
   8  */
   9
  10 #include <linux/etherdevice.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/of_fdt.h>
  13 #include <linux/libfdt.h>
  14
  15 #include <asm/octeon/octeon.h>
  16 #include <asm/octeon/cvmx-helper-board.h>
  17
  18 #ifdef CONFIG_USB
  19 #include <linux/usb/ehci_def.h>
  20 #include <linux/usb/ehci_pdriver.h>
  21 #include <linux/usb/ohci_pdriver.h>
  22 #include <asm/octeon/cvmx-uctlx-defs.h>
  23
  24 #define CVMX_UAHCX_EHCI_USBCMD  (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
  25 #define CVMX_UAHCX_OHCI_USBCMD  (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
  26
  27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
  28
  29 static int octeon2_usb_clock_start_cnt;
  30
  31 static int __init octeon2_usb_reset(void)
  32 {
  33         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
  34         u32 ucmd;
  35
  36         if (!OCTEON_IS_OCTEON2())
  37                 return 0;
  38
  39         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
  40         if (clk_rst_ctl.s.hrst) {
  41                 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
  42                 ucmd &= ~CMD_RUN;
  43                 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
  44                 mdelay(2);
  45                 ucmd |= CMD_RESET;
  46                 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
  47                 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
  48                 ucmd |= CMD_RUN;
  49                 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
  50         }
  51
  52         return 0;
  53 }
  54 arch_initcall(octeon2_usb_reset);
  55
  56 static void octeon2_usb_clocks_start(struct device *dev)
  57 {
  58         u64 div;
  59         union cvmx_uctlx_if_ena if_ena;
  60         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
  61         union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
  62         int i;
  63         unsigned long io_clk_64_to_ns;
  64         u32 clock_rate = 12000000;
  65         bool is_crystal_clock = false;
  66
  67
  68         mutex_lock(&octeon2_usb_clocks_mutex);
  69
  70         octeon2_usb_clock_start_cnt++;
  71         if (octeon2_usb_clock_start_cnt != 1)
  72                 goto exit;
  73
  74         io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
  75
  76         if (dev->of_node) {
  77                 struct device_node *uctl_node;
  78                 const char *clock_type;
  79
  80                 uctl_node = of_get_parent(dev->of_node);
  81                 if (!uctl_node) {
  82                         dev_err(dev, "No UCTL device node\n");
  83                         goto exit;
  84                 }
  85                 i = of_property_read_u32(uctl_node,
  86                                          "refclk-frequency", &clock_rate);
  87                 if (i) {
  88                         dev_err(dev, "No UCTL \"refclk-frequency\"\n");
  89                         goto exit;
  90                 }
  91                 i = of_property_read_string(uctl_node,
  92                                             "refclk-type", &clock_type);
  93
  94                 if (!i && strcmp("crystal", clock_type) == 0)
  95                         is_crystal_clock = true;
  96         }
  97
  98         /*
  99          * Step 1: Wait for voltages stable.  That surely happened
 100          * before starting the kernel.
 101          *
 102          * Step 2: Enable  SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
 103          */
 104         if_ena.u64 = 0;
 105         if_ena.s.en = 1;
 106         cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
 107
 108         for (i = 0; i <= 1; i++) {
 109                 port_ctl_status.u64 =
 110                         cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
 111                 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
 112                 port_ctl_status.s.txvreftune = 15;
 113                 port_ctl_status.s.txrisetune = 1;
 114                 port_ctl_status.s.txpreemphasistune = 1;
 115                 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
 116                                port_ctl_status.u64);
 117         }
 118
 119         /* Step 3: Configure the reference clock, PHY, and HCLK */
 120         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
 121
 122         /*
 123          * If the UCTL looks like it has already been started, skip
 124          * the initialization, otherwise bus errors are obtained.
 125          */
 126         if (clk_rst_ctl.s.hrst)
 127                 goto end_clock;
 128         /* 3a */
 129         clk_rst_ctl.s.p_por = 1;
 130         clk_rst_ctl.s.hrst = 0;
 131         clk_rst_ctl.s.p_prst = 0;
 132         clk_rst_ctl.s.h_clkdiv_rst = 0;
 133         clk_rst_ctl.s.o_clkdiv_rst = 0;
 134         clk_rst_ctl.s.h_clkdiv_en = 0;
 135         clk_rst_ctl.s.o_clkdiv_en = 0;
 136         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 137
 138         /* 3b */
 139         clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
 140         switch (clock_rate) {
 141         default:
 142                 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
 143                         clock_rate);
 144                 /* Fall through */
 145         case 12000000:
 146                 clk_rst_ctl.s.p_refclk_div = 0;
 147                 break;
 148         case 24000000:
 149                 clk_rst_ctl.s.p_refclk_div = 1;
 150                 break;
 151         case 48000000:
 152                 clk_rst_ctl.s.p_refclk_div = 2;
 153                 break;
 154         }
 155         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 156
 157         /* 3c */
 158         div = octeon_get_io_clock_rate() / 130000000ull;
 159
 160         switch (div) {
 161         case 0:
 162                 div = 1;
 163                 break;
 164         case 1:
 165         case 2:
 166         case 3:
 167         case 4:
 168                 break;
 169         case 5:
 170                 div = 4;
 171                 break;
 172         case 6:
 173         case 7:
 174                 div = 6;
 175                 break;
 176         case 8:
 177         case 9:
 178         case 10:
 179         case 11:
 180                 div = 8;
 181                 break;
 182         default:
 183                 div = 12;
 184                 break;
 185         }
 186         clk_rst_ctl.s.h_div = div;
 187         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 188         /* Read it back, */
 189         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
 190         clk_rst_ctl.s.h_clkdiv_en = 1;
 191         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 192         /* 3d */
 193         clk_rst_ctl.s.h_clkdiv_rst = 1;
 194         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 195
 196         /* 3e: delay 64 io clocks */
 197         ndelay(io_clk_64_to_ns);
 198
 199         /*
 200          * Step 4: Program the power-on reset field in the UCTL
 201          * clock-reset-control register.
 202          */
 203         clk_rst_ctl.s.p_por = 0;
 204         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 205
 206         /* Step 5:    Wait 3 ms for the PHY clock to start. */
 207         mdelay(3);
 208
 209         /* Steps 6..9 for ATE only, are skipped. */
 210
 211         /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
 212         /* 10a */
 213         clk_rst_ctl.s.o_clkdiv_rst = 1;
 214         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 215
 216         /* 10b */
 217         clk_rst_ctl.s.o_clkdiv_en = 1;
 218         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 219
 220         /* 10c */
 221         ndelay(io_clk_64_to_ns);
 222
 223         /*
 224          * Step 11: Program the PHY reset field:
 225          * UCTL0_CLK_RST_CTL[P_PRST] = 1
 226          */
 227         clk_rst_ctl.s.p_prst = 1;
 228         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 229
 230         /* Step 11b */
 231         udelay(1);
 232
 233         /* Step 11c */
 234         clk_rst_ctl.s.p_prst = 0;
 235         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 236
 237         /* Step 11d */
 238         mdelay(1);
 239
 240         /* Step 11e */
 241         clk_rst_ctl.s.p_prst = 1;
 242         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 243
 244         /* Step 12: Wait 1 uS. */
 245         udelay(1);
 246
 247         /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
 248         clk_rst_ctl.s.hrst = 1;
 249         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 250
 251 end_clock:
 252         /* Set uSOF cycle period to 60,000 bits. */
 253         cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
 254
 255 exit:
 256         mutex_unlock(&octeon2_usb_clocks_mutex);
 257 }
 258
 259 static void octeon2_usb_clocks_stop(void)
 260 {
 261         mutex_lock(&octeon2_usb_clocks_mutex);
 262         octeon2_usb_clock_start_cnt--;
 263         mutex_unlock(&octeon2_usb_clocks_mutex);
 264 }
 265
 266 static int octeon_ehci_power_on(struct platform_device *pdev)
 267 {
 268         octeon2_usb_clocks_start(&pdev->dev);
 269         return 0;
 270 }
 271
 272 static void octeon_ehci_power_off(struct platform_device *pdev)
 273 {
 274         octeon2_usb_clocks_stop();
 275 }
 276
 277 static struct usb_ehci_pdata octeon_ehci_pdata = {
 278         /* Octeon EHCI matches CPU endianness. */
 279 #ifdef __BIG_ENDIAN
 280         .big_endian_mmio        = 1,
 281 #endif
 282         /*
 283          * We can DMA from anywhere. But the descriptors must be in
 284          * the lower 4GB.
 285          */
 286         .dma_mask_64    = 0,
 287         .power_on       = octeon_ehci_power_on,
 288         .power_off      = octeon_ehci_power_off,
 289 };
 290
 291 static void __init octeon_ehci_hw_start(struct device *dev)
 292 {
 293         union cvmx_uctlx_ehci_ctl ehci_ctl;
 294
 295         octeon2_usb_clocks_start(dev);
 296
 297         ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
 298         /* Use 64-bit addressing. */
 299         ehci_ctl.s.ehci_64b_addr_en = 1;
 300         ehci_ctl.s.l2c_addr_msb = 0;
 301 #ifdef __BIG_ENDIAN
 302         ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
 303         ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
 304 #else
 305         ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
 306         ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
 307         ehci_ctl.s.inv_reg_a2 = 1;
 308 #endif
 309         cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
 310
 311         octeon2_usb_clocks_stop();
 312 }
 313
 314 static int __init octeon_ehci_device_init(void)
 315 {
 316         struct platform_device *pd;
 317         struct device_node *ehci_node;
 318         int ret = 0;
 319
 320         ehci_node = of_find_node_by_name(NULL, "ehci");
 321         if (!ehci_node)
 322                 return 0;
 323
 324         pd = of_find_device_by_node(ehci_node);
 325         of_node_put(ehci_node);
 326         if (!pd)
 327                 return 0;
 328
 329         pd->dev.platform_data = &octeon_ehci_pdata;
 330         octeon_ehci_hw_start(&pd->dev);
 331         put_device(&pd->dev);
 332
 333         return ret;
 334 }
 335 device_initcall(octeon_ehci_device_init);
 336
 337 static int octeon_ohci_power_on(struct platform_device *pdev)
 338 {
 339         octeon2_usb_clocks_start(&pdev->dev);
 340         return 0;
 341 }
 342
 343 static void octeon_ohci_power_off(struct platform_device *pdev)
 344 {
 345         octeon2_usb_clocks_stop();
 346 }
 347
 348 static struct usb_ohci_pdata octeon_ohci_pdata = {
 349         /* Octeon OHCI matches CPU endianness. */
 350 #ifdef __BIG_ENDIAN
 351         .big_endian_mmio        = 1,
 352 #endif
 353         .power_on       = octeon_ohci_power_on,
 354         .power_off      = octeon_ohci_power_off,
 355 };
 356
 357 static void __init octeon_ohci_hw_start(struct device *dev)
 358 {
 359         union cvmx_uctlx_ohci_ctl ohci_ctl;
 360
 361         octeon2_usb_clocks_start(dev);
 362
 363         ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
 364         ohci_ctl.s.l2c_addr_msb = 0;
 365 #ifdef __BIG_ENDIAN
 366         ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
 367         ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
 368 #else
 369         ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
 370         ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
 371         ohci_ctl.s.inv_reg_a2 = 1;
 372 #endif
 373         cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
 374
 375         octeon2_usb_clocks_stop();
 376 }
 377
 378 static int __init octeon_ohci_device_init(void)
 379 {
 380         struct platform_device *pd;
 381         struct device_node *ohci_node;
 382         int ret = 0;
 383
 384         ohci_node = of_find_node_by_name(NULL, "ohci");
 385         if (!ohci_node)
 386                 return 0;
 387
 388         pd = of_find_device_by_node(ohci_node);
 389         of_node_put(ohci_node);
 390         if (!pd)
 391                 return 0;
 392
 393         pd->dev.platform_data = &octeon_ohci_pdata;
 394         octeon_ohci_hw_start(&pd->dev);
 395         put_device(&pd->dev);
 396
 397         return ret;
 398 }
 399 device_initcall(octeon_ohci_device_init);
 400
 401 #endif /* CONFIG_USB */
 402
 403 /* Octeon Random Number Generator.  */
 404 static int __init octeon_rng_device_init(void)
 405 {
 406         struct platform_device *pd;
 407         int ret = 0;
 408
 409         struct resource rng_resources[] = {
 410                 {
 411                         .flags  = IORESOURCE_MEM,
 412                         .start  = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
 413                         .end    = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
 414                 }, {
 415                         .flags  = IORESOURCE_MEM,
 416                         .start  = cvmx_build_io_address(8, 0),
 417                         .end    = cvmx_build_io_address(8, 0) + 0x7
 418                 }
 419         };
 420
 421         pd = platform_device_alloc("octeon_rng", -1);
 422         if (!pd) {
 423                 ret = -ENOMEM;
 424                 goto out;
 425         }
 426
 427         ret = platform_device_add_resources(pd, rng_resources,
 428                                             ARRAY_SIZE(rng_resources));
 429         if (ret)
 430                 goto fail;
 431
 432         ret = platform_device_add(pd);
 433         if (ret)
 434                 goto fail;
 435
 436         return ret;
 437 fail:
 438         platform_device_put(pd);
 439
 440 out:
 441         return ret;
 442 }
 443 device_initcall(octeon_rng_device_init);
 444
 445 const struct of_device_id octeon_ids[] __initconst = {
 446         { .compatible = "simple-bus", },
 447         { .compatible = "cavium,octeon-6335-uctl", },
 448         { .compatible = "cavium,octeon-5750-usbn", },
 449         { .compatible = "cavium,octeon-3860-bootbus", },
 450         { .compatible = "cavium,mdio-mux", },
 451         { .compatible = "gpio-leds", },
 452         { .compatible = "cavium,octeon-7130-usb-uctl", },
 453         {},
 454 };
 455
 456 static bool __init octeon_has_88e1145(void)
 457 {
 458         return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
 459                !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
 460                !OCTEON_IS_MODEL(OCTEON_CN56XX);
 461 }
 462
 463 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
 464 {
 465         const __be32 *phy_handle;
 466         const __be32 *alt_phy_handle;
 467         const __be32 *reg;
 468         u32 phandle;
 469         int phy;
 470         int alt_phy;
 471         const char *p;
 472         int current_len;
 473         char new_name[20];
 474
 475         phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
 476         if (!phy_handle)
 477                 return;
 478
 479         phandle = be32_to_cpup(phy_handle);
 480         phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
 481
 482         alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
 483         if (alt_phy_handle) {
 484                 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
 485
 486                 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
 487         } else {
 488                 alt_phy = -1;
 489         }
 490
 491         if (phy_addr < 0 || phy < 0) {
 492                 /* Delete the PHY things */
 493                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
 494                 /* This one may fail */
 495                 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
 496                 if (phy >= 0)
 497                         fdt_nop_node(initial_boot_params, phy);
 498                 if (alt_phy >= 0)
 499                         fdt_nop_node(initial_boot_params, alt_phy);
 500                 return;
 501         }
 502
 503         if (phy_addr >= 256 && alt_phy > 0) {
 504                 const struct fdt_property *phy_prop;
 505                 struct fdt_property *alt_prop;
 506                 fdt32_t phy_handle_name;
 507
 508                 /* Use the alt phy node instead.*/
 509                 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
 510                 phy_handle_name = phy_prop->nameoff;
 511                 fdt_nop_node(initial_boot_params, phy);
 512                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
 513                 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
 514                 alt_prop->nameoff = phy_handle_name;
 515                 phy = alt_phy;
 516         }
 517
 518         phy_addr &= 0xff;
 519
 520         if (octeon_has_88e1145()) {
 521                 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
 522                 memset(new_name, 0, sizeof(new_name));
 523                 strcpy(new_name, "marvell,88e1145");
 524                 p = fdt_getprop(initial_boot_params, phy, "compatible",
 525                                 &current_len);
 526                 if (p && current_len >= strlen(new_name))
 527                         fdt_setprop_inplace(initial_boot_params, phy,
 528                                         "compatible", new_name, current_len);
 529         }
 530
 531         reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
 532         if (phy_addr == be32_to_cpup(reg))
 533                 return;
 534
 535         fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
 536
 537         snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
 538
 539         p = fdt_get_name(initial_boot_params, phy, &current_len);
 540         if (p && current_len == strlen(new_name))
 541                 fdt_set_name(initial_boot_params, phy, new_name);
 542         else
 543                 pr_err("Error: could not rename ethernet phy: <%s>", p);
 544 }
 545
 546 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
 547 {
 548         const u8 *old_mac;
 549         int old_len;
 550         u8 new_mac[6];
 551         u64 mac = *pmac;
 552         int r;
 553
 554         old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
 555                               &old_len);
 556         if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
 557                 return;
 558
 559         new_mac[0] = (mac >> 40) & 0xff;
 560         new_mac[1] = (mac >> 32) & 0xff;
 561         new_mac[2] = (mac >> 24) & 0xff;
 562         new_mac[3] = (mac >> 16) & 0xff;
 563         new_mac[4] = (mac >> 8) & 0xff;
 564         new_mac[5] = mac & 0xff;
 565
 566         r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
 567                                 new_mac, sizeof(new_mac));
 568
 569         if (r) {
 570                 pr_err("Setting \"local-mac-address\" failed %d", r);
 571                 return;
 572         }
 573         *pmac = mac + 1;
 574 }
 575
 576 static void __init octeon_fdt_rm_ethernet(int node)
 577 {
 578         const __be32 *phy_handle;
 579
 580         phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
 581         if (phy_handle) {
 582                 u32 ph = be32_to_cpup(phy_handle);
 583                 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
 584
 585                 if (p >= 0)
 586                         fdt_nop_node(initial_boot_params, p);
 587         }
 588         fdt_nop_node(initial_boot_params, node);
 589 }
 590
 591 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
 592 {
 593         char name_buffer[20];
 594         int eth;
 595         int phy_addr;
 596         int ipd_port;
 597
 598         snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
 599         eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
 600         if (eth < 0)
 601                 return;
 602         if (p > max) {
 603                 pr_debug("Deleting port %x:%x\n", i, p);
 604                 octeon_fdt_rm_ethernet(eth);
 605                 return;
 606         }
 607         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 608                 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
 609         else
 610                 ipd_port = 16 * i + p;
 611
 612         phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
 613         octeon_fdt_set_phy(eth, phy_addr);
 614 }
 615
 616 static void __init octeon_fdt_pip_iface(int pip, int idx)
 617 {
 618         char name_buffer[20];
 619         int iface;
 620         int p;
 621         int count = 0;
 622
 623         snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
 624         iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
 625         if (iface < 0)
 626                 return;
 627
 628         if (cvmx_helper_interface_enumerate(idx) == 0)
 629                 count = cvmx_helper_ports_on_interface(idx);
 630
 631         for (p = 0; p < 16; p++)
 632                 octeon_fdt_pip_port(iface, idx, p, count - 1);
 633 }
 634
 635 void __init octeon_fill_mac_addresses(void)
 636 {
 637         const char *alias_prop;
 638         char name_buffer[20];
 639         u64 mac_addr_base;
 640         int aliases;
 641         int pip;
 642         int i;
 643
 644         aliases = fdt_path_offset(initial_boot_params, "/aliases");
 645         if (aliases < 0)
 646                 return;
 647
 648         mac_addr_base =
 649                 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
 650                 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
 651                 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
 652                 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
 653                 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
 654                  (octeon_bootinfo->mac_addr_base[5] & 0xffull);
 655
 656         for (i = 0; i < 2; i++) {
 657                 int mgmt;
 658
 659                 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
 660                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 661                                          name_buffer, NULL);
 662                 if (!alias_prop)
 663                         continue;
 664                 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
 665                 if (mgmt < 0)
 666                         continue;
 667                 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
 668         }
 669
 670         alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
 671         if (!alias_prop)
 672                 return;
 673
 674         pip = fdt_path_offset(initial_boot_params, alias_prop);
 675         if (pip < 0)
 676                 return;
 677
 678         for (i = 0; i <= 4; i++) {
 679                 int iface;
 680                 int p;
 681
 682                 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
 683                 iface = fdt_subnode_offset(initial_boot_params, pip,
 684                                            name_buffer);
 685                 if (iface < 0)
 686                         continue;
 687                 for (p = 0; p < 16; p++) {
 688                         int eth;
 689
 690                         snprintf(name_buffer, sizeof(name_buffer),
 691                                  "ethernet@%x", p);
 692                         eth = fdt_subnode_offset(initial_boot_params, iface,
 693                                                  name_buffer);
 694                         if (eth < 0)
 695                                 continue;
 696                         octeon_fdt_set_mac_addr(eth, &mac_addr_base);
 697                 }
 698         }
 699 }
 700
 701 int __init octeon_prune_device_tree(void)
 702 {
 703         int i, max_port, uart_mask;
 704         const char *pip_path;
 705         const char *alias_prop;
 706         char name_buffer[20];
 707         int aliases;
 708
 709         if (fdt_check_header(initial_boot_params))
 710                 panic("Corrupt Device Tree.");
 711
 712         WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
 713              "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
 714              cvmx_board_type_to_string(octeon_bootinfo->board_type));
 715
 716         aliases = fdt_path_offset(initial_boot_params, "/aliases");
 717         if (aliases < 0) {
 718                 pr_err("Error: No /aliases node in device tree.");
 719                 return -EINVAL;
 720         }
 721
 722         if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
 723                 max_port = 2;
 724         else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
 725                 max_port = 1;
 726         else
 727                 max_port = 0;
 728
 729         if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
 730                 max_port = 0;
 731
 732         for (i = 0; i < 2; i++) {
 733                 int mgmt;
 734
 735                 snprintf(name_buffer, sizeof(name_buffer),
 736                          "mix%d", i);
 737                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 738                                         name_buffer, NULL);
 739                 if (alias_prop) {
 740                         mgmt = fdt_path_offset(initial_boot_params, alias_prop);
 741                         if (mgmt < 0)
 742                                 continue;
 743                         if (i >= max_port) {
 744                                 pr_debug("Deleting mix%d\n", i);
 745                                 octeon_fdt_rm_ethernet(mgmt);
 746                                 fdt_nop_property(initial_boot_params, aliases,
 747                                                  name_buffer);
 748                         } else {
 749                                 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
 750
 751                                 octeon_fdt_set_phy(mgmt, phy_addr);
 752                         }
 753                 }
 754         }
 755
 756         pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
 757         if (pip_path) {
 758                 int pip = fdt_path_offset(initial_boot_params, pip_path);
 759
 760                 if (pip  >= 0)
 761                         for (i = 0; i <= 4; i++)
 762                                 octeon_fdt_pip_iface(pip, i);
 763         }
 764
 765         /* I2C */
 766         if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
 767             OCTEON_IS_MODEL(OCTEON_CN63XX) ||
 768             OCTEON_IS_MODEL(OCTEON_CN68XX) ||
 769             OCTEON_IS_MODEL(OCTEON_CN56XX))
 770                 max_port = 2;
 771         else
 772                 max_port = 1;
 773
 774         for (i = 0; i < 2; i++) {
 775                 int i2c;
 776
 777                 snprintf(name_buffer, sizeof(name_buffer),
 778                          "twsi%d", i);
 779                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 780                                         name_buffer, NULL);
 781
 782                 if (alias_prop) {
 783                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
 784                         if (i2c < 0)
 785                                 continue;
 786                         if (i >= max_port) {
 787                                 pr_debug("Deleting twsi%d\n", i);
 788                                 fdt_nop_node(initial_boot_params, i2c);
 789                                 fdt_nop_property(initial_boot_params, aliases,
 790                                                  name_buffer);
 791                         }
 792                 }
 793         }
 794
 795         /* SMI/MDIO */
 796         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 797                 max_port = 4;
 798         else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
 799                  OCTEON_IS_MODEL(OCTEON_CN63XX) ||
 800                  OCTEON_IS_MODEL(OCTEON_CN56XX))
 801                 max_port = 2;
 802         else
 803                 max_port = 1;
 804
 805         for (i = 0; i < 2; i++) {
 806                 int i2c;
 807
 808                 snprintf(name_buffer, sizeof(name_buffer),
 809                          "smi%d", i);
 810                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 811                                         name_buffer, NULL);
 812                 if (alias_prop) {
 813                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
 814                         if (i2c < 0)
 815                                 continue;
 816                         if (i >= max_port) {
 817                                 pr_debug("Deleting smi%d\n", i);
 818                                 fdt_nop_node(initial_boot_params, i2c);
 819                                 fdt_nop_property(initial_boot_params, aliases,
 820                                                  name_buffer);
 821                         }
 822                 }
 823         }
 824
 825         /* Serial */
 826         uart_mask = 3;
 827
 828         /* Right now CN52XX is the only chip with a third uart */
 829         if (OCTEON_IS_MODEL(OCTEON_CN52XX))
 830                 uart_mask |= 4; /* uart2 */
 831
 832         for (i = 0; i < 3; i++) {
 833                 int uart;
 834
 835                 snprintf(name_buffer, sizeof(name_buffer),
 836                          "uart%d", i);
 837                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 838                                         name_buffer, NULL);
 839
 840                 if (alias_prop) {
 841                         uart = fdt_path_offset(initial_boot_params, alias_prop);
 842                         if (uart_mask & (1 << i)) {
 843                                 __be32 f;
 844
 845                                 f = cpu_to_be32(octeon_get_io_clock_rate());
 846                                 fdt_setprop_inplace(initial_boot_params,
 847                                                     uart, "clock-frequency",
 848                                                     &f, sizeof(f));
 849                                 continue;
 850                         }
 851                         pr_debug("Deleting uart%d\n", i);
 852                         fdt_nop_node(initial_boot_params, uart);
 853                         fdt_nop_property(initial_boot_params, aliases,
 854                                          name_buffer);
 855                 }
 856         }
 857
 858         /* Compact Flash */
 859         alias_prop = fdt_getprop(initial_boot_params, aliases,
 860                                  "cf0", NULL);
 861         if (alias_prop) {
 862                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
 863                 unsigned long base_ptr, region_base, region_size;
 864                 unsigned long region1_base = 0;
 865                 unsigned long region1_size = 0;
 866                 int cs, bootbus;
 867                 bool is_16bit = false;
 868                 bool is_true_ide = false;
 869                 __be32 new_reg[6];
 870                 __be32 *ranges;
 871                 int len;
 872
 873                 int cf = fdt_path_offset(initial_boot_params, alias_prop);
 874
 875                 base_ptr = 0;
 876                 if (octeon_bootinfo->major_version == 1
 877                         && octeon_bootinfo->minor_version >= 1) {
 878                         if (octeon_bootinfo->compact_flash_common_base_addr)
 879                                 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
 880                 } else {
 881                         base_ptr = 0x1d000800;
 882                 }
 883
 884                 if (!base_ptr)
 885                         goto no_cf;
 886
 887                 /* Find CS0 region. */
 888                 for (cs = 0; cs < 8; cs++) {
 889                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 890                         region_base = mio_boot_reg_cfg.s.base << 16;
 891                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 892                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
 893                                 && base_ptr < region_base + region_size) {
 894                                 is_16bit = mio_boot_reg_cfg.s.width;
 895                                 break;
 896                         }
 897                 }
 898                 if (cs >= 7) {
 899                         /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
 900                         goto no_cf;
 901                 }
 902
 903                 if (!(base_ptr & 0xfffful)) {
 904                         /*
 905                          * Boot loader signals availability of DMA (true_ide
 906                          * mode) by setting low order bits of base_ptr to
 907                          * zero.
 908                          */
 909
 910                         /* Asume that CS1 immediately follows. */
 911                         mio_boot_reg_cfg.u64 =
 912                                 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
 913                         region1_base = mio_boot_reg_cfg.s.base << 16;
 914                         region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 915                         if (!mio_boot_reg_cfg.s.en)
 916                                 goto no_cf;
 917                         is_true_ide = true;
 918
 919                 } else {
 920                         fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
 921                         fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
 922                         if (!is_16bit) {
 923                                 __be32 width = cpu_to_be32(8);
 924
 925                                 fdt_setprop_inplace(initial_boot_params, cf,
 926                                                 "cavium,bus-width", &width, sizeof(width));
 927                         }
 928                 }
 929                 new_reg[0] = cpu_to_be32(cs);
 930                 new_reg[1] = cpu_to_be32(0);
 931                 new_reg[2] = cpu_to_be32(0x10000);
 932                 new_reg[3] = cpu_to_be32(cs + 1);
 933                 new_reg[4] = cpu_to_be32(0);
 934                 new_reg[5] = cpu_to_be32(0x10000);
 935                 fdt_setprop_inplace(initial_boot_params, cf,
 936                                     "reg",  new_reg, sizeof(new_reg));
 937
 938                 bootbus = fdt_parent_offset(initial_boot_params, cf);
 939                 if (bootbus < 0)
 940                         goto no_cf;
 941                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
 942                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
 943                         goto no_cf;
 944
 945                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
 946                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
 947                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
 948                 if (is_true_ide) {
 949                         cs++;
 950                         ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
 951                         ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
 952                         ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
 953                 }
 954                 goto end_cf;
 955 no_cf:
 956                 fdt_nop_node(initial_boot_params, cf);
 957
 958 end_cf:
 959                 ;
 960         }
 961
 962         /* 8 char LED */
 963         alias_prop = fdt_getprop(initial_boot_params, aliases,
 964                                  "led0", NULL);
 965         if (alias_prop) {
 966                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
 967                 unsigned long base_ptr, region_base, region_size;
 968                 int cs, bootbus;
 969                 __be32 new_reg[6];
 970                 __be32 *ranges;
 971                 int len;
 972                 int led = fdt_path_offset(initial_boot_params, alias_prop);
 973
 974                 base_ptr = octeon_bootinfo->led_display_base_addr;
 975                 if (base_ptr == 0)
 976                         goto no_led;
 977                 /* Find CS0 region. */
 978                 for (cs = 0; cs < 8; cs++) {
 979                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 980                         region_base = mio_boot_reg_cfg.s.base << 16;
 981                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 982                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
 983                                 && base_ptr < region_base + region_size)
 984                                 break;
 985                 }
 986
 987                 if (cs > 7)
 988                         goto no_led;
 989
 990                 new_reg[0] = cpu_to_be32(cs);
 991                 new_reg[1] = cpu_to_be32(0x20);
 992                 new_reg[2] = cpu_to_be32(0x20);
 993                 new_reg[3] = cpu_to_be32(cs);
 994                 new_reg[4] = cpu_to_be32(0);
 995                 new_reg[5] = cpu_to_be32(0x20);
 996                 fdt_setprop_inplace(initial_boot_params, led,
 997                                     "reg",  new_reg, sizeof(new_reg));
 998
 999                 bootbus = fdt_parent_offset(initial_boot_params, led);
1000                 if (bootbus < 0)
1001                         goto no_led;
1002                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1003                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
1004                         goto no_led;
1005
1006                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1007                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1008                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1009                 goto end_led;
1010
1011 no_led:
1012                 fdt_nop_node(initial_boot_params, led);
1013 end_led:
1014                 ;
1015         }
1016
1017 #ifdef CONFIG_USB
1018         /* OHCI/UHCI USB */
1019         alias_prop = fdt_getprop(initial_boot_params, aliases,
1020                                  "uctl", NULL);
1021         if (alias_prop) {
1022                 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1023
1024                 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1025                                   octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1026                         pr_debug("Deleting uctl\n");
1027                         fdt_nop_node(initial_boot_params, uctl);
1028                         fdt_nop_property(initial_boot_params, aliases, "uctl");
1029                 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1030                            octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1031                         /* Missing "refclk-type" defaults to crystal. */
1032                         fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1033                 }
1034         }
1035
1036         /* DWC2 USB */
1037         alias_prop = fdt_getprop(initial_boot_params, aliases,
1038                                  "usbn", NULL);
1039         if (alias_prop) {
1040                 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1041
1042                 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1043                                   !octeon_has_feature(OCTEON_FEATURE_USB))) {
1044                         pr_debug("Deleting usbn\n");
1045                         fdt_nop_node(initial_boot_params, usbn);
1046                         fdt_nop_property(initial_boot_params, aliases, "usbn");
1047                 } else  {
1048                         __be32 new_f[1];
1049                         enum cvmx_helper_board_usb_clock_types c;
1050
1051                         c = __cvmx_helper_board_usb_get_clock_type();
1052                         switch (c) {
1053                         case USB_CLOCK_TYPE_REF_48:
1054                                 new_f[0] = cpu_to_be32(48000000);
1055                                 fdt_setprop_inplace(initial_boot_params, usbn,
1056                                                     "refclk-frequency",  new_f, sizeof(new_f));
1057                                 /* Fall through ...*/
1058                         case USB_CLOCK_TYPE_REF_12:
1059                                 /* Missing "refclk-type" defaults to external. */
1060                                 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1061                                 break;
1062                         default:
1063                                 break;
1064                         }
1065                 }
1066         }
1067 #endif
1068
1069         return 0;
1070 }
1071
1072 static int __init octeon_publish_devices(void)
1073 {
1074         return of_platform_bus_probe(NULL, octeon_ids, NULL);
1075 }
1076 arch_initcall(octeon_publish_devices);