GNU Linux-libre 4.19.286-gnu1
[releases.git] / arch / mips / cavium-octeon / octeon-platform.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2017 Cavium, Inc.
7  * Copyright (C) 2008 Wind River Systems
8  */
9
10 #include <linux/etherdevice.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_fdt.h>
13 #include <linux/libfdt.h>
14
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-helper-board.h>
17
18 #ifdef CONFIG_USB
19 #include <linux/usb/ehci_def.h>
20 #include <linux/usb/ehci_pdriver.h>
21 #include <linux/usb/ohci_pdriver.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
23
24 #define CVMX_UAHCX_EHCI_USBCMD  (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD  (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26
27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
28
29 static int octeon2_usb_clock_start_cnt;
30
31 static int __init octeon2_usb_reset(void)
32 {
33         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
34         u32 ucmd;
35
36         if (!OCTEON_IS_OCTEON2())
37                 return 0;
38
39         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
40         if (clk_rst_ctl.s.hrst) {
41                 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
42                 ucmd &= ~CMD_RUN;
43                 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
44                 mdelay(2);
45                 ucmd |= CMD_RESET;
46                 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
47                 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
48                 ucmd |= CMD_RUN;
49                 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
50         }
51
52         return 0;
53 }
54 arch_initcall(octeon2_usb_reset);
55
56 static void octeon2_usb_clocks_start(struct device *dev)
57 {
58         u64 div;
59         union cvmx_uctlx_if_ena if_ena;
60         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
61         union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
62         int i;
63         unsigned long io_clk_64_to_ns;
64         u32 clock_rate = 12000000;
65         bool is_crystal_clock = false;
66
67
68         mutex_lock(&octeon2_usb_clocks_mutex);
69
70         octeon2_usb_clock_start_cnt++;
71         if (octeon2_usb_clock_start_cnt != 1)
72                 goto exit;
73
74         io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
75
76         if (dev->of_node) {
77                 struct device_node *uctl_node;
78                 const char *clock_type;
79
80                 uctl_node = of_get_parent(dev->of_node);
81                 if (!uctl_node) {
82                         dev_err(dev, "No UCTL device node\n");
83                         goto exit;
84                 }
85                 i = of_property_read_u32(uctl_node,
86                                          "refclk-frequency", &clock_rate);
87                 if (i) {
88                         dev_err(dev, "No UCTL \"refclk-frequency\"\n");
89                         of_node_put(uctl_node);
90                         goto exit;
91                 }
92                 i = of_property_read_string(uctl_node,
93                                             "refclk-type", &clock_type);
94                 of_node_put(uctl_node);
95                 if (!i && strcmp("crystal", clock_type) == 0)
96                         is_crystal_clock = true;
97         }
98
99         /*
100          * Step 1: Wait for voltages stable.  That surely happened
101          * before starting the kernel.
102          *
103          * Step 2: Enable  SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
104          */
105         if_ena.u64 = 0;
106         if_ena.s.en = 1;
107         cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
108
109         for (i = 0; i <= 1; i++) {
110                 port_ctl_status.u64 =
111                         cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
112                 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
113                 port_ctl_status.s.txvreftune = 15;
114                 port_ctl_status.s.txrisetune = 1;
115                 port_ctl_status.s.txpreemphasistune = 1;
116                 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
117                                port_ctl_status.u64);
118         }
119
120         /* Step 3: Configure the reference clock, PHY, and HCLK */
121         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
122
123         /*
124          * If the UCTL looks like it has already been started, skip
125          * the initialization, otherwise bus errors are obtained.
126          */
127         if (clk_rst_ctl.s.hrst)
128                 goto end_clock;
129         /* 3a */
130         clk_rst_ctl.s.p_por = 1;
131         clk_rst_ctl.s.hrst = 0;
132         clk_rst_ctl.s.p_prst = 0;
133         clk_rst_ctl.s.h_clkdiv_rst = 0;
134         clk_rst_ctl.s.o_clkdiv_rst = 0;
135         clk_rst_ctl.s.h_clkdiv_en = 0;
136         clk_rst_ctl.s.o_clkdiv_en = 0;
137         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
138
139         /* 3b */
140         clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
141         switch (clock_rate) {
142         default:
143                 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
144                         clock_rate);
145                 /* Fall through */
146         case 12000000:
147                 clk_rst_ctl.s.p_refclk_div = 0;
148                 break;
149         case 24000000:
150                 clk_rst_ctl.s.p_refclk_div = 1;
151                 break;
152         case 48000000:
153                 clk_rst_ctl.s.p_refclk_div = 2;
154                 break;
155         }
156         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
157
158         /* 3c */
159         div = octeon_get_io_clock_rate() / 130000000ull;
160
161         switch (div) {
162         case 0:
163                 div = 1;
164                 break;
165         case 1:
166         case 2:
167         case 3:
168         case 4:
169                 break;
170         case 5:
171                 div = 4;
172                 break;
173         case 6:
174         case 7:
175                 div = 6;
176                 break;
177         case 8:
178         case 9:
179         case 10:
180         case 11:
181                 div = 8;
182                 break;
183         default:
184                 div = 12;
185                 break;
186         }
187         clk_rst_ctl.s.h_div = div;
188         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
189         /* Read it back, */
190         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
191         clk_rst_ctl.s.h_clkdiv_en = 1;
192         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
193         /* 3d */
194         clk_rst_ctl.s.h_clkdiv_rst = 1;
195         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
196
197         /* 3e: delay 64 io clocks */
198         ndelay(io_clk_64_to_ns);
199
200         /*
201          * Step 4: Program the power-on reset field in the UCTL
202          * clock-reset-control register.
203          */
204         clk_rst_ctl.s.p_por = 0;
205         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
206
207         /* Step 5:    Wait 3 ms for the PHY clock to start. */
208         mdelay(3);
209
210         /* Steps 6..9 for ATE only, are skipped. */
211
212         /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
213         /* 10a */
214         clk_rst_ctl.s.o_clkdiv_rst = 1;
215         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
216
217         /* 10b */
218         clk_rst_ctl.s.o_clkdiv_en = 1;
219         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
220
221         /* 10c */
222         ndelay(io_clk_64_to_ns);
223
224         /*
225          * Step 11: Program the PHY reset field:
226          * UCTL0_CLK_RST_CTL[P_PRST] = 1
227          */
228         clk_rst_ctl.s.p_prst = 1;
229         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
230
231         /* Step 11b */
232         udelay(1);
233
234         /* Step 11c */
235         clk_rst_ctl.s.p_prst = 0;
236         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
237
238         /* Step 11d */
239         mdelay(1);
240
241         /* Step 11e */
242         clk_rst_ctl.s.p_prst = 1;
243         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
244
245         /* Step 12: Wait 1 uS. */
246         udelay(1);
247
248         /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
249         clk_rst_ctl.s.hrst = 1;
250         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
251
252 end_clock:
253         /* Set uSOF cycle period to 60,000 bits. */
254         cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
255
256 exit:
257         mutex_unlock(&octeon2_usb_clocks_mutex);
258 }
259
260 static void octeon2_usb_clocks_stop(void)
261 {
262         mutex_lock(&octeon2_usb_clocks_mutex);
263         octeon2_usb_clock_start_cnt--;
264         mutex_unlock(&octeon2_usb_clocks_mutex);
265 }
266
267 static int octeon_ehci_power_on(struct platform_device *pdev)
268 {
269         octeon2_usb_clocks_start(&pdev->dev);
270         return 0;
271 }
272
273 static void octeon_ehci_power_off(struct platform_device *pdev)
274 {
275         octeon2_usb_clocks_stop();
276 }
277
278 static struct usb_ehci_pdata octeon_ehci_pdata = {
279         /* Octeon EHCI matches CPU endianness. */
280 #ifdef __BIG_ENDIAN
281         .big_endian_mmio        = 1,
282 #endif
283         /*
284          * We can DMA from anywhere. But the descriptors must be in
285          * the lower 4GB.
286          */
287         .dma_mask_64    = 0,
288         .power_on       = octeon_ehci_power_on,
289         .power_off      = octeon_ehci_power_off,
290 };
291
292 static void __init octeon_ehci_hw_start(struct device *dev)
293 {
294         union cvmx_uctlx_ehci_ctl ehci_ctl;
295
296         octeon2_usb_clocks_start(dev);
297
298         ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
299         /* Use 64-bit addressing. */
300         ehci_ctl.s.ehci_64b_addr_en = 1;
301         ehci_ctl.s.l2c_addr_msb = 0;
302 #ifdef __BIG_ENDIAN
303         ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
304         ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
305 #else
306         ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
307         ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
308         ehci_ctl.s.inv_reg_a2 = 1;
309 #endif
310         cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
311
312         octeon2_usb_clocks_stop();
313 }
314
315 static int __init octeon_ehci_device_init(void)
316 {
317         struct platform_device *pd;
318         struct device_node *ehci_node;
319         int ret = 0;
320
321         ehci_node = of_find_node_by_name(NULL, "ehci");
322         if (!ehci_node)
323                 return 0;
324
325         pd = of_find_device_by_node(ehci_node);
326         of_node_put(ehci_node);
327         if (!pd)
328                 return 0;
329
330         pd->dev.platform_data = &octeon_ehci_pdata;
331         octeon_ehci_hw_start(&pd->dev);
332         put_device(&pd->dev);
333
334         return ret;
335 }
336 device_initcall(octeon_ehci_device_init);
337
338 static int octeon_ohci_power_on(struct platform_device *pdev)
339 {
340         octeon2_usb_clocks_start(&pdev->dev);
341         return 0;
342 }
343
344 static void octeon_ohci_power_off(struct platform_device *pdev)
345 {
346         octeon2_usb_clocks_stop();
347 }
348
349 static struct usb_ohci_pdata octeon_ohci_pdata = {
350         /* Octeon OHCI matches CPU endianness. */
351 #ifdef __BIG_ENDIAN
352         .big_endian_mmio        = 1,
353 #endif
354         .power_on       = octeon_ohci_power_on,
355         .power_off      = octeon_ohci_power_off,
356 };
357
358 static void __init octeon_ohci_hw_start(struct device *dev)
359 {
360         union cvmx_uctlx_ohci_ctl ohci_ctl;
361
362         octeon2_usb_clocks_start(dev);
363
364         ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
365         ohci_ctl.s.l2c_addr_msb = 0;
366 #ifdef __BIG_ENDIAN
367         ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
368         ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
369 #else
370         ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
371         ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
372         ohci_ctl.s.inv_reg_a2 = 1;
373 #endif
374         cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
375
376         octeon2_usb_clocks_stop();
377 }
378
379 static int __init octeon_ohci_device_init(void)
380 {
381         struct platform_device *pd;
382         struct device_node *ohci_node;
383         int ret = 0;
384
385         ohci_node = of_find_node_by_name(NULL, "ohci");
386         if (!ohci_node)
387                 return 0;
388
389         pd = of_find_device_by_node(ohci_node);
390         of_node_put(ohci_node);
391         if (!pd)
392                 return 0;
393
394         pd->dev.platform_data = &octeon_ohci_pdata;
395         octeon_ohci_hw_start(&pd->dev);
396         put_device(&pd->dev);
397
398         return ret;
399 }
400 device_initcall(octeon_ohci_device_init);
401
402 #endif /* CONFIG_USB */
403
404 /* Octeon Random Number Generator.  */
405 static int __init octeon_rng_device_init(void)
406 {
407         struct platform_device *pd;
408         int ret = 0;
409
410         struct resource rng_resources[] = {
411                 {
412                         .flags  = IORESOURCE_MEM,
413                         .start  = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
414                         .end    = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
415                 }, {
416                         .flags  = IORESOURCE_MEM,
417                         .start  = cvmx_build_io_address(8, 0),
418                         .end    = cvmx_build_io_address(8, 0) + 0x7
419                 }
420         };
421
422         pd = platform_device_alloc("octeon_rng", -1);
423         if (!pd) {
424                 ret = -ENOMEM;
425                 goto out;
426         }
427
428         ret = platform_device_add_resources(pd, rng_resources,
429                                             ARRAY_SIZE(rng_resources));
430         if (ret)
431                 goto fail;
432
433         ret = platform_device_add(pd);
434         if (ret)
435                 goto fail;
436
437         return ret;
438 fail:
439         platform_device_put(pd);
440
441 out:
442         return ret;
443 }
444 device_initcall(octeon_rng_device_init);
445
446 const struct of_device_id octeon_ids[] __initconst = {
447         { .compatible = "simple-bus", },
448         { .compatible = "cavium,octeon-6335-uctl", },
449         { .compatible = "cavium,octeon-5750-usbn", },
450         { .compatible = "cavium,octeon-3860-bootbus", },
451         { .compatible = "cavium,mdio-mux", },
452         { .compatible = "gpio-leds", },
453         { .compatible = "cavium,octeon-7130-usb-uctl", },
454         {},
455 };
456
457 static bool __init octeon_has_88e1145(void)
458 {
459         return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
460                !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
461                !OCTEON_IS_MODEL(OCTEON_CN56XX);
462 }
463
464 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
465 {
466         const __be32 *phy_handle;
467         const __be32 *alt_phy_handle;
468         const __be32 *reg;
469         u32 phandle;
470         int phy;
471         int alt_phy;
472         const char *p;
473         int current_len;
474         char new_name[20];
475
476         phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
477         if (!phy_handle)
478                 return;
479
480         phandle = be32_to_cpup(phy_handle);
481         phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
482
483         alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
484         if (alt_phy_handle) {
485                 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
486
487                 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
488         } else {
489                 alt_phy = -1;
490         }
491
492         if (phy_addr < 0 || phy < 0) {
493                 /* Delete the PHY things */
494                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
495                 /* This one may fail */
496                 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
497                 if (phy >= 0)
498                         fdt_nop_node(initial_boot_params, phy);
499                 if (alt_phy >= 0)
500                         fdt_nop_node(initial_boot_params, alt_phy);
501                 return;
502         }
503
504         if (phy_addr >= 256 && alt_phy > 0) {
505                 const struct fdt_property *phy_prop;
506                 struct fdt_property *alt_prop;
507                 fdt32_t phy_handle_name;
508
509                 /* Use the alt phy node instead.*/
510                 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
511                 phy_handle_name = phy_prop->nameoff;
512                 fdt_nop_node(initial_boot_params, phy);
513                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
514                 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
515                 alt_prop->nameoff = phy_handle_name;
516                 phy = alt_phy;
517         }
518
519         phy_addr &= 0xff;
520
521         if (octeon_has_88e1145()) {
522                 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
523                 memset(new_name, 0, sizeof(new_name));
524                 strcpy(new_name, "marvell,88e1145");
525                 p = fdt_getprop(initial_boot_params, phy, "compatible",
526                                 &current_len);
527                 if (p && current_len >= strlen(new_name))
528                         fdt_setprop_inplace(initial_boot_params, phy,
529                                         "compatible", new_name, current_len);
530         }
531
532         reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
533         if (phy_addr == be32_to_cpup(reg))
534                 return;
535
536         fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
537
538         snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
539
540         p = fdt_get_name(initial_boot_params, phy, &current_len);
541         if (p && current_len == strlen(new_name))
542                 fdt_set_name(initial_boot_params, phy, new_name);
543         else
544                 pr_err("Error: could not rename ethernet phy: <%s>", p);
545 }
546
547 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
548 {
549         const u8 *old_mac;
550         int old_len;
551         u8 new_mac[6];
552         u64 mac = *pmac;
553         int r;
554
555         old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
556                               &old_len);
557         if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
558                 return;
559
560         new_mac[0] = (mac >> 40) & 0xff;
561         new_mac[1] = (mac >> 32) & 0xff;
562         new_mac[2] = (mac >> 24) & 0xff;
563         new_mac[3] = (mac >> 16) & 0xff;
564         new_mac[4] = (mac >> 8) & 0xff;
565         new_mac[5] = mac & 0xff;
566
567         r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
568                                 new_mac, sizeof(new_mac));
569
570         if (r) {
571                 pr_err("Setting \"local-mac-address\" failed %d", r);
572                 return;
573         }
574         *pmac = mac + 1;
575 }
576
577 static void __init octeon_fdt_rm_ethernet(int node)
578 {
579         const __be32 *phy_handle;
580
581         phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
582         if (phy_handle) {
583                 u32 ph = be32_to_cpup(phy_handle);
584                 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
585
586                 if (p >= 0)
587                         fdt_nop_node(initial_boot_params, p);
588         }
589         fdt_nop_node(initial_boot_params, node);
590 }
591
592 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
593 {
594         char name_buffer[20];
595         int eth;
596         int phy_addr;
597         int ipd_port;
598
599         snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
600         eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
601         if (eth < 0)
602                 return;
603         if (p > max) {
604                 pr_debug("Deleting port %x:%x\n", i, p);
605                 octeon_fdt_rm_ethernet(eth);
606                 return;
607         }
608         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
609                 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
610         else
611                 ipd_port = 16 * i + p;
612
613         phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
614         octeon_fdt_set_phy(eth, phy_addr);
615 }
616
617 static void __init octeon_fdt_pip_iface(int pip, int idx)
618 {
619         char name_buffer[20];
620         int iface;
621         int p;
622         int count = 0;
623
624         snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
625         iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
626         if (iface < 0)
627                 return;
628
629         if (cvmx_helper_interface_enumerate(idx) == 0)
630                 count = cvmx_helper_ports_on_interface(idx);
631
632         for (p = 0; p < 16; p++)
633                 octeon_fdt_pip_port(iface, idx, p, count - 1);
634 }
635
636 void __init octeon_fill_mac_addresses(void)
637 {
638         const char *alias_prop;
639         char name_buffer[20];
640         u64 mac_addr_base;
641         int aliases;
642         int pip;
643         int i;
644
645         aliases = fdt_path_offset(initial_boot_params, "/aliases");
646         if (aliases < 0)
647                 return;
648
649         mac_addr_base =
650                 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
651                 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
652                 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
653                 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
654                 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
655                  (octeon_bootinfo->mac_addr_base[5] & 0xffull);
656
657         for (i = 0; i < 2; i++) {
658                 int mgmt;
659
660                 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
661                 alias_prop = fdt_getprop(initial_boot_params, aliases,
662                                          name_buffer, NULL);
663                 if (!alias_prop)
664                         continue;
665                 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
666                 if (mgmt < 0)
667                         continue;
668                 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
669         }
670
671         alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
672         if (!alias_prop)
673                 return;
674
675         pip = fdt_path_offset(initial_boot_params, alias_prop);
676         if (pip < 0)
677                 return;
678
679         for (i = 0; i <= 4; i++) {
680                 int iface;
681                 int p;
682
683                 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
684                 iface = fdt_subnode_offset(initial_boot_params, pip,
685                                            name_buffer);
686                 if (iface < 0)
687                         continue;
688                 for (p = 0; p < 16; p++) {
689                         int eth;
690
691                         snprintf(name_buffer, sizeof(name_buffer),
692                                  "ethernet@%x", p);
693                         eth = fdt_subnode_offset(initial_boot_params, iface,
694                                                  name_buffer);
695                         if (eth < 0)
696                                 continue;
697                         octeon_fdt_set_mac_addr(eth, &mac_addr_base);
698                 }
699         }
700 }
701
702 int __init octeon_prune_device_tree(void)
703 {
704         int i, max_port, uart_mask;
705         const char *pip_path;
706         const char *alias_prop;
707         char name_buffer[20];
708         int aliases;
709
710         if (fdt_check_header(initial_boot_params))
711                 panic("Corrupt Device Tree.");
712
713         WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
714              "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
715              cvmx_board_type_to_string(octeon_bootinfo->board_type));
716
717         aliases = fdt_path_offset(initial_boot_params, "/aliases");
718         if (aliases < 0) {
719                 pr_err("Error: No /aliases node in device tree.");
720                 return -EINVAL;
721         }
722
723         if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
724                 max_port = 2;
725         else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
726                 max_port = 1;
727         else
728                 max_port = 0;
729
730         if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
731                 max_port = 0;
732
733         for (i = 0; i < 2; i++) {
734                 int mgmt;
735
736                 snprintf(name_buffer, sizeof(name_buffer),
737                          "mix%d", i);
738                 alias_prop = fdt_getprop(initial_boot_params, aliases,
739                                         name_buffer, NULL);
740                 if (alias_prop) {
741                         mgmt = fdt_path_offset(initial_boot_params, alias_prop);
742                         if (mgmt < 0)
743                                 continue;
744                         if (i >= max_port) {
745                                 pr_debug("Deleting mix%d\n", i);
746                                 octeon_fdt_rm_ethernet(mgmt);
747                                 fdt_nop_property(initial_boot_params, aliases,
748                                                  name_buffer);
749                         } else {
750                                 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
751
752                                 octeon_fdt_set_phy(mgmt, phy_addr);
753                         }
754                 }
755         }
756
757         pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
758         if (pip_path) {
759                 int pip = fdt_path_offset(initial_boot_params, pip_path);
760
761                 if (pip  >= 0)
762                         for (i = 0; i <= 4; i++)
763                                 octeon_fdt_pip_iface(pip, i);
764         }
765
766         /* I2C */
767         if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
768             OCTEON_IS_MODEL(OCTEON_CN63XX) ||
769             OCTEON_IS_MODEL(OCTEON_CN68XX) ||
770             OCTEON_IS_MODEL(OCTEON_CN56XX))
771                 max_port = 2;
772         else
773                 max_port = 1;
774
775         for (i = 0; i < 2; i++) {
776                 int i2c;
777
778                 snprintf(name_buffer, sizeof(name_buffer),
779                          "twsi%d", i);
780                 alias_prop = fdt_getprop(initial_boot_params, aliases,
781                                         name_buffer, NULL);
782
783                 if (alias_prop) {
784                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
785                         if (i2c < 0)
786                                 continue;
787                         if (i >= max_port) {
788                                 pr_debug("Deleting twsi%d\n", i);
789                                 fdt_nop_node(initial_boot_params, i2c);
790                                 fdt_nop_property(initial_boot_params, aliases,
791                                                  name_buffer);
792                         }
793                 }
794         }
795
796         /* SMI/MDIO */
797         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
798                 max_port = 4;
799         else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
800                  OCTEON_IS_MODEL(OCTEON_CN63XX) ||
801                  OCTEON_IS_MODEL(OCTEON_CN56XX))
802                 max_port = 2;
803         else
804                 max_port = 1;
805
806         for (i = 0; i < 2; i++) {
807                 int i2c;
808
809                 snprintf(name_buffer, sizeof(name_buffer),
810                          "smi%d", i);
811                 alias_prop = fdt_getprop(initial_boot_params, aliases,
812                                         name_buffer, NULL);
813                 if (alias_prop) {
814                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
815                         if (i2c < 0)
816                                 continue;
817                         if (i >= max_port) {
818                                 pr_debug("Deleting smi%d\n", i);
819                                 fdt_nop_node(initial_boot_params, i2c);
820                                 fdt_nop_property(initial_boot_params, aliases,
821                                                  name_buffer);
822                         }
823                 }
824         }
825
826         /* Serial */
827         uart_mask = 3;
828
829         /* Right now CN52XX is the only chip with a third uart */
830         if (OCTEON_IS_MODEL(OCTEON_CN52XX))
831                 uart_mask |= 4; /* uart2 */
832
833         for (i = 0; i < 3; i++) {
834                 int uart;
835
836                 snprintf(name_buffer, sizeof(name_buffer),
837                          "uart%d", i);
838                 alias_prop = fdt_getprop(initial_boot_params, aliases,
839                                         name_buffer, NULL);
840
841                 if (alias_prop) {
842                         uart = fdt_path_offset(initial_boot_params, alias_prop);
843                         if (uart_mask & (1 << i)) {
844                                 __be32 f;
845
846                                 f = cpu_to_be32(octeon_get_io_clock_rate());
847                                 fdt_setprop_inplace(initial_boot_params,
848                                                     uart, "clock-frequency",
849                                                     &f, sizeof(f));
850                                 continue;
851                         }
852                         pr_debug("Deleting uart%d\n", i);
853                         fdt_nop_node(initial_boot_params, uart);
854                         fdt_nop_property(initial_boot_params, aliases,
855                                          name_buffer);
856                 }
857         }
858
859         /* Compact Flash */
860         alias_prop = fdt_getprop(initial_boot_params, aliases,
861                                  "cf0", NULL);
862         if (alias_prop) {
863                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
864                 unsigned long base_ptr, region_base, region_size;
865                 unsigned long region1_base = 0;
866                 unsigned long region1_size = 0;
867                 int cs, bootbus;
868                 bool is_16bit = false;
869                 bool is_true_ide = false;
870                 __be32 new_reg[6];
871                 __be32 *ranges;
872                 int len;
873
874                 int cf = fdt_path_offset(initial_boot_params, alias_prop);
875
876                 base_ptr = 0;
877                 if (octeon_bootinfo->major_version == 1
878                         && octeon_bootinfo->minor_version >= 1) {
879                         if (octeon_bootinfo->compact_flash_common_base_addr)
880                                 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
881                 } else {
882                         base_ptr = 0x1d000800;
883                 }
884
885                 if (!base_ptr)
886                         goto no_cf;
887
888                 /* Find CS0 region. */
889                 for (cs = 0; cs < 8; cs++) {
890                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
891                         region_base = mio_boot_reg_cfg.s.base << 16;
892                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
893                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
894                                 && base_ptr < region_base + region_size) {
895                                 is_16bit = mio_boot_reg_cfg.s.width;
896                                 break;
897                         }
898                 }
899                 if (cs >= 7) {
900                         /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
901                         goto no_cf;
902                 }
903
904                 if (!(base_ptr & 0xfffful)) {
905                         /*
906                          * Boot loader signals availability of DMA (true_ide
907                          * mode) by setting low order bits of base_ptr to
908                          * zero.
909                          */
910
911                         /* Asume that CS1 immediately follows. */
912                         mio_boot_reg_cfg.u64 =
913                                 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
914                         region1_base = mio_boot_reg_cfg.s.base << 16;
915                         region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
916                         if (!mio_boot_reg_cfg.s.en)
917                                 goto no_cf;
918                         is_true_ide = true;
919
920                 } else {
921                         fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
922                         fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
923                         if (!is_16bit) {
924                                 __be32 width = cpu_to_be32(8);
925
926                                 fdt_setprop_inplace(initial_boot_params, cf,
927                                                 "cavium,bus-width", &width, sizeof(width));
928                         }
929                 }
930                 new_reg[0] = cpu_to_be32(cs);
931                 new_reg[1] = cpu_to_be32(0);
932                 new_reg[2] = cpu_to_be32(0x10000);
933                 new_reg[3] = cpu_to_be32(cs + 1);
934                 new_reg[4] = cpu_to_be32(0);
935                 new_reg[5] = cpu_to_be32(0x10000);
936                 fdt_setprop_inplace(initial_boot_params, cf,
937                                     "reg",  new_reg, sizeof(new_reg));
938
939                 bootbus = fdt_parent_offset(initial_boot_params, cf);
940                 if (bootbus < 0)
941                         goto no_cf;
942                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
943                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
944                         goto no_cf;
945
946                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
947                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
948                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
949                 if (is_true_ide) {
950                         cs++;
951                         ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
952                         ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
953                         ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
954                 }
955                 goto end_cf;
956 no_cf:
957                 fdt_nop_node(initial_boot_params, cf);
958
959 end_cf:
960                 ;
961         }
962
963         /* 8 char LED */
964         alias_prop = fdt_getprop(initial_boot_params, aliases,
965                                  "led0", NULL);
966         if (alias_prop) {
967                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
968                 unsigned long base_ptr, region_base, region_size;
969                 int cs, bootbus;
970                 __be32 new_reg[6];
971                 __be32 *ranges;
972                 int len;
973                 int led = fdt_path_offset(initial_boot_params, alias_prop);
974
975                 base_ptr = octeon_bootinfo->led_display_base_addr;
976                 if (base_ptr == 0)
977                         goto no_led;
978                 /* Find CS0 region. */
979                 for (cs = 0; cs < 8; cs++) {
980                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
981                         region_base = mio_boot_reg_cfg.s.base << 16;
982                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
983                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
984                                 && base_ptr < region_base + region_size)
985                                 break;
986                 }
987
988                 if (cs > 7)
989                         goto no_led;
990
991                 new_reg[0] = cpu_to_be32(cs);
992                 new_reg[1] = cpu_to_be32(0x20);
993                 new_reg[2] = cpu_to_be32(0x20);
994                 new_reg[3] = cpu_to_be32(cs);
995                 new_reg[4] = cpu_to_be32(0);
996                 new_reg[5] = cpu_to_be32(0x20);
997                 fdt_setprop_inplace(initial_boot_params, led,
998                                     "reg",  new_reg, sizeof(new_reg));
999
1000                 bootbus = fdt_parent_offset(initial_boot_params, led);
1001                 if (bootbus < 0)
1002                         goto no_led;
1003                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1004                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
1005                         goto no_led;
1006
1007                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1008                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1009                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1010                 goto end_led;
1011
1012 no_led:
1013                 fdt_nop_node(initial_boot_params, led);
1014 end_led:
1015                 ;
1016         }
1017
1018 #ifdef CONFIG_USB
1019         /* OHCI/UHCI USB */
1020         alias_prop = fdt_getprop(initial_boot_params, aliases,
1021                                  "uctl", NULL);
1022         if (alias_prop) {
1023                 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1024
1025                 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1026                                   octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1027                         pr_debug("Deleting uctl\n");
1028                         fdt_nop_node(initial_boot_params, uctl);
1029                         fdt_nop_property(initial_boot_params, aliases, "uctl");
1030                 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1031                            octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1032                         /* Missing "refclk-type" defaults to crystal. */
1033                         fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1034                 }
1035         }
1036
1037         /* DWC2 USB */
1038         alias_prop = fdt_getprop(initial_boot_params, aliases,
1039                                  "usbn", NULL);
1040         if (alias_prop) {
1041                 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1042
1043                 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1044                                   !octeon_has_feature(OCTEON_FEATURE_USB))) {
1045                         pr_debug("Deleting usbn\n");
1046                         fdt_nop_node(initial_boot_params, usbn);
1047                         fdt_nop_property(initial_boot_params, aliases, "usbn");
1048                 } else  {
1049                         __be32 new_f[1];
1050                         enum cvmx_helper_board_usb_clock_types c;
1051
1052                         c = __cvmx_helper_board_usb_get_clock_type();
1053                         switch (c) {
1054                         case USB_CLOCK_TYPE_REF_48:
1055                                 new_f[0] = cpu_to_be32(48000000);
1056                                 fdt_setprop_inplace(initial_boot_params, usbn,
1057                                                     "refclk-frequency",  new_f, sizeof(new_f));
1058                                 /* Fall through ...*/
1059                         case USB_CLOCK_TYPE_REF_12:
1060                                 /* Missing "refclk-type" defaults to external. */
1061                                 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1062                                 break;
1063                         default:
1064                                 break;
1065                         }
1066                 }
1067         }
1068 #endif
1069
1070         return 0;
1071 }
1072
1073 static int __init octeon_publish_devices(void)
1074 {
1075         return of_platform_populate(NULL, octeon_ids, NULL, NULL);
1076 }
1077 arch_initcall(octeon_publish_devices);