2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2016 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of_platform.h>
14 #include <linux/of_fdt.h>
15 #include <linux/libfdt.h>
16 #include <linux/usb/ehci_def.h>
17 #include <linux/usb/ehci_pdriver.h>
18 #include <linux/usb/ohci_pdriver.h>
20 #include <asm/octeon/octeon.h>
21 #include <asm/octeon/cvmx-helper-board.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
27 /* Octeon Random Number Generator. */
28 static int __init octeon_rng_device_init(void)
30 struct platform_device *pd;
33 struct resource rng_resources[] = {
35 .flags = IORESOURCE_MEM,
36 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
37 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
39 .flags = IORESOURCE_MEM,
40 .start = cvmx_build_io_address(8, 0),
41 .end = cvmx_build_io_address(8, 0) + 0x7
45 pd = platform_device_alloc("octeon_rng", -1);
51 ret = platform_device_add_resources(pd, rng_resources,
52 ARRAY_SIZE(rng_resources));
56 ret = platform_device_add(pd);
62 platform_device_put(pd);
67 device_initcall(octeon_rng_device_init);
71 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
73 static int octeon2_usb_clock_start_cnt;
75 static int __init octeon2_usb_reset(void)
77 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
80 if (!OCTEON_IS_OCTEON2())
83 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
84 if (clk_rst_ctl.s.hrst) {
85 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
87 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
90 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
91 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
93 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
98 arch_initcall(octeon2_usb_reset);
100 static void octeon2_usb_clocks_start(struct device *dev)
103 union cvmx_uctlx_if_ena if_ena;
104 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
105 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
107 unsigned long io_clk_64_to_ns;
108 u32 clock_rate = 12000000;
109 bool is_crystal_clock = false;
112 mutex_lock(&octeon2_usb_clocks_mutex);
114 octeon2_usb_clock_start_cnt++;
115 if (octeon2_usb_clock_start_cnt != 1)
118 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
121 struct device_node *uctl_node;
122 const char *clock_type;
124 uctl_node = of_get_parent(dev->of_node);
126 dev_err(dev, "No UCTL device node\n");
129 i = of_property_read_u32(uctl_node,
130 "refclk-frequency", &clock_rate);
132 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
135 i = of_property_read_string(uctl_node,
136 "refclk-type", &clock_type);
138 if (!i && strcmp("crystal", clock_type) == 0)
139 is_crystal_clock = true;
143 * Step 1: Wait for voltages stable. That surely happened
144 * before starting the kernel.
146 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
150 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
152 for (i = 0; i <= 1; i++) {
153 port_ctl_status.u64 =
154 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
155 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
156 port_ctl_status.s.txvreftune = 15;
157 port_ctl_status.s.txrisetune = 1;
158 port_ctl_status.s.txpreemphasistune = 1;
159 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
160 port_ctl_status.u64);
163 /* Step 3: Configure the reference clock, PHY, and HCLK */
164 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
167 * If the UCTL looks like it has already been started, skip
168 * the initialization, otherwise bus errors are obtained.
170 if (clk_rst_ctl.s.hrst)
173 clk_rst_ctl.s.p_por = 1;
174 clk_rst_ctl.s.hrst = 0;
175 clk_rst_ctl.s.p_prst = 0;
176 clk_rst_ctl.s.h_clkdiv_rst = 0;
177 clk_rst_ctl.s.o_clkdiv_rst = 0;
178 clk_rst_ctl.s.h_clkdiv_en = 0;
179 clk_rst_ctl.s.o_clkdiv_en = 0;
180 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
183 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
184 switch (clock_rate) {
186 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
190 clk_rst_ctl.s.p_refclk_div = 0;
193 clk_rst_ctl.s.p_refclk_div = 1;
196 clk_rst_ctl.s.p_refclk_div = 2;
199 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
202 div = octeon_get_io_clock_rate() / 130000000ull;
230 clk_rst_ctl.s.h_div = div;
231 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
233 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
234 clk_rst_ctl.s.h_clkdiv_en = 1;
235 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
237 clk_rst_ctl.s.h_clkdiv_rst = 1;
238 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
240 /* 3e: delay 64 io clocks */
241 ndelay(io_clk_64_to_ns);
244 * Step 4: Program the power-on reset field in the UCTL
245 * clock-reset-control register.
247 clk_rst_ctl.s.p_por = 0;
248 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
250 /* Step 5: Wait 3 ms for the PHY clock to start. */
253 /* Steps 6..9 for ATE only, are skipped. */
255 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
257 clk_rst_ctl.s.o_clkdiv_rst = 1;
258 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
261 clk_rst_ctl.s.o_clkdiv_en = 1;
262 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
265 ndelay(io_clk_64_to_ns);
268 * Step 11: Program the PHY reset field:
269 * UCTL0_CLK_RST_CTL[P_PRST] = 1
271 clk_rst_ctl.s.p_prst = 1;
272 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
278 clk_rst_ctl.s.p_prst = 0;
279 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
285 clk_rst_ctl.s.p_prst = 1;
286 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
288 /* Step 12: Wait 1 uS. */
291 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
292 clk_rst_ctl.s.hrst = 1;
293 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
296 /* Set uSOF cycle period to 60,000 bits. */
297 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
300 mutex_unlock(&octeon2_usb_clocks_mutex);
303 static void octeon2_usb_clocks_stop(void)
305 mutex_lock(&octeon2_usb_clocks_mutex);
306 octeon2_usb_clock_start_cnt--;
307 mutex_unlock(&octeon2_usb_clocks_mutex);
310 static int octeon_ehci_power_on(struct platform_device *pdev)
312 octeon2_usb_clocks_start(&pdev->dev);
316 static void octeon_ehci_power_off(struct platform_device *pdev)
318 octeon2_usb_clocks_stop();
321 static struct usb_ehci_pdata octeon_ehci_pdata = {
322 /* Octeon EHCI matches CPU endianness. */
324 .big_endian_mmio = 1,
327 * We can DMA from anywhere. But the descriptors must be in
331 .power_on = octeon_ehci_power_on,
332 .power_off = octeon_ehci_power_off,
335 static void __init octeon_ehci_hw_start(struct device *dev)
337 union cvmx_uctlx_ehci_ctl ehci_ctl;
339 octeon2_usb_clocks_start(dev);
341 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
342 /* Use 64-bit addressing. */
343 ehci_ctl.s.ehci_64b_addr_en = 1;
344 ehci_ctl.s.l2c_addr_msb = 0;
346 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
347 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
349 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
350 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
351 ehci_ctl.s.inv_reg_a2 = 1;
353 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
355 octeon2_usb_clocks_stop();
358 static int __init octeon_ehci_device_init(void)
360 struct platform_device *pd;
361 struct device_node *ehci_node;
364 ehci_node = of_find_node_by_name(NULL, "ehci");
368 pd = of_find_device_by_node(ehci_node);
369 of_node_put(ehci_node);
373 pd->dev.platform_data = &octeon_ehci_pdata;
374 octeon_ehci_hw_start(&pd->dev);
378 device_initcall(octeon_ehci_device_init);
380 static int octeon_ohci_power_on(struct platform_device *pdev)
382 octeon2_usb_clocks_start(&pdev->dev);
386 static void octeon_ohci_power_off(struct platform_device *pdev)
388 octeon2_usb_clocks_stop();
391 static struct usb_ohci_pdata octeon_ohci_pdata = {
392 /* Octeon OHCI matches CPU endianness. */
394 .big_endian_mmio = 1,
396 .power_on = octeon_ohci_power_on,
397 .power_off = octeon_ohci_power_off,
400 static void __init octeon_ohci_hw_start(struct device *dev)
402 union cvmx_uctlx_ohci_ctl ohci_ctl;
404 octeon2_usb_clocks_start(dev);
406 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
407 ohci_ctl.s.l2c_addr_msb = 0;
409 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
410 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
412 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
413 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
414 ohci_ctl.s.inv_reg_a2 = 1;
416 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
418 octeon2_usb_clocks_stop();
421 static int __init octeon_ohci_device_init(void)
423 struct platform_device *pd;
424 struct device_node *ohci_node;
427 ohci_node = of_find_node_by_name(NULL, "ohci");
431 pd = of_find_device_by_node(ohci_node);
432 of_node_put(ohci_node);
436 pd->dev.platform_data = &octeon_ohci_pdata;
437 octeon_ohci_hw_start(&pd->dev);
441 device_initcall(octeon_ohci_device_init);
443 #endif /* CONFIG_USB */
446 static struct of_device_id __initdata octeon_ids[] = {
447 { .compatible = "simple-bus", },
448 { .compatible = "cavium,octeon-6335-uctl", },
449 { .compatible = "cavium,octeon-5750-usbn", },
450 { .compatible = "cavium,octeon-3860-bootbus", },
451 { .compatible = "cavium,mdio-mux", },
452 { .compatible = "gpio-leds", },
456 static bool __init octeon_has_88e1145(void)
458 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
459 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
460 !OCTEON_IS_MODEL(OCTEON_CN56XX);
463 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
465 const __be32 *phy_handle;
466 const __be32 *alt_phy_handle;
475 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
479 phandle = be32_to_cpup(phy_handle);
480 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
482 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
483 if (alt_phy_handle) {
484 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
485 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
490 if (phy_addr < 0 || phy < 0) {
491 /* Delete the PHY things */
492 fdt_nop_property(initial_boot_params, eth, "phy-handle");
493 /* This one may fail */
494 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
496 fdt_nop_node(initial_boot_params, phy);
498 fdt_nop_node(initial_boot_params, alt_phy);
502 if (phy_addr >= 256 && alt_phy > 0) {
503 const struct fdt_property *phy_prop;
504 struct fdt_property *alt_prop;
505 fdt32_t phy_handle_name;
507 /* Use the alt phy node instead.*/
508 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
509 phy_handle_name = phy_prop->nameoff;
510 fdt_nop_node(initial_boot_params, phy);
511 fdt_nop_property(initial_boot_params, eth, "phy-handle");
512 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
513 alt_prop->nameoff = phy_handle_name;
519 if (octeon_has_88e1145()) {
520 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
521 memset(new_name, 0, sizeof(new_name));
522 strcpy(new_name, "marvell,88e1145");
523 p = fdt_getprop(initial_boot_params, phy, "compatible",
525 if (p && current_len >= strlen(new_name))
526 fdt_setprop_inplace(initial_boot_params, phy,
527 "compatible", new_name, current_len);
530 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
531 if (phy_addr == be32_to_cpup(reg))
534 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
536 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
538 p = fdt_get_name(initial_boot_params, phy, ¤t_len);
539 if (p && current_len == strlen(new_name))
540 fdt_set_name(initial_boot_params, phy, new_name);
542 pr_err("Error: could not rename ethernet phy: <%s>", p);
545 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
553 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
555 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
558 new_mac[0] = (mac >> 40) & 0xff;
559 new_mac[1] = (mac >> 32) & 0xff;
560 new_mac[2] = (mac >> 24) & 0xff;
561 new_mac[3] = (mac >> 16) & 0xff;
562 new_mac[4] = (mac >> 8) & 0xff;
563 new_mac[5] = mac & 0xff;
565 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
566 new_mac, sizeof(new_mac));
569 pr_err("Setting \"local-mac-address\" failed %d", r);
575 static void __init octeon_fdt_rm_ethernet(int node)
577 const __be32 *phy_handle;
579 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
581 u32 ph = be32_to_cpup(phy_handle);
582 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
584 fdt_nop_node(initial_boot_params, p);
586 fdt_nop_node(initial_boot_params, node);
589 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
591 char name_buffer[20];
596 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
597 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
601 pr_debug("Deleting port %x:%x\n", i, p);
602 octeon_fdt_rm_ethernet(eth);
605 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
606 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
608 ipd_port = 16 * i + p;
610 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
611 octeon_fdt_set_phy(eth, phy_addr);
614 static void __init octeon_fdt_pip_iface(int pip, int idx)
616 char name_buffer[20];
621 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
622 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
626 if (cvmx_helper_interface_enumerate(idx) == 0)
627 count = cvmx_helper_ports_on_interface(idx);
629 for (p = 0; p < 16; p++)
630 octeon_fdt_pip_port(iface, idx, p, count - 1);
633 void __init octeon_fill_mac_addresses(void)
635 const char *alias_prop;
636 char name_buffer[20];
642 aliases = fdt_path_offset(initial_boot_params, "/aliases");
647 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
648 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
649 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
650 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
651 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
652 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
654 for (i = 0; i < 2; i++) {
657 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
658 alias_prop = fdt_getprop(initial_boot_params, aliases,
662 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
665 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
668 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
672 pip = fdt_path_offset(initial_boot_params, alias_prop);
676 for (i = 0; i <= 4; i++) {
680 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
681 iface = fdt_subnode_offset(initial_boot_params, pip,
685 for (p = 0; p < 16; p++) {
688 snprintf(name_buffer, sizeof(name_buffer),
690 eth = fdt_subnode_offset(initial_boot_params, iface,
694 octeon_fdt_set_mac_addr(eth, &mac_addr_base);
699 int __init octeon_prune_device_tree(void)
701 int i, max_port, uart_mask;
702 const char *pip_path;
703 const char *alias_prop;
704 char name_buffer[20];
707 if (fdt_check_header(initial_boot_params))
708 panic("Corrupt Device Tree.");
710 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
711 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
712 cvmx_board_type_to_string(octeon_bootinfo->board_type));
714 aliases = fdt_path_offset(initial_boot_params, "/aliases");
716 pr_err("Error: No /aliases node in device tree.");
720 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
722 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
727 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
730 for (i = 0; i < 2; i++) {
732 snprintf(name_buffer, sizeof(name_buffer),
734 alias_prop = fdt_getprop(initial_boot_params, aliases,
737 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
741 pr_debug("Deleting mix%d\n", i);
742 octeon_fdt_rm_ethernet(mgmt);
743 fdt_nop_property(initial_boot_params, aliases,
746 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
747 octeon_fdt_set_phy(mgmt, phy_addr);
752 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
754 int pip = fdt_path_offset(initial_boot_params, pip_path);
756 for (i = 0; i <= 4; i++)
757 octeon_fdt_pip_iface(pip, i);
761 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
762 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
763 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
764 OCTEON_IS_MODEL(OCTEON_CN56XX))
769 for (i = 0; i < 2; i++) {
771 snprintf(name_buffer, sizeof(name_buffer),
773 alias_prop = fdt_getprop(initial_boot_params, aliases,
777 i2c = fdt_path_offset(initial_boot_params, alias_prop);
781 pr_debug("Deleting twsi%d\n", i);
782 fdt_nop_node(initial_boot_params, i2c);
783 fdt_nop_property(initial_boot_params, aliases,
790 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
792 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
793 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
794 OCTEON_IS_MODEL(OCTEON_CN56XX))
799 for (i = 0; i < 2; i++) {
801 snprintf(name_buffer, sizeof(name_buffer),
803 alias_prop = fdt_getprop(initial_boot_params, aliases,
807 i2c = fdt_path_offset(initial_boot_params, alias_prop);
811 pr_debug("Deleting smi%d\n", i);
812 fdt_nop_node(initial_boot_params, i2c);
813 fdt_nop_property(initial_boot_params, aliases,
822 /* Right now CN52XX is the only chip with a third uart */
823 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
824 uart_mask |= 4; /* uart2 */
826 for (i = 0; i < 3; i++) {
828 snprintf(name_buffer, sizeof(name_buffer),
830 alias_prop = fdt_getprop(initial_boot_params, aliases,
834 uart = fdt_path_offset(initial_boot_params, alias_prop);
835 if (uart_mask & (1 << i)) {
838 f = cpu_to_be32(octeon_get_io_clock_rate());
839 fdt_setprop_inplace(initial_boot_params,
840 uart, "clock-frequency",
844 pr_debug("Deleting uart%d\n", i);
845 fdt_nop_node(initial_boot_params, uart);
846 fdt_nop_property(initial_boot_params, aliases,
852 alias_prop = fdt_getprop(initial_boot_params, aliases,
855 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
856 unsigned long base_ptr, region_base, region_size;
857 unsigned long region1_base = 0;
858 unsigned long region1_size = 0;
860 bool is_16bit = false;
861 bool is_true_ide = false;
866 int cf = fdt_path_offset(initial_boot_params, alias_prop);
868 if (octeon_bootinfo->major_version == 1
869 && octeon_bootinfo->minor_version >= 1) {
870 if (octeon_bootinfo->compact_flash_common_base_addr)
871 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
873 base_ptr = 0x1d000800;
879 /* Find CS0 region. */
880 for (cs = 0; cs < 8; cs++) {
881 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
882 region_base = mio_boot_reg_cfg.s.base << 16;
883 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
884 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
885 && base_ptr < region_base + region_size) {
886 is_16bit = mio_boot_reg_cfg.s.width;
891 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
895 if (!(base_ptr & 0xfffful)) {
897 * Boot loader signals availability of DMA (true_ide
898 * mode) by setting low order bits of base_ptr to
902 /* Asume that CS1 immediately follows. */
903 mio_boot_reg_cfg.u64 =
904 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
905 region1_base = mio_boot_reg_cfg.s.base << 16;
906 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
907 if (!mio_boot_reg_cfg.s.en)
912 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
913 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
915 __be32 width = cpu_to_be32(8);
916 fdt_setprop_inplace(initial_boot_params, cf,
917 "cavium,bus-width", &width, sizeof(width));
920 new_reg[0] = cpu_to_be32(cs);
921 new_reg[1] = cpu_to_be32(0);
922 new_reg[2] = cpu_to_be32(0x10000);
923 new_reg[3] = cpu_to_be32(cs + 1);
924 new_reg[4] = cpu_to_be32(0);
925 new_reg[5] = cpu_to_be32(0x10000);
926 fdt_setprop_inplace(initial_boot_params, cf,
927 "reg", new_reg, sizeof(new_reg));
929 bootbus = fdt_parent_offset(initial_boot_params, cf);
932 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
933 if (!ranges || len < (5 * 8 * sizeof(__be32)))
936 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
937 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
938 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
941 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
942 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
943 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
947 fdt_nop_node(initial_boot_params, cf);
954 alias_prop = fdt_getprop(initial_boot_params, aliases,
957 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
958 unsigned long base_ptr, region_base, region_size;
963 int led = fdt_path_offset(initial_boot_params, alias_prop);
965 base_ptr = octeon_bootinfo->led_display_base_addr;
968 /* Find CS0 region. */
969 for (cs = 0; cs < 8; cs++) {
970 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
971 region_base = mio_boot_reg_cfg.s.base << 16;
972 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
973 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
974 && base_ptr < region_base + region_size)
981 new_reg[0] = cpu_to_be32(cs);
982 new_reg[1] = cpu_to_be32(0x20);
983 new_reg[2] = cpu_to_be32(0x20);
984 new_reg[3] = cpu_to_be32(cs);
985 new_reg[4] = cpu_to_be32(0);
986 new_reg[5] = cpu_to_be32(0x20);
987 fdt_setprop_inplace(initial_boot_params, led,
988 "reg", new_reg, sizeof(new_reg));
990 bootbus = fdt_parent_offset(initial_boot_params, led);
993 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
994 if (!ranges || len < (5 * 8 * sizeof(__be32)))
997 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
998 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
999 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1003 fdt_nop_node(initial_boot_params, led);
1009 alias_prop = fdt_getprop(initial_boot_params, aliases,
1012 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1014 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1015 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1016 pr_debug("Deleting uctl\n");
1017 fdt_nop_node(initial_boot_params, uctl);
1018 fdt_nop_property(initial_boot_params, aliases, "uctl");
1019 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1020 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1021 /* Missing "refclk-type" defaults to crystal. */
1022 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1027 alias_prop = fdt_getprop(initial_boot_params, aliases,
1030 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1032 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1033 !octeon_has_feature(OCTEON_FEATURE_USB))) {
1034 pr_debug("Deleting usbn\n");
1035 fdt_nop_node(initial_boot_params, usbn);
1036 fdt_nop_property(initial_boot_params, aliases, "usbn");
1039 enum cvmx_helper_board_usb_clock_types c;
1040 c = __cvmx_helper_board_usb_get_clock_type();
1042 case USB_CLOCK_TYPE_REF_48:
1043 new_f[0] = cpu_to_be32(48000000);
1044 fdt_setprop_inplace(initial_boot_params, usbn,
1045 "refclk-frequency", new_f, sizeof(new_f));
1046 /* Fall through ...*/
1047 case USB_CLOCK_TYPE_REF_12:
1048 /* Missing "refclk-type" defaults to external. */
1049 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1060 static int __init octeon_publish_devices(void)
1062 return of_platform_bus_probe(NULL, octeon_ids, NULL);
1064 arch_initcall(octeon_publish_devices);
1066 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
1067 MODULE_LICENSE("GPL");
1068 MODULE_DESCRIPTION("Platform driver for Octeon SOC");