1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
10 compatible = "mediatek,mt7621-soc";
18 compatible = "mips,mips1004Kc";
24 compatible = "mips,mips1004Kc";
31 #interrupt-cells = <1>;
33 compatible = "mti,cpu-interrupt-controller";
36 mmc_fixed_3v3: regulator-3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "mmc_power";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
45 mmc_fixed_1v8_io: regulator-1v8 {
46 compatible = "regulator-fixed";
47 regulator-name = "mmc_io";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
54 palmbus: palmbus@1e000000 {
55 compatible = "palmbus";
56 reg = <0x1e000000 0x100000>;
57 ranges = <0x0 0x1e000000 0x0fffff>;
63 compatible = "mediatek,mt7621-sysc", "syscon";
67 ralink,memctl = <&memc>;
68 clock-output-names = "xtal", "cpu", "bus",
69 "50m", "125m", "150m",
74 compatible = "mediatek,mt7621-wdt";
76 mediatek,sysctl = <&sysc>;
81 #interrupt-cells = <2>;
82 compatible = "mediatek,mt7621-gpio";
84 gpio-ranges = <&pinctrl 0 0 95>;
87 interrupt-parent = <&gic>;
88 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
92 compatible = "mediatek,mt7621-i2c";
95 clocks = <&sysc MT7621_CLK_I2C>;
97 resets = <&sysc MT7621_RST_I2C>;
100 #address-cells = <1>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&i2c_pins>;
109 memc: memory-controller@5000 {
110 compatible = "mediatek,mt7621-memc", "syscon";
111 reg = <0x5000 0x1000>;
114 serial0: serial@c00 {
115 compatible = "ns16550a";
118 clocks = <&sysc MT7621_CLK_UART1>;
120 interrupt-parent = <&gic>;
121 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
131 compatible = "ralink,mt7621-spi";
134 clocks = <&sysc MT7621_CLK_SPI>;
137 resets = <&sysc MT7621_RST_SPI>;
140 #address-cells = <1>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&spi_pins>;
149 compatible = "ralink,mt7621-pinctrl";
151 i2c_pins: i2c0-pins {
158 spi_pins: spi0-pins {
165 uart1_pins: uart1-pins {
172 uart2_pins: uart2-pins {
179 uart3_pins: uart3-pins {
186 rgmii1_pins: rgmii1-pins {
193 rgmii2_pins: rgmii2-pins {
200 mdio_pins: mdio0-pins {
207 pcie_pins: pcie0-pins {
214 nand_pins: nand0-pins {
226 sdhci_pins: sdhci0-pins {
237 compatible = "mediatek,mt7620-mmc";
238 reg = <0x1e130000 0x4000>;
241 max-frequency = <48000000>;
244 vmmc-supply = <&mmc_fixed_3v3>;
245 vqmmc-supply = <&mmc_fixed_1v8_io>;
248 pinctrl-names = "default", "state_uhs";
249 pinctrl-0 = <&sdhci_pins>;
250 pinctrl-1 = <&sdhci_pins>;
252 clocks = <&sysc MT7621_CLK_SHXC>,
253 <&sysc MT7621_CLK_50M>;
254 clock-names = "source", "hclk";
256 interrupt-parent = <&gic>;
257 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
261 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
262 reg = <0x1e1c0000 0x1000
264 reg-names = "mac", "ippc";
266 clocks = <&sysc MT7621_CLK_XTAL>;
267 clock-names = "sys_ck";
269 interrupt-parent = <&gic>;
270 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
273 gic: interrupt-controller@1fbc0000 {
274 compatible = "mti,gic";
275 reg = <0x1fbc0000 0x2000>;
277 interrupt-controller;
278 #interrupt-cells = <3>;
280 mti,reserved-cpu-vectors = <7>;
283 compatible = "mti,gic-timer";
284 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
285 clocks = <&sysc MT7621_CLK_CPU>;
290 compatible = "mti,mips-cpc";
291 reg = <0x1fbf0000 0x8000>;
294 cdmm: cdmm@1fbf8000 {
295 compatible = "mti,mips-cdmm";
296 reg = <0x1fbf8000 0x8000>;
299 ethernet: ethernet@1e100000 {
300 compatible = "mediatek,mt7621-eth";
301 reg = <0x1e100000 0x10000>;
303 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
304 clock-names = "fe", "ethif";
306 #address-cells = <1>;
309 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
310 reset-names = "fe", "eth";
312 interrupt-parent = <&gic>;
313 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
315 mediatek,ethsys = <&sysc>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
321 compatible = "mediatek,eth-mac";
333 compatible = "mediatek,eth-mac";
345 #address-cells = <1>;
349 compatible = "mediatek,mt7621";
352 resets = <&sysc MT7621_RST_MCM>;
354 interrupt-controller;
355 #interrupt-cells = <1>;
356 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
420 pcie: pcie@1e140000 {
421 compatible = "mediatek,mt7621-pci";
422 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
423 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
424 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
425 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
426 #address-cells = <3>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pcie_pins>;
434 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
435 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
437 #interrupt-cells = <1>;
438 interrupt-map-mask = <0xF800 0 0 0>;
439 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
440 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
441 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
445 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
448 reg = <0x0000 0 0 0 0>;
449 #address-cells = <3>;
452 #interrupt-cells = <1>;
453 interrupt-map-mask = <0 0 0 0>;
454 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
455 resets = <&sysc MT7621_RST_PCIE0>;
456 clocks = <&sysc MT7621_CLK_PCIE0>;
457 phys = <&pcie0_phy 1>;
458 phy-names = "pcie-phy0";
463 reg = <0x0800 0 0 0 0>;
464 #address-cells = <3>;
467 #interrupt-cells = <1>;
468 interrupt-map-mask = <0 0 0 0>;
469 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
470 resets = <&sysc MT7621_RST_PCIE1>;
471 clocks = <&sysc MT7621_CLK_PCIE1>;
472 phys = <&pcie0_phy 1>;
473 phy-names = "pcie-phy1";
478 reg = <0x1000 0 0 0 0>;
479 #address-cells = <3>;
482 #interrupt-cells = <1>;
483 interrupt-map-mask = <0 0 0 0>;
484 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
485 resets = <&sysc MT7621_RST_PCIE2>;
486 clocks = <&sysc MT7621_CLK_PCIE2>;
487 phys = <&pcie2_phy 0>;
488 phy-names = "pcie-phy2";
493 pcie0_phy: pcie-phy@1e149000 {
494 compatible = "mediatek,mt7621-pci-phy";
495 reg = <0x1e149000 0x0700>;
496 clocks = <&sysc MT7621_CLK_XTAL>;
500 pcie2_phy: pcie-phy@1e14a000 {
501 compatible = "mediatek,mt7621-pci-phy";
502 reg = <0x1e14a000 0x0700>;
503 clocks = <&sysc MT7621_CLK_XTAL>;