1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
5 compatible = "qca,ar9331";
16 compatible = "mips,mips24Kc";
17 clocks = <&pll ATH79_CLK_CPU>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
26 #interrupt-cells = <1>;
28 qca,ddr-wb-channel-interrupts = <2>, <3>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
33 compatible = "fixed-clock";
38 compatible = "simple-bus";
44 interrupt-parent = <&cpuintc>;
47 compatible = "simple-bus";
53 interrupt-parent = <&miscintc>;
55 ddr_ctrl: memory-controller@18000000 {
56 compatible = "qca,ar7240-ddr-controller";
57 reg = <0x18000000 0x100>;
59 #qca,ddr-wb-channel-cells = <1>;
62 uart: serial@18020000 {
63 compatible = "qca,ar9330-uart";
64 reg = <0x18020000 0x14>;
75 compatible = "qca,ar7100-gpio";
76 reg = <0x18040000 0x34>;
85 #interrupt-cells = <2>;
90 pll: pll-controller@18050000 {
91 compatible = "qca,ar9330-pll";
92 reg = <0x18050000 0x100>;
100 miscintc: interrupt-controller@18060010 {
101 compatible = "qca,ar7240-misc-intc";
102 reg = <0x18060010 0x8>;
104 interrupt-parent = <&cpuintc>;
107 interrupt-controller;
108 #interrupt-cells = <1>;
111 rst: reset-controller@1806001c {
112 compatible = "qca,ar7100-reset";
113 reg = <0x1806001c 0x4>;
119 eth0: ethernet@19000000 {
120 compatible = "qca,ar9330-eth";
121 reg = <0x19000000 0x200>;
124 resets = <&rst 9>, <&rst 22>;
125 reset-names = "mac", "mdio";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
127 clock-names = "eth", "mdio";
130 phy-handle = <&phy_port4>;
135 eth1: ethernet@1a000000 {
136 compatible = "qca,ar9330-eth";
137 reg = <0x1a000000 0x200>;
139 resets = <&rst 13>, <&rst 23>;
140 reset-names = "mac", "mdio";
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
142 clock-names = "eth", "mdio";
155 #address-cells = <1>;
158 switch10: switch@10 {
159 #address-cells = <1>;
162 compatible = "qca,ar9331-switch";
165 reset-names = "switch";
167 interrupt-parent = <&miscintc>;
170 interrupt-controller;
171 #interrupt-cells = <1>;
174 #address-cells = <1>;
177 switch_port0: port@0 {
191 switch_port1: port@1 {
193 phy-handle = <&phy_port0>;
194 phy-mode = "internal";
199 switch_port2: port@2 {
201 phy-handle = <&phy_port1>;
202 phy-mode = "internal";
207 switch_port3: port@3 {
209 phy-handle = <&phy_port2>;
210 phy-mode = "internal";
215 switch_port4: port@4 {
217 phy-handle = <&phy_port3>;
218 phy-mode = "internal";
225 #address-cells = <1>;
228 interrupt-parent = <&switch10>;
265 compatible = "chipidea,usb2";
266 reg = <0x1b000000 0x200>;
271 phy-names = "usb-phy";
278 compatible = "qca,ar7100-spi";
279 reg = <0x1f000000 0x10>;
281 clocks = <&pll ATH79_CLK_AHB>;
284 #address-cells = <1>;
292 compatible = "qca,ar7100-usb-phy";
294 reset-names = "phy", "suspend-override";
295 resets = <&rst 4>, <&rst 3>;