1 #include <dt-bindings/clock/ath79-clk.h>
4 compatible = "qca,ar9132";
15 compatible = "mips,mips24Kc";
16 clocks = <&pll ATH79_CLK_CPU>;
21 cpuintc: interrupt-controller {
22 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 #interrupt-cells = <1>;
27 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
28 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
29 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
33 compatible = "simple-bus";
39 interrupt-parent = <&cpuintc>;
42 compatible = "simple-bus";
48 interrupt-parent = <&miscintc>;
50 ddr_ctrl: memory-controller@18000000 {
51 compatible = "qca,ar9132-ddr-controller",
52 "qca,ar7240-ddr-controller";
53 reg = <0x18000000 0x100>;
55 #qca,ddr-wb-channel-cells = <1>;
59 compatible = "ns8250";
60 reg = <0x18020000 0x20>;
63 clocks = <&pll ATH79_CLK_AHB>;
74 compatible = "qca,ar9132-gpio",
76 reg = <0x18040000 0x30>;
85 #interrupt-cells = <2>;
88 pll: pll-controller@18050000 {
89 compatible = "qca,ar9132-pll",
91 reg = <0x18050000 0x20>;
94 /* The board must provides the ref clock */
97 clock-output-names = "cpu", "ddr", "ahb";
101 compatible = "qca,ar7130-wdt";
102 reg = <0x18060008 0x8>;
106 clocks = <&pll ATH79_CLK_AHB>;
110 miscintc: interrupt-controller@18060010 {
111 compatible = "qca,ar9132-misc-intc",
112 "qca,ar7100-misc-intc";
113 reg = <0x18060010 0x8>;
115 interrupt-parent = <&cpuintc>;
118 interrupt-controller;
119 #interrupt-cells = <1>;
122 rst: reset-controller@1806001c {
123 compatible = "qca,ar9132-reset",
125 reg = <0x1806001c 0x4>;
132 compatible = "qca,ar7100-ehci", "generic-ehci";
133 reg = <0x1b000100 0x100>;
138 has-transaction-translator;
147 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
148 reg = <0x1f000000 0x10>;
150 clocks = <&pll ATH79_CLK_AHB>;
155 #address-cells = <1>;
161 compatible = "qca,ar7100-usb-phy";
163 reset-names = "usb-phy", "usb-suspend-override";
164 resets = <&rst 4>, <&rst 3>;