arm64: dts: qcom: sm8550: add TRNG node
[linux-modified.git] / arch / mips / boot / dts / ingenic / cu1830-neo.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include "x1830.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8
9 / {
10         compatible = "yna,cu1830-neo", "ingenic,x1830";
11         model = "YSH & ATIL General Board CU1830-Neo";
12
13         aliases {
14                 serial1 = &uart1;
15         };
16
17         chosen {
18                 stdout-path = "serial1:115200n8";
19         };
20
21         memory {
22                 device_type = "memory";
23                 reg = <0x0 0x08000000>;
24         };
25
26         leds {
27                 compatible = "gpio-leds";
28                 led-0 {
29                         gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
30                         linux,default-trigger = "mmc0";
31                 };
32         };
33
34         wlan_pwrseq: msc1-pwrseq {
35                 compatible = "mmc-pwrseq-simple";
36
37                 reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
38                 post-power-on-delay-ms = <200>;
39         };
40 };
41
42 &exclk {
43         clock-frequency = <24000000>;
44 };
45
46 &cgu {
47         /*
48          * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
49          * precision.
50          */
51         assigned-clocks = <&cgu X1830_CLK_RTC>;
52         assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
53 };
54
55 &ost {
56         /* 1500 kHz for the system timer and clocksource */
57         assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
58         assigned-clock-rates = <1500000>, <1500000>;
59 };
60
61 &uart1 {
62         status = "okay";
63
64         pinctrl-names = "default";
65         pinctrl-0 = <&pins_uart1>;
66 };
67
68 &ssi0 {
69         status = "okay";
70
71         num-cs = <2>;
72
73         pinctrl-names = "default";
74         pinctrl-0 = <&pins_ssi0>;
75
76         sc16is752: expander@0 {
77                 compatible = "nxp,sc16is752";
78                 reg = <0>; /* CE0 */
79
80                 spi-rx-bus-width = <1>;
81                 spi-tx-bus-width = <1>;
82                 spi-max-frequency = <4000000>;
83
84                 clocks = <&exclk_sc16is752>;
85
86                 interrupt-parent = <&gpb>;
87                 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
88
89                 gpio-controller;
90                 #gpio-cells = <2>;
91
92                 exclk_sc16is752: sc16is752 {
93                         compatible = "fixed-clock";
94                         #clock-cells = <0>;
95                         clock-frequency = <48000000>;
96                 };
97         };
98 };
99
100 &i2c0 {
101         status = "okay";
102
103         clock-frequency = <400000>;
104
105         pinctrl-names = "default";
106         pinctrl-0 = <&pins_i2c0>;
107
108         ads7830: adc@48 {
109                 compatible = "ti,ads7830";
110                 reg = <0x48>;
111         };
112 };
113
114 &dtrng {
115         status = "okay";
116 };
117
118 &msc0 {
119         status = "okay";
120
121         bus-width = <4>;
122         max-frequency = <50000000>;
123
124         pinctrl-names = "default";
125         pinctrl-0 = <&pins_msc0>;
126
127         non-removable;
128 };
129
130 &msc1 {
131         status = "okay";
132
133         #address-cells = <1>;
134         #size-cells = <0>;
135         bus-width = <4>;
136         max-frequency = <50000000>;
137
138         pinctrl-names = "default";
139         pinctrl-0 = <&pins_msc1>;
140
141         non-removable;
142
143         mmc-pwrseq = <&wlan_pwrseq>;
144
145         ap6212a: wifi@1 {
146                 compatible = "brcm,bcm4329-fmac";
147                 reg = <1>;
148
149                 interrupt-parent = <&gpc>;
150                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
151                 interrupt-names = "host-wake";
152
153                 brcm,drive-strength = <10>;
154         };
155 };
156
157 &mac {
158         status = "okay";
159
160         phy-mode = "rmii";
161         phy-handle = <&ip101gr>;
162
163         pinctrl-names = "default";
164         pinctrl-0 = <&pins_mac>;
165
166         snps,reset-gpio = <&gpb 28 GPIO_ACTIVE_LOW>; /* PB28 */
167         snps,reset-active-low;
168         snps,reset-delays-us = <0 10000 30000>;
169 };
170
171 &mdio {
172         status = "okay";
173
174         ip101gr: ethernet-phy@0 {
175                 compatible = "ethernet-phy-id0243.0c54", "ethernet-phy-ieee802.3-c22";
176                 reg = <0>;
177         };
178 };
179
180 &otg_phy {
181         status = "okay";
182 };
183
184 &otg {
185         status = "okay";
186 };
187
188 &pinctrl {
189         pins_uart1: uart1 {
190                 function = "uart1";
191                 groups = "uart1-data";
192                 bias-pull-up;
193         };
194
195         pins_ssi0: ssi0 {
196                 function = "ssi0";
197                 groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
198                 bias-disable;
199         };
200
201         pins_i2c0: i2c0 {
202                 function = "i2c0";
203                 groups = "i2c0-data";
204                 bias-pull-up;
205         };
206
207         pins_msc0: msc0 {
208                 function = "mmc0";
209                 groups = "mmc0-1bit", "mmc0-4bit";
210                 bias-disable;
211         };
212
213         pins_msc1: msc1 {
214                 function = "mmc1";
215                 groups = "mmc1-1bit", "mmc1-4bit";
216                 bias-disable;
217         };
218
219         pins_mac: mac {
220                 function = "mac";
221                 groups = "mac";
222                 bias-disable;
223         };
224 };