arch/mips/boot/dts/img/pistachio.dtsi

   1 /*
   2  * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
   3  * Copyright (C) 2015 Google, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <dt-bindings/clock/pistachio-clk.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/mips-gic.h>
  14 #include <dt-bindings/reset/pistachio-resets.h>
  15
  16 / {
  17         compatible = "img,pistachio";
  18
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         interrupt-parent = <&gic>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "mti,interaptiv";
  31                         reg = <0>;
  32                         clocks = <&clk_core CLK_MIPS_PLL>;
  33                         clock-names = "cpu";
  34                         clock-latency = <1000>;
  35                         operating-points = <
  36                                 /* kHz    uV(dummy) */
  37                                 546000 1150000
  38                                 520000 1100000
  39                                 494000 1000000
  40                                 468000 950000
  41                                 442000 900000
  42                                 416000 800000
  43                         >;
  44                 };
  45         };
  46
  47         i2c0: i2c@18100000 {
  48                 compatible = "img,scb-i2c";
  49                 reg = <0x18100000 0x200>;
  50                 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
  51                 clocks = <&clk_periph PERIPH_CLK_I2C0>,
  52                          <&cr_periph SYS_CLK_I2C0>;
  53                 clock-names = "scb", "sys";
  54                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
  55                                   <&clk_periph PERIPH_CLK_I2C0_DIV>;
  56                 assigned-clock-rates = <100000000>, <33333334>;
  57                 status = "disabled";
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&i2c0_pins>;
  60
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63         };
  64
  65         i2c1: i2c@18100200 {
  66                 compatible = "img,scb-i2c";
  67                 reg = <0x18100200 0x200>;
  68                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
  69                 clocks = <&clk_periph PERIPH_CLK_I2C1>,
  70                          <&cr_periph SYS_CLK_I2C1>;
  71                 clock-names = "scb", "sys";
  72                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
  73                                   <&clk_periph PERIPH_CLK_I2C1_DIV>;
  74                 assigned-clock-rates = <100000000>, <33333334>;
  75                 status = "disabled";
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&i2c1_pins>;
  78
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81         };
  82
  83         i2c2: i2c@18100400 {
  84                 compatible = "img,scb-i2c";
  85                 reg = <0x18100400 0x200>;
  86                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
  87                 clocks = <&clk_periph PERIPH_CLK_I2C2>,
  88                          <&cr_periph SYS_CLK_I2C2>;
  89                 clock-names = "scb", "sys";
  90                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
  91                                   <&clk_periph PERIPH_CLK_I2C2_DIV>;
  92                 assigned-clock-rates = <100000000>, <33333334>;
  93                 status = "disabled";
  94                 pinctrl-names = "default";
  95                 pinctrl-0 = <&i2c2_pins>;
  96
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99         };
 100
 101         i2c3: i2c@18100600 {
 102                 compatible = "img,scb-i2c";
 103                 reg = <0x18100600 0x200>;
 104                 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 105                 clocks = <&clk_periph PERIPH_CLK_I2C3>,
 106                          <&cr_periph SYS_CLK_I2C3>;
 107                 clock-names = "scb", "sys";
 108                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
 109                                   <&clk_periph PERIPH_CLK_I2C3_DIV>;
 110                 assigned-clock-rates = <100000000>, <33333334>;
 111                 status = "disabled";
 112                 pinctrl-names = "default";
 113                 pinctrl-0 = <&i2c3_pins>;
 114
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117         };
 118
 119         i2s_in: i2s-in@18100800 {
 120                 compatible = "img,i2s-in";
 121                 reg = <0x18100800 0x200>;
 122                 interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
 123                 dmas = <&mdc 30 0xffffffff 0>;
 124                 dma-names = "rx";
 125                 clocks = <&cr_periph SYS_CLK_I2S_IN>;
 126                 clock-names = "sys";
 127                 img,i2s-channels = <6>;
 128                 pinctrl-names = "default";
 129                 pinctrl-0 = <&i2s_in_pins>;
 130                 status = "disabled";
 131
 132                 #sound-dai-cells = <0>;
 133         };
 134
 135         i2s_out: i2s-out@18100a00 {
 136                 compatible = "img,i2s-out";
 137                 reg = <0x18100a00 0x200>;
 138                 interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
 139                 dmas = <&mdc 23 0xffffffff 0>;
 140                 dma-names = "tx";
 141                 clocks = <&cr_periph SYS_CLK_I2S_OUT>,
 142                          <&clk_core CLK_I2S>;
 143                 clock-names = "sys", "ref";
 144                 assigned-clocks = <&clk_core CLK_I2S_DIV>;
 145                 assigned-clock-rates = <12288000>;
 146                 img,i2s-channels = <6>;
 147                 pinctrl-names = "default";
 148                 pinctrl-0 = <&i2s_out_pins>;
 149                 status = "disabled";
 150                 resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
 151                 reset-names = "rst";
 152                 #sound-dai-cells = <0>;
 153         };
 154
 155         parallel_out: parallel-audio-out@18100c00 {
 156                 compatible = "img,parallel-out";
 157                 reg = <0x18100c00 0x100>;
 158                 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
 159                 dmas = <&mdc 16 0xffffffff 0>;
 160                 dma-names = "tx";
 161                 clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
 162                          <&clk_core CLK_AUDIO_DAC>;
 163                 clock-names = "sys", "ref";
 164                 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
 165                 assigned-clock-rates = <12288000>;
 166                 status = "disabled";
 167                 resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
 168                 reset-names = "rst";
 169                 #sound-dai-cells = <0>;
 170         };
 171
 172         spdif_out: spdif-out@18100d00 {
 173                 compatible = "img,spdif-out";
 174                 reg = <0x18100d00 0x100>;
 175                 interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
 176                 dmas = <&mdc 14 0xffffffff 0>;
 177                 dma-names = "tx";
 178                 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
 179                          <&clk_core CLK_SPDIF>;
 180                 clock-names = "sys", "ref";
 181                 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
 182                 assigned-clock-rates = <12288000>;
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&spdif_out_pin>;
 185                 status = "disabled";
 186                 resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
 187                 reset-names = "rst";
 188                 #sound-dai-cells = <0>;
 189         };
 190
 191         spdif_in: spdif-in@18100e00 {
 192                 compatible = "img,spdif-in";
 193                 reg = <0x18100e00 0x100>;
 194                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 195                 dmas = <&mdc 15 0xffffffff 0>;
 196                 dma-names = "rx";
 197                 clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
 198                 clock-names = "sys";
 199                 pinctrl-names = "default";
 200                 pinctrl-0 = <&spdif_in_pin>;
 201                 status = "disabled";
 202
 203                 #sound-dai-cells = <0>;
 204         };
 205
 206         internal_dac: internal-dac {
 207                 compatible = "img,pistachio-internal-dac";
 208                 img,cr-top = <&cr_top>;
 209                 img,voltage-select = <1>;
 210
 211                 #sound-dai-cells = <0>;
 212         };
 213
 214         spfi0: spi@18100f00 {
 215                 compatible = "img,spfi";
 216                 reg = <0x18100f00 0x100>;
 217                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
 219                 clock-names = "sys", "spfi";
 220                 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
 221                 dma-names = "rx", "tx";
 222                 spfi-max-frequency = <50000000>;
 223                 status = "disabled";
 224
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227         };
 228
 229         spfi1: spi@18101000 {
 230                 compatible = "img,spfi";
 231                 reg = <0x18101000 0x100>;
 232                 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
 234                 clock-names = "sys", "spfi";
 235                 dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
 236                 dma-names = "rx", "tx";
 237                 img,supports-quad-mode;
 238                 spfi-max-frequency = <50000000>;
 239                 status = "disabled";
 240
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243         };
 244
 245         pwm: pwm@18101300 {
 246                 compatible = "img,pistachio-pwm";
 247                 reg = <0x18101300 0x100>;
 248                 clocks = <&clk_periph PERIPH_CLK_PWM>,
 249                          <&cr_periph SYS_CLK_PWM>;
 250                 clock-names = "pwm", "sys";
 251                 img,cr-periph = <&cr_periph>;
 252                 #pwm-cells = <2>;
 253                 status = "disabled";
 254         };
 255
 256         uart0: uart@18101400 {
 257                 compatible = "snps,dw-apb-uart";
 258                 reg = <0x18101400 0x100>;
 259                 interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
 261                 clock-names = "baudclk", "apb_pclk";
 262                 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
 263                                   <&clk_core CLK_UART0_DIV>;
 264                 reg-shift = <2>;
 265                 reg-io-width = <4>;
 266                 pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
 267                 pinctrl-names = "default";
 268                 status = "disabled";
 269         };
 270
 271         uart1: uart@18101500 {
 272                 compatible = "snps,dw-apb-uart";
 273                 reg = <0x18101500 0x100>;
 274                 interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 275                 clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
 276                 clock-names = "baudclk", "apb_pclk";
 277                 assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
 278                                   <&clk_core CLK_UART1_DIV>;
 279                 assigned-clock-rates = <114278400>, <1843200>;
 280                 reg-shift = <2>;
 281                 reg-io-width = <4>;
 282                 pinctrl-0 = <&uart1_pins>;
 283                 pinctrl-names = "default";
 284                 status = "disabled";
 285         };
 286
 287         adc: adc@18101600 {
 288                 compatible = "cosmic,10001-adc";
 289                 reg = <0x18101600 0x24>;
 290                 adc-reserved-channels = <0x30>;
 291                 clocks = <&clk_core CLK_AUX_ADC>;
 292                 clock-names = "adc";
 293                 assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
 294                                   <&clk_core CLK_AUX_ADC_DIV>;
 295                 assigned-clock-rates = <100000000>, <1000000>;
 296                 status = "disabled";
 297
 298                 #io-channel-cells = <1>;
 299         };
 300
 301         pinctrl: pinctrl@18101c00 {
 302                 compatible = "img,pistachio-system-pinctrl";
 303                 reg = <0x18101c00 0x400>;
 304
 305                 gpio0: gpio0 {
 306                         interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
 307
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                         gpio-ranges = <&pinctrl 0 0 16>;
 311
 312                         interrupt-controller;
 313                         #interrupt-cells = <2>;
 314                 };
 315
 316                 gpio1: gpio1 {
 317                         interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
 318
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321                         gpio-ranges = <&pinctrl 0 16 16>;
 322
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                 };
 326
 327                 gpio2: gpio2 {
 328                         interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
 329
 330                         gpio-controller;
 331                         #gpio-cells = <2>;
 332                         gpio-ranges = <&pinctrl 0 32 16>;
 333
 334                         interrupt-controller;
 335                         #interrupt-cells = <2>;
 336                 };
 337
 338                 gpio3: gpio3 {
 339                         interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
 340
 341                         gpio-controller;
 342                         #gpio-cells = <2>;
 343                         gpio-ranges = <&pinctrl 0 48 16>;
 344
 345                         interrupt-controller;
 346                         #interrupt-cells = <2>;
 347                 };
 348
 349                 gpio4: gpio4 {
 350                         interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
 351
 352                         gpio-controller;
 353                         #gpio-cells = <2>;
 354                         gpio-ranges = <&pinctrl 0 64 16>;
 355
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                 };
 359
 360                 gpio5: gpio5 {
 361                         interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
 362
 363                         gpio-controller;
 364                         #gpio-cells = <2>;
 365                         gpio-ranges = <&pinctrl 0 80 10>;
 366
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                 };
 370
 371                 i2c0_pins: i2c0-pins {
 372                         pin_i2c0: i2c0 {
 373                                 pins = "mfio28", "mfio29";
 374                                 function = "i2c0";
 375                                 drive-strength = <4>;
 376                         };
 377                 };
 378
 379                 i2c1_pins: i2c1-pins {
 380                         pin_i2c1: i2c1 {
 381                                 pins = "mfio30", "mfio31";
 382                                 function = "i2c1";
 383                                 drive-strength = <4>;
 384                         };
 385                 };
 386
 387                 i2c2_pins: i2c2-pins {
 388                         pin_i2c2: i2c2 {
 389                                 pins = "mfio32", "mfio33";
 390                                 function = "i2c2";
 391                                 drive-strength = <4>;
 392                         };
 393                 };
 394
 395                 i2c3_pins: i2c3-pins {
 396                         pin_i2c3: i2c3 {
 397                                 pins = "mfio34", "mfio35";
 398                                 function = "i2c3";
 399                                 drive-strength = <4>;
 400                         };
 401                 };
 402
 403                 spim0_pins: spim0-pins {
 404                         pin_spim0: spim0 {
 405                                 pins = "mfio9", "mfio10";
 406                                 function = "spim0";
 407                                 drive-strength = <4>;
 408                         };
 409                         spim0_clk: spim0-clk {
 410                                 pins = "mfio8";
 411                                 function = "spim0";
 412                                 drive-strength = <4>;
 413                         };
 414                 };
 415
 416                 spim0_cs0_alt_pin: spim0-cs0-alt-pin {
 417                         spim0-cs0 {
 418                                 pins = "mfio2";
 419                                 drive-strength = <2>;
 420                         };
 421                 };
 422
 423                 spim0_cs1_pin: spim0-cs1-pin {
 424                         spim0-cs1 {
 425                                 pins = "mfio1";
 426                                 drive-strength = <2>;
 427                         };
 428                 };
 429
 430                 spim0_cs2_pin: spim0-cs2-pin {
 431                         spim0-cs2 {
 432                                 pins = "mfio55";
 433                                 drive-strength = <2>;
 434                         };
 435                 };
 436
 437                 spim0_cs2_alt_pin: spim0-cs2-alt-pin {
 438                         spim0-cs2 {
 439                                 pins = "mfio28";
 440                                 drive-strength = <2>;
 441                         };
 442                 };
 443
 444                 spim0_cs3_pin: spim0-cs3-pin {
 445                         spim0-cs3 {
 446                                 pins = "mfio56";
 447                                 drive-strength = <2>;
 448                         };
 449                 };
 450
 451                 spim0_cs3_alt_pin: spim0-cs3-alt-pin {
 452                         spim0-cs3 {
 453                                 pins = "mfio29";
 454                                 drive-strength = <2>;
 455                         };
 456                 };
 457
 458                 spim0_cs4_pin: spim0-cs4-pin {
 459                         spim0-cs4 {
 460                                 pins = "mfio57";
 461                                 drive-strength = <2>;
 462                         };
 463                 };
 464
 465                 spim0_cs4_alt_pin: spim0-cs4-alt-pin {
 466                         spim0-cs4 {
 467                                 pins = "mfio30";
 468                                 drive-strength = <2>;
 469                         };
 470                 };
 471
 472                 spim1_pins: spim1-pins {
 473                         spim1 {
 474                                 pins = "mfio3", "mfio4", "mfio5";
 475                                 function = "spim1";
 476                                 drive-strength = <2>;
 477                         };
 478                 };
 479
 480                 spim1_quad_pins: spim1-quad-pins {
 481                         spim1-quad {
 482                                 pins = "mfio6", "mfio7";
 483                                 function = "spim1";
 484                                 drive-strength = <2>;
 485                         };
 486                 };
 487
 488                 spim1_cs0_pin: spim1-cs0-pins {
 489                         spim1-cs0 {
 490                                 pins = "mfio0";
 491                                 function = "spim1";
 492                                 drive-strength = <2>;
 493                         };
 494                 };
 495
 496                 spim1_cs1_pin: spim1-cs1-pin {
 497                         spim1-cs1 {
 498                                 pins = "mfio1";
 499                                 function = "spim1";
 500                                 drive-strength = <2>;
 501                         };
 502                 };
 503
 504                 spim1_cs1_alt_pin: spim1-cs1-alt-pin {
 505                         spim1-cs1 {
 506                                 pins = "mfio58";
 507                                 function = "spim1";
 508                                 drive-strength = <2>;
 509                         };
 510                 };
 511
 512                 spim1_cs2_pin: spim1-cs2-pin {
 513                         spim1-cs2 {
 514                                 pins = "mfio2";
 515                                 function = "spim1";
 516                                 drive-strength = <2>;
 517                         };
 518                 };
 519
 520                 spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
 521                         spim1-cs2 {
 522                                 pins = "mfio31";
 523                                 function = "spim1";
 524                                 drive-strength = <2>;
 525                         };
 526                 };
 527
 528                 spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
 529                         spim1-cs2 {
 530                                 pins = "mfio55";
 531                                 function = "spim1";
 532                                 drive-strength = <2>;
 533                         };
 534                 };
 535
 536                 spim1_cs3_pin: spim1-cs3-pin {
 537                         spim1-cs3 {
 538                                 pins = "mfio56";
 539                                 function = "spim1";
 540                                 drive-strength = <2>;
 541                         };
 542                 };
 543
 544                 spim1_cs4_pin: spim1-cs4-pin {
 545                         spim1-cs4 {
 546                                 pins = "mfio57";
 547                                 function = "spim1";
 548                                 drive-strength = <2>;
 549                         };
 550                 };
 551
 552                 uart0_pins: uart0-pins {
 553                         uart0 {
 554                                 pins = "mfio55", "mfio56";
 555                                 function = "uart0";
 556                                 drive-strength = <2>;
 557                         };
 558                 };
 559
 560                 uart0_rts_cts_pins: uart0-rts-cts-pins {
 561                         uart0-rts-cts {
 562                                 pins = "mfio57", "mfio58";
 563                                 function = "uart0";
 564                                 drive-strength = <2>;
 565                         };
 566                 };
 567
 568                 uart1_pins: uart1-pins {
 569                         uart1 {
 570                                 pins = "mfio59", "mfio60";
 571                                 function = "uart1";
 572                                 drive-strength = <2>;
 573                         };
 574                 };
 575
 576                 uart1_rts_cts_pins: uart1-rts-cts-pins {
 577                         uart1-rts-cts {
 578                                   pins = "mfio1", "mfio2";
 579                                   function = "uart1";
 580                                   drive-strength = <2>;
 581                         };
 582                 };
 583
 584                 enet_pins: enet-pins {
 585                         pin_enet: enet {
 586                                 pins = "mfio63", "mfio64", "mfio65", "mfio66",
 587                                        "mfio67", "mfio68", "mfio69", "mfio70";
 588                                 function = "eth";
 589                                 slew-rate = <1>;
 590                                 drive-strength = <4>;
 591                         };
 592                         pin_enet_phy_clk: enet-phy-clk {
 593                                 pins = "mfio71";
 594                                 function = "eth";
 595                                 slew-rate = <1>;
 596                                 drive-strength = <8>;
 597                         };
 598                 };
 599
 600                 sdhost_pins: sdhost-pins {
 601                         pin_sdhost_clk: sdhost-clk {
 602                                 pins = "mfio15";
 603                                 function = "sdhost";
 604                                 slew-rate = <1>;
 605                                 drive-strength = <4>;
 606                         };
 607                         pin_sdhost_cmd: sdhost-cmd {
 608                                 pins = "mfio16";
 609                                 function = "sdhost";
 610                                 slew-rate = <1>;
 611                                 drive-strength = <4>;
 612                         };
 613                         pin_sdhost_data: sdhost-data {
 614                                 pins = "mfio17", "mfio18", "mfio19", "mfio20",
 615                                        "mfio21", "mfio22", "mfio23", "mfio24";
 616                                 function = "sdhost";
 617                                 slew-rate = <1>;
 618                                 drive-strength = <4>;
 619                         };
 620                         pin_sdhost_power_select: sdhost-power-select {
 621                                 pins = "mfio25";
 622                                 function = "sdhost";
 623                                 slew-rate = <1>;
 624                                 drive-strength = <2>;
 625                         };
 626                         pin_sdhost_card_detect: sdhost-card-detect {
 627                                 pins = "mfio26";
 628                                 function = "sdhost";
 629                                 drive-strength = <2>;
 630                         };
 631                         pin_sdhost_write_protect: sdhost-write-protect {
 632                                 pins = "mfio27";
 633                                 function = "sdhost";
 634                                 drive-strength = <2>;
 635                         };
 636                 };
 637
 638                 ir_pin: ir-pin {
 639                         ir-data {
 640                                 pins = "mfio72";
 641                                 function = "ir";
 642                                 drive-strength = <2>;
 643                         };
 644                 };
 645
 646                 pwmpdm0_pin: pwmpdm0-pin {
 647                         pwmpdm0 {
 648                                 pins = "mfio73";
 649                                 function = "pwmpdm";
 650                                 drive-strength = <2>;
 651                         };
 652                 };
 653
 654                 pwmpdm1_pin: pwmpdm1-pin {
 655                         pwmpdm1 {
 656                                 pins = "mfio74";
 657                                 function = "pwmpdm";
 658                                 drive-strength = <2>;
 659                         };
 660                 };
 661
 662                 pwmpdm2_pin: pwmpdm2-pin {
 663                         pwmpdm2 {
 664                                 pins = "mfio75";
 665                                 function = "pwmpdm";
 666                                 drive-strength = <2>;
 667                         };
 668                 };
 669
 670                 pwmpdm3_pin: pwmpdm3-pin {
 671                         pwmpdm3 {
 672                                 pins = "mfio76";
 673                                 function = "pwmpdm";
 674                                 drive-strength = <2>;
 675                         };
 676                 };
 677
 678                 dac_clk_pin: dac-clk-pin {
 679                         pin_dac_clk: dac-clk {
 680                                 pins = "mfio45";
 681                                 function = "i2s_dac_clk";
 682                                 drive-strength = <4>;
 683                         };
 684                 };
 685
 686                 i2s_mclk_pin: i2s-mclk-pin {
 687                         pin_i2s_mclk: i2s-mclk {
 688                                 pins = "mfio36";
 689                                 function = "i2s_out";
 690                                 drive-strength = <4>;
 691                         };
 692                 };
 693
 694                 spdif_out_pin: spdif-out-pin {
 695                         spdif-out {
 696                                 pins = "mfio61";
 697                                 function = "spdif_out";
 698                                 slew-rate = <1>;
 699                                 drive-strength = <2>;
 700                         };
 701                 };
 702
 703                 spdif_in_pin: spdif-in-pin {
 704                         spdif-in {
 705                                 pins = "mfio62";
 706                                 function = "spdif_in";
 707                                 drive-strength = <2>;
 708                         };
 709                 };
 710
 711                 i2s_out_pins: i2s-out-pins {
 712                         pins_i2s_out_clk: i2s-out-clk {
 713                                 pins = "mfio37", "mfio38";
 714                                 function = "i2s_out";
 715                                 drive-strength = <4>;
 716                         };
 717                         pins_i2s_out: i2s-out {
 718                                 pins = "mfio39", "mfio40",
 719                                        "mfio41", "mfio42",
 720                                        "mfio43", "mfio44";
 721                                 function = "i2s_out";
 722                                 drive-strength = <2>;
 723                         };
 724                 };
 725
 726                 i2s_in_pins: i2s-in-pins {
 727                         i2s-in {
 728                                 pins = "mfio47", "mfio48", "mfio49",
 729                                        "mfio50", "mfio51", "mfio52",
 730                                        "mfio53", "mfio54";
 731                                 function = "i2s_in";
 732                                 drive-strength = <2>;
 733                         };
 734                 };
 735         };
 736
 737         timer: timer@18102000 {
 738                 compatible = "img,pistachio-gptimer";
 739                 reg = <0x18102000 0x100>;
 740                 interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
 742                          <&cr_periph SYS_CLK_TIMER>;
 743                 clock-names = "fast", "sys";
 744                 img,cr-periph = <&cr_periph>;
 745         };
 746
 747         wdt: watchdog@18102100 {
 748                 compatible = "img,pdc-wdt";
 749                 reg = <0x18102100 0x100>;
 750                 interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
 751                 clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
 752                 clock-names = "wdt", "sys";
 753                 assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
 754                                   <&clk_periph PERIPH_CLK_WD_DIV>;
 755                 assigned-clock-rates = <4000000>, <32768>;
 756         };
 757
 758         ir: ir@18102200 {
 759                 compatible = "img,ir-rev1";
 760                 reg = <0x18102200 0x100>;
 761                 interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
 763                 clock-names = "core", "sys";
 764                 assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
 765                                   <&clk_periph PERIPH_CLK_IR_DIV>;
 766                 assigned-clock-rates = <4000000>, <32768>;
 767                 pinctrl-0 = <&ir_pin>;
 768                 pinctrl-names = "default";
 769                 status = "disabled";
 770         };
 771
 772         usb: usb@18120000 {
 773                 compatible = "snps,dwc2";
 774                 reg = <0x18120000 0x1c000>;
 775                 interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
 776                 phys = <&usb_phy>;
 777                 phy-names = "usb2-phy";
 778                 g-tx-fifo-size = <256 256 256 256>;
 779                 status = "disabled";
 780         };
 781
 782         enet: ethernet@18140000 {
 783                 compatible = "snps,dwmac";
 784                 reg = <0x18140000 0x2000>;
 785                 interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
 786                 interrupt-names = "macirq";
 787                 clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
 788                 clock-names = "stmmaceth", "pclk";
 789                 assigned-clocks = <&clk_core CLK_ENET_MUX>,
 790                                   <&clk_core CLK_ENET_DIV>;
 791                 assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
 792                 assigned-clock-rates = <0>, <50000000>;
 793                 pinctrl-0 = <&enet_pins>;
 794                 pinctrl-names = "default";
 795                 phy-mode = "rmii";
 796                 status = "disabled";
 797         };
 798
 799         sdhost: mmc@18142000 {
 800                 compatible = "img,pistachio-dw-mshc";
 801                 reg = <0x18142000 0x400>;
 802                 interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
 803                 clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
 804                 clock-names = "ciu", "biu";
 805                 pinctrl-0 = <&sdhost_pins>;
 806                 pinctrl-names = "default";
 807                 fifo-depth = <0x20>;
 808                 num-slots = <1>;
 809                 clock-frequency = <50000000>;
 810                 bus-width = <8>;
 811                 cap-mmc-highspeed;
 812                 cap-sd-highspeed;
 813                 status = "disabled";
 814         };
 815
 816         sram: sram@1b000000 {
 817                 compatible = "mmio-sram";
 818                 reg = <0x1b000000 0x10000>;
 819         };
 820
 821         mdc: dma-controller@18143000 {
 822                 compatible = "img,pistachio-mdc-dma";
 823                 reg = <0x18143000 0x1000>;
 824                 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
 825                              <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
 826                              <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
 827                              <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
 828                              <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
 829                              <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
 830                              <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
 831                              <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
 832                              <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
 833                              <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
 834                              <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
 836                 clocks = <&cr_periph SYS_CLK_MDC>;
 837                 clock-names = "sys";
 838
 839                 img,max-burst-multiplier = <16>;
 840                 img,cr-periph = <&cr_periph>;
 841
 842                 #dma-cells = <3>;
 843         };
 844
 845         clk_core: clk@18144000 {
 846                 compatible = "img,pistachio-clk", "syscon";
 847                 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
 848                          <&cr_top EXT_CLK_ENET_IN>;
 849                 clock-names = "xtal", "audio_refclk_ext_gate",
 850                               "ext_enet_in_gate";
 851                 reg = <0x18144000 0x800>;
 852                 #clock-cells = <1>;
 853         };
 854
 855         clk_periph: clk@18144800 {
 856                 compatible = "img,pistachio-clk-periph";
 857                 reg = <0x18144800 0x1000>;
 858                 clocks = <&clk_core CLK_PERIPH_SYS>;
 859                 clock-names = "periph_sys_core";
 860                 #clock-cells = <1>;
 861         };
 862
 863         cr_periph: clk@18148000 {
 864                 compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
 865                 reg = <0x18148000 0x1000>;
 866                 clocks = <&clk_periph PERIPH_CLK_SYS>;
 867                 clock-names = "sys";
 868                 #clock-cells = <1>;
 869
 870                 pistachio_reset: reset-controller {
 871                         compatible = "img,pistachio-reset";
 872                         #reset-cells = <1>;
 873                 };
 874         };
 875
 876         cr_top: clk@18149000 {
 877                 compatible = "img,pistachio-cr-top", "syscon";
 878                 reg = <0x18149000 0x200>;
 879                 #clock-cells = <1>;
 880         };
 881
 882         hash: hash@18149600 {
 883                 compatible = "img,hash-accelerator";
 884                 reg = <0x18149600 0x100>, <0x18101100 0x4>;
 885                 interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
 886                 dmas = <&mdc 8 0xffffffff 0>;
 887                 dma-names = "tx";
 888                 clocks = <&cr_periph SYS_CLK_HASH>,
 889                          <&clk_periph PERIPH_CLK_ROM>;
 890                 clock-names = "sys", "hash";
 891         };
 892
 893         gic: interrupt-controller@1bdc0000 {
 894                 compatible = "mti,gic";
 895                 reg = <0x1bdc0000 0x20000>;
 896
 897                 interrupt-controller;
 898                 #interrupt-cells = <3>;
 899
 900                 timer {
 901                         compatible = "mti,gic-timer";
 902                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 903                         clocks = <&clk_core CLK_MIPS>;
 904                 };
 905         };
 906
 907         usb_phy: usb-phy {
 908                 compatible = "img,pistachio-usb-phy";
 909                 clocks = <&clk_core CLK_USB_PHY>;
 910                 clock-names = "usb_phy";
 911                 assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
 912                 assigned-clock-rates = <50000000>;
 913                 img,refclk = <0x2>;
 914                 img,cr-top = <&cr_top>;
 915                 #phy-cells = <0>;
 916         };
 917
 918         xtal: xtal {
 919                 compatible = "fixed-clock";
 920                 #clock-cells = <0>;
 921                 clock-frequency = <52000000>;
 922                 clock-output-names = "xtal";
 923         };
 924 };