1 // SPDX-License-Identifier: GPL-2.0
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available
7 * devices and properties.
10 /include/ "octeon_3xxx.dtsi"
14 smi0: mdio@1180000001800 {
15 phy0: ethernet-phy@0 {
16 compatible = "marvell,88e1118";
18 /* Fix rx and tx clock transition timing */
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
20 /* Adjust LED drive. */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
28 compatible = "marvell,88e1118";
30 /* Fix rx and tx clock transition timing */
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
32 /* Adjust LED drive. */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
34 /* irq, blink-activity, blink-link */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
39 phy2: ethernet-phy@2 {
41 compatible = "marvell,88e1149r";
42 marvell,reg-init = <3 0x10 0 0x5777>,
47 phy3: ethernet-phy@3 {
49 compatible = "marvell,88e1149r";
50 marvell,reg-init = <3 0x10 0 0x5777>,
55 phy4: ethernet-phy@4 {
57 compatible = "marvell,88e1149r";
58 marvell,reg-init = <3 0x10 0 0x5777>,
63 phy5: ethernet-phy@5 {
65 compatible = "marvell,88e1149r";
66 marvell,reg-init = <3 0x10 0 0x5777>,
72 phy6: ethernet-phy@6 {
74 compatible = "marvell,88e1149r";
75 marvell,reg-init = <3 0x10 0 0x5777>,
80 phy7: ethernet-phy@7 {
82 compatible = "marvell,88e1149r";
83 marvell,reg-init = <3 0x10 0 0x5777>,
88 phy8: ethernet-phy@8 {
90 compatible = "marvell,88e1149r";
91 marvell,reg-init = <3 0x10 0 0x5777>,
96 phy9: ethernet-phy@9 {
98 compatible = "marvell,88e1149r";
99 marvell,reg-init = <3 0x10 0 0x5777>,
106 smi1: mdio@1180000001900 {
107 compatible = "cavium,octeon-3860-mdio";
108 #address-cells = <1>;
110 reg = <0x11800 0x00001900 0x0 0x40>;
112 phy100: ethernet-phy@1 {
114 compatible = "marvell,88e1149r";
115 marvell,reg-init = <3 0x10 0 0x5777>,
119 interrupt-parent = <&gpio>;
120 interrupts = <12 8>; /* Pin 12, active low */
122 phy101: ethernet-phy@2 {
124 compatible = "marvell,88e1149r";
125 marvell,reg-init = <3 0x10 0 0x5777>,
129 interrupt-parent = <&gpio>;
130 interrupts = <12 8>; /* Pin 12, active low */
132 phy102: ethernet-phy@3 {
134 compatible = "marvell,88e1149r";
135 marvell,reg-init = <3 0x10 0 0x5777>,
139 interrupt-parent = <&gpio>;
140 interrupts = <12 8>; /* Pin 12, active low */
142 phy103: ethernet-phy@4 {
144 compatible = "marvell,88e1149r";
145 marvell,reg-init = <3 0x10 0 0x5777>,
149 interrupt-parent = <&gpio>;
150 interrupts = <12 8>; /* Pin 12, active low */
154 mix0: ethernet@1070000100000 {
155 compatible = "cavium,octeon-5750-mix";
156 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
157 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
158 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
159 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
161 interrupts = <0 62>, <1 46>;
162 local-mac-address = [ 00 00 00 00 00 00 ];
163 phy-handle = <&phy0>;
166 mix1: ethernet@1070000100800 {
167 compatible = "cavium,octeon-5750-mix";
168 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
169 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
170 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
171 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
173 interrupts = <1 18>, < 1 46>;
174 local-mac-address = [ 00 00 00 00 00 00 ];
175 phy-handle = <&phy1>;
178 pip: pip@11800a0000000 {
181 phy-handle = <&phy2>;
182 cavium,alt-phy-handle = <&phy100>;
185 phy-handle = <&phy3>;
186 cavium,alt-phy-handle = <&phy101>;
189 phy-handle = <&phy4>;
190 cavium,alt-phy-handle = <&phy102>;
193 compatible = "cavium,octeon-3860-pip-port";
194 reg = <0x3>; /* Port */
195 local-mac-address = [ 00 00 00 00 00 00 ];
196 phy-handle = <&phy5>;
197 cavium,alt-phy-handle = <&phy103>;
200 compatible = "cavium,octeon-3860-pip-port";
201 reg = <0x4>; /* Port */
202 local-mac-address = [ 00 00 00 00 00 00 ];
205 compatible = "cavium,octeon-3860-pip-port";
206 reg = <0x5>; /* Port */
207 local-mac-address = [ 00 00 00 00 00 00 ];
210 compatible = "cavium,octeon-3860-pip-port";
211 reg = <0x6>; /* Port */
212 local-mac-address = [ 00 00 00 00 00 00 ];
215 compatible = "cavium,octeon-3860-pip-port";
216 reg = <0x7>; /* Port */
217 local-mac-address = [ 00 00 00 00 00 00 ];
220 compatible = "cavium,octeon-3860-pip-port";
221 reg = <0x8>; /* Port */
222 local-mac-address = [ 00 00 00 00 00 00 ];
225 compatible = "cavium,octeon-3860-pip-port";
226 reg = <0x9>; /* Port */
227 local-mac-address = [ 00 00 00 00 00 00 ];
230 compatible = "cavium,octeon-3860-pip-port";
231 reg = <0xa>; /* Port */
232 local-mac-address = [ 00 00 00 00 00 00 ];
235 compatible = "cavium,octeon-3860-pip-port";
236 reg = <0xb>; /* Port */
237 local-mac-address = [ 00 00 00 00 00 00 ];
240 compatible = "cavium,octeon-3860-pip-port";
241 reg = <0xc>; /* Port */
242 local-mac-address = [ 00 00 00 00 00 00 ];
245 compatible = "cavium,octeon-3860-pip-port";
246 reg = <0xd>; /* Port */
247 local-mac-address = [ 00 00 00 00 00 00 ];
250 compatible = "cavium,octeon-3860-pip-port";
251 reg = <0xe>; /* Port */
252 local-mac-address = [ 00 00 00 00 00 00 ];
255 compatible = "cavium,octeon-3860-pip-port";
256 reg = <0xf>; /* Port */
257 local-mac-address = [ 00 00 00 00 00 00 ];
263 compatible = "cavium,octeon-3860-pip-port";
264 reg = <0x0>; /* Port */
265 local-mac-address = [ 00 00 00 00 00 00 ];
266 phy-handle = <&phy6>;
269 compatible = "cavium,octeon-3860-pip-port";
270 reg = <0x1>; /* Port */
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 phy-handle = <&phy7>;
275 compatible = "cavium,octeon-3860-pip-port";
276 reg = <0x2>; /* Port */
277 local-mac-address = [ 00 00 00 00 00 00 ];
278 phy-handle = <&phy8>;
281 compatible = "cavium,octeon-3860-pip-port";
282 reg = <0x3>; /* Port */
283 local-mac-address = [ 00 00 00 00 00 00 ];
284 phy-handle = <&phy9>;
289 twsi0: i2c@1180000001000 {
291 compatible = "dallas,ds1337";
295 compatible = "ti,tmp421";
300 twsi1: i2c@1180000001200 {
301 #address-cells = <1>;
303 compatible = "cavium,octeon-3860-twsi";
304 reg = <0x11800 0x00001200 0x0 0x200>;
306 clock-frequency = <100000>;
309 uart1: serial@1180000000c00 {
310 compatible = "cavium,octeon-3860-uart","ns16550";
311 reg = <0x11800 0x00000c00 0x0 0x400>;
312 clock-frequency = <0>;
313 current-speed = <115200>;
318 uart2: serial@1180000000400 {
319 compatible = "cavium,octeon-3860-uart","ns16550";
320 reg = <0x11800 0x00000400 0x0 0x400>;
321 clock-frequency = <0>;
322 current-speed = <115200>;
327 bootbus: bootbus@1180000000000 {
328 led0: led-display@4,0 {
329 compatible = "avago,hdsp-253x";
330 reg = <4 0x20 0x20>, <4 0 0x20>;
333 cf0: compact-flash@5,0 {
334 compatible = "cavium,ebt3000-compact-flash";
335 reg = <5 0 0x10000>, <6 0 0x10000>;
336 cavium,bus-width = <16>;
338 cavium,dma-engine-handle = <&dma0>;
342 uctl: uctl@118006f000000 {
343 compatible = "cavium,octeon-6335-uctl";
344 reg = <0x11800 0x6f000000 0x0 0x100>;
345 ranges; /* Direct mapping */
346 #address-cells = <2>;
348 /* 12MHz, 24MHz and 48MHz allowed */
349 refclk-frequency = <12000000>;
350 /* Either "crystal" or "external" */
351 refclk-type = "crystal";
354 compatible = "cavium,octeon-6335-ehci","usb-ehci";
355 reg = <0x16f00 0x00000000 0x0 0x100>;
360 compatible = "cavium,octeon-6335-ohci","usb-ohci";
361 reg = <0x16f00 0x00000400 0x0 0x100>;
367 usbn: usbn@1180068000000 {
368 /* 12MHz, 24MHz and 48MHz allowed */
369 refclk-frequency = <12000000>;
370 /* Either "crystal" or "external" */
371 refclk-type = "crystal";