1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "brcm,bcm7435";
11 mips-hpt-frequency = <175625000>;
14 compatible = "brcm,bmips5200";
20 compatible = "brcm,bmips5200";
26 compatible = "brcm,bmips5200";
32 compatible = "brcm,bmips5200";
42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
47 #interrupt-cells = <1>;
52 compatible = "fixed-clock";
54 clock-frequency = <81000000>;
58 compatible = "fixed-clock";
60 clock-frequency = <27000000>;
68 compatible = "simple-bus";
69 ranges = <0 0x10000000 0x01000000>;
71 periph_intc: interrupt-controller@41b500 {
72 compatible = "brcm,bcm7038-l1-intc";
73 reg = <0x41b500 0x40>, <0x41b600 0x40>,
74 <0x41b700 0x40>, <0x41b800 0x40>;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
80 interrupts = <2>, <3>, <2>, <3>;
83 sun_l2_intc: interrupt-controller@403000 {
84 compatible = "brcm,l2-intc";
85 reg = <0x403000 0x30>;
87 #interrupt-cells = <1>;
88 interrupt-parent = <&periph_intc>;
93 compatible = "brcm,bcm7435-gisb-arb";
94 reg = <0x400000 0xdc>;
96 interrupt-parent = <&sun_l2_intc>;
97 interrupts = <0>, <2>;
98 brcm,gisb-arb-master-mask = <0xf77f>;
99 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
108 upg_irq0_intc: interrupt-controller@406780 {
109 compatible = "brcm,bcm7120-l2-intc";
110 reg = <0x406780 0x8>;
112 brcm,int-map-mask = <0x44>, <0x7000000>;
113 brcm,int-fwd-mask = <0x70000>;
115 interrupt-controller;
116 #interrupt-cells = <1>;
118 interrupt-parent = <&periph_intc>;
119 interrupts = <60>, <58>;
120 interrupt-names = "upg_main", "upg_bsc";
123 upg_aon_irq0_intc: interrupt-controller@409480 {
124 compatible = "brcm,bcm7120-l2-intc";
125 reg = <0x409480 0x8>;
127 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
128 brcm,int-fwd-mask = <0>;
131 interrupt-controller;
132 #interrupt-cells = <1>;
134 interrupt-parent = <&periph_intc>;
135 interrupts = <61>, <59>, <64>;
136 interrupt-names = "upg_main_aon", "upg_bsc_aon",
140 sun_top_ctrl: syscon@404000 {
141 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
142 reg = <0x404000 0x51c>;
147 compatible = "brcm,brcmstb-reboot";
148 syscon = <&sun_top_ctrl 0x304 0x308>;
151 uart0: serial@406b00 {
152 compatible = "ns16550a";
153 reg = <0x406b00 0x20>;
154 reg-io-width = <0x4>;
156 interrupt-parent = <&periph_intc>;
158 clocks = <&uart_clk>;
162 uart1: serial@406b40 {
163 compatible = "ns16550a";
164 reg = <0x406b40 0x20>;
165 reg-io-width = <0x4>;
167 interrupt-parent = <&periph_intc>;
169 clocks = <&uart_clk>;
173 uart2: serial@406b80 {
174 compatible = "ns16550a";
175 reg = <0x406b80 0x20>;
176 reg-io-width = <0x4>;
178 interrupt-parent = <&periph_intc>;
180 clocks = <&uart_clk>;
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
190 interrupt-names = "upg_bsca";
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
198 reg = <0x409400 0x58>;
200 interrupt-names = "upg_bscb";
205 clock-frequency = <390000>;
206 compatible = "brcm,brcmstb-i2c";
207 interrupt-parent = <&upg_irq0_intc>;
208 reg = <0x406200 0x58>;
210 interrupt-names = "upg_bscc";
215 clock-frequency = <390000>;
216 compatible = "brcm,brcmstb-i2c";
217 interrupt-parent = <&upg_irq0_intc>;
218 reg = <0x406280 0x58>;
220 interrupt-names = "upg_bscd";
225 clock-frequency = <390000>;
226 compatible = "brcm,brcmstb-i2c";
227 interrupt-parent = <&upg_aon_irq0_intc>;
228 reg = <0x409180 0x58>;
230 interrupt-names = "upg_bsce";
235 compatible = "brcm,bcm7038-pwm";
236 reg = <0x406580 0x28>;
243 compatible = "brcm,bcm7038-pwm";
244 reg = <0x406800 0x28>;
250 aon_pm_l2_intc: interrupt-controller@408440 {
251 compatible = "brcm,l2-intc";
252 reg = <0x408440 0x30>;
253 interrupt-controller;
254 #interrupt-cells = <1>;
255 interrupt-parent = <&periph_intc>;
260 upg_gio: gpio@406700 {
261 compatible = "brcm,brcmstb-gpio";
262 reg = <0x406700 0x80>;
264 #interrupt-cells = <2>;
266 interrupt-controller;
267 interrupt-parent = <&upg_irq0_intc>;
269 brcm,gpio-bank-widths = <32 32 32 21>;
272 upg_gio_aon: gpio@4094c0 {
273 compatible = "brcm,brcmstb-gpio";
274 reg = <0x4094c0 0x40>;
276 #interrupt-cells = <2>;
278 interrupt-controller;
279 interrupt-parent = <&upg_aon_irq0_intc>;
281 interrupts-extended = <&upg_aon_irq0_intc 6>,
284 brcm,gpio-bank-widths = <18 4>;
287 enet0: ethernet@b80000 {
288 phy-mode = "internal";
289 phy-handle = <&phy1>;
290 mac-address = [ 00 10 18 36 23 1a ];
291 compatible = "brcm,genet-v3";
292 #address-cells = <0x1>;
294 reg = <0xb80000 0x11c88>;
295 interrupts = <17>, <18>;
296 interrupt-parent = <&periph_intc>;
300 compatible = "brcm,genet-mdio-v3";
301 #address-cells = <0x1>;
305 phy1: ethernet-phy@1 {
308 compatible = "brcm,40nm-ephy",
309 "ethernet-phy-ieee802.3-c22";
315 compatible = "brcm,bcm7435-ehci", "generic-ehci";
316 reg = <0x480300 0x100>;
318 interrupt-parent = <&periph_intc>;
324 compatible = "brcm,bcm7435-ohci", "generic-ohci";
325 reg = <0x480400 0x100>;
328 interrupt-parent = <&periph_intc>;
334 compatible = "brcm,bcm7435-ehci", "generic-ehci";
335 reg = <0x480500 0x100>;
337 interrupt-parent = <&periph_intc>;
343 compatible = "brcm,bcm7435-ohci", "generic-ohci";
344 reg = <0x480600 0x100>;
347 interrupt-parent = <&periph_intc>;
353 compatible = "brcm,bcm7435-ehci", "generic-ehci";
354 reg = <0x490300 0x100>;
356 interrupt-parent = <&periph_intc>;
362 compatible = "brcm,bcm7435-ohci", "generic-ohci";
363 reg = <0x490400 0x100>;
366 interrupt-parent = <&periph_intc>;
372 compatible = "brcm,bcm7435-ehci", "generic-ehci";
373 reg = <0x490500 0x100>;
375 interrupt-parent = <&periph_intc>;
381 compatible = "brcm,bcm7435-ohci", "generic-ohci";
382 reg = <0x490600 0x100>;
385 interrupt-parent = <&periph_intc>;
390 hif_l2_intc: interrupt-controller@41b000 {
391 compatible = "brcm,l2-intc";
392 reg = <0x41b000 0x30>;
393 interrupt-controller;
394 #interrupt-cells = <1>;
395 interrupt-parent = <&periph_intc>;
400 compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand";
401 #address-cells = <1>;
403 reg-names = "nand", "flash-dma";
404 reg = <0x41c800 0x600>, <0x41d000 0x100>;
405 interrupt-parent = <&hif_l2_intc>;
406 interrupts = <24>, <4>;
411 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
412 reg-names = "ahci", "top-ctrl";
413 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
414 interrupt-parent = <&periph_intc>;
416 #address-cells = <1>;
431 sata_phy: sata-phy@180100 {
432 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
433 reg = <0x180100 0x0eff>;
435 #address-cells = <1>;
439 sata_phy0: sata-phy@0 {
444 sata_phy1: sata-phy@1 {
450 sdhci0: sdhci@41a000 {
451 compatible = "brcm,bcm7425-sdhci";
452 reg = <0x41a000 0x100>;
453 interrupt-parent = <&periph_intc>;
460 sdhci1: sdhci@41a200 {
461 compatible = "brcm,bcm7425-sdhci";
462 reg = <0x41a200 0x100>;
463 interrupt-parent = <&periph_intc>;
470 spi_l2_intc: interrupt-controller@41bd00 {
471 compatible = "brcm,l2-intc";
472 reg = <0x41bd00 0x30>;
473 interrupt-controller;
474 #interrupt-cells = <1>;
475 interrupt-parent = <&periph_intc>;
480 #address-cells = <0x1>;
482 compatible = "brcm,spi-bcm-qspi",
483 "brcm,spi-brcmstb-qspi";
485 reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
486 reg-names = "cs_reg", "hif_mspi", "bspi";
487 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
488 interrupt-parent = <&spi_l2_intc>;
489 interrupt-names = "spi_lr_fullness_reached",
490 "spi_lr_session_aborted",
492 "spi_lr_session_done",
500 #address-cells = <1>;
502 compatible = "brcm,spi-bcm-qspi",
503 "brcm,spi-brcmstb-mspi";
505 reg = <0x409200 0x180>;
508 interrupt-parent = <&upg_aon_irq0_intc>;
509 interrupt-names = "mspi_done";