1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "brcm,bcm7425";
11 mips-hpt-frequency = <163125000>;
14 compatible = "brcm,bmips5000";
20 compatible = "brcm,bmips5000";
30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
35 #interrupt-cells = <1>;
40 compatible = "fixed-clock";
42 clock-frequency = <81000000>;
46 compatible = "fixed-clock";
48 clock-frequency = <27000000>;
56 compatible = "simple-bus";
57 ranges = <0 0x10000000 0x01000000>;
59 periph_intc: interrupt-controller@41a400 {
60 compatible = "brcm,bcm7038-l1-intc";
61 reg = <0x41a400 0x30>, <0x41a600 0x30>;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
67 interrupts = <2>, <3>;
70 sun_l2_intc: interrupt-controller@403000 {
71 compatible = "brcm,l2-intc";
72 reg = <0x403000 0x30>;
74 #interrupt-cells = <1>;
75 interrupt-parent = <&periph_intc>;
80 compatible = "brcm,bcm7400-gisb-arb";
81 reg = <0x400000 0xdc>;
83 interrupt-parent = <&sun_l2_intc>;
84 interrupts = <0>, <2>;
85 brcm,gisb-arb-master-mask = <0x177b>;
86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
93 upg_irq0_intc: interrupt-controller@406780 {
94 compatible = "brcm,bcm7120-l2-intc";
97 brcm,int-map-mask = <0x44>, <0x7000000>;
98 brcm,int-fwd-mask = <0x70000>;
100 interrupt-controller;
101 #interrupt-cells = <1>;
103 interrupt-parent = <&periph_intc>;
104 interrupts = <55>, <53>;
105 interrupt-names = "upg_main", "upg_bsc";
108 upg_aon_irq0_intc: interrupt-controller@409480 {
109 compatible = "brcm,bcm7120-l2-intc";
110 reg = <0x409480 0x8>;
112 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
113 brcm,int-fwd-mask = <0>;
116 interrupt-controller;
117 #interrupt-cells = <1>;
119 interrupt-parent = <&periph_intc>;
120 interrupts = <56>, <54>, <59>;
121 interrupt-names = "upg_main_aon", "upg_bsc_aon",
125 sun_top_ctrl: syscon@404000 {
126 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
127 reg = <0x404000 0x51c>;
132 compatible = "brcm,brcmstb-reboot";
133 syscon = <&sun_top_ctrl 0x304 0x308>;
136 uart0: serial@406b00 {
137 compatible = "ns16550a";
138 reg = <0x406b00 0x20>;
139 reg-io-width = <0x4>;
141 interrupt-parent = <&periph_intc>;
143 clocks = <&uart_clk>;
147 uart1: serial@406b40 {
148 compatible = "ns16550a";
149 reg = <0x406b40 0x20>;
150 reg-io-width = <0x4>;
152 interrupt-parent = <&periph_intc>;
154 clocks = <&uart_clk>;
158 uart2: serial@406b80 {
159 compatible = "ns16550a";
160 reg = <0x406b80 0x20>;
161 reg-io-width = <0x4>;
163 interrupt-parent = <&periph_intc>;
165 clocks = <&uart_clk>;
170 clock-frequency = <390000>;
171 compatible = "brcm,brcmstb-i2c";
172 interrupt-parent = <&upg_aon_irq0_intc>;
173 reg = <0x409180 0x58>;
175 interrupt-names = "upg_bsca";
180 clock-frequency = <390000>;
181 compatible = "brcm,brcmstb-i2c";
182 interrupt-parent = <&upg_aon_irq0_intc>;
183 reg = <0x409400 0x58>;
185 interrupt-names = "upg_bscb";
190 clock-frequency = <390000>;
191 compatible = "brcm,brcmstb-i2c";
192 interrupt-parent = <&upg_irq0_intc>;
193 reg = <0x406200 0x58>;
195 interrupt-names = "upg_bscc";
200 clock-frequency = <390000>;
201 compatible = "brcm,brcmstb-i2c";
202 interrupt-parent = <&upg_irq0_intc>;
203 reg = <0x406280 0x58>;
205 interrupt-names = "upg_bscd";
210 clock-frequency = <390000>;
211 compatible = "brcm,brcmstb-i2c";
212 interrupt-parent = <&upg_irq0_intc>;
213 reg = <0x406300 0x58>;
215 interrupt-names = "upg_bsce";
220 compatible = "brcm,bcm7038-pwm";
221 reg = <0x406580 0x28>;
228 compatible = "brcm,bcm7038-pwm";
229 reg = <0x406800 0x28>;
235 aon_pm_l2_intc: interrupt-controller@408440 {
236 compatible = "brcm,l2-intc";
237 reg = <0x408440 0x30>;
238 interrupt-controller;
239 #interrupt-cells = <1>;
240 interrupt-parent = <&periph_intc>;
245 upg_gio: gpio@406700 {
246 compatible = "brcm,brcmstb-gpio";
247 reg = <0x406700 0x80>;
249 #interrupt-cells = <2>;
251 interrupt-controller;
252 interrupt-parent = <&upg_irq0_intc>;
254 brcm,gpio-bank-widths = <32 32 32 21>;
257 upg_gio_aon: gpio@4094c0 {
258 compatible = "brcm,brcmstb-gpio";
259 reg = <0x4094c0 0x40>;
261 #interrupt-cells = <2>;
263 interrupt-controller;
264 interrupt-parent = <&upg_aon_irq0_intc>;
266 interrupts-extended = <&upg_aon_irq0_intc 6>,
269 brcm,gpio-bank-widths = <18 4>;
272 enet0: ethernet@b80000 {
273 phy-mode = "internal";
274 phy-handle = <&phy1>;
275 mac-address = [ 00 10 18 36 23 1a ];
276 compatible = "brcm,genet-v3";
277 #address-cells = <0x1>;
279 reg = <0xb80000 0x11c88>;
280 interrupts = <17>, <18>;
281 interrupt-parent = <&periph_intc>;
285 compatible = "brcm,genet-mdio-v3";
286 #address-cells = <0x1>;
290 phy1: ethernet-phy@1 {
293 compatible = "brcm,40nm-ephy",
294 "ethernet-phy-ieee802.3-c22";
300 compatible = "brcm,bcm7425-ehci", "generic-ehci";
301 reg = <0x480300 0x100>;
303 interrupt-parent = <&periph_intc>;
309 compatible = "brcm,bcm7425-ohci", "generic-ohci";
310 reg = <0x480400 0x100>;
313 interrupt-parent = <&periph_intc>;
319 compatible = "brcm,bcm7425-ehci", "generic-ehci";
320 reg = <0x480500 0x100>;
322 interrupt-parent = <&periph_intc>;
328 compatible = "brcm,bcm7425-ohci", "generic-ohci";
329 reg = <0x480600 0x100>;
332 interrupt-parent = <&periph_intc>;
338 compatible = "brcm,bcm7425-ehci", "generic-ehci";
339 reg = <0x490300 0x100>;
341 interrupt-parent = <&periph_intc>;
347 compatible = "brcm,bcm7425-ohci", "generic-ohci";
348 reg = <0x490400 0x100>;
351 interrupt-parent = <&periph_intc>;
357 compatible = "brcm,bcm7425-ehci", "generic-ehci";
358 reg = <0x490500 0x100>;
360 interrupt-parent = <&periph_intc>;
366 compatible = "brcm,bcm7425-ohci", "generic-ohci";
367 reg = <0x490600 0x100>;
370 interrupt-parent = <&periph_intc>;
375 hif_l2_intc: interrupt-controller@41a000 {
376 compatible = "brcm,l2-intc";
377 reg = <0x41a000 0x30>;
378 interrupt-controller;
379 #interrupt-cells = <1>;
380 interrupt-parent = <&periph_intc>;
385 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
386 #address-cells = <1>;
389 reg = <0x41b800 0x400>;
390 interrupt-parent = <&hif_l2_intc>;
396 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
397 reg-names = "ahci", "top-ctrl";
398 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
399 interrupt-parent = <&periph_intc>;
401 #address-cells = <1>;
416 sata_phy: sata-phy@180100 {
417 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
418 reg = <0x180100 0x0eff>;
420 #address-cells = <1>;
424 sata_phy0: sata-phy@0 {
429 sata_phy1: sata-phy@1 {
435 sdhci0: sdhci@419000 {
436 compatible = "brcm,bcm7425-sdhci";
437 reg = <0x419000 0x100>;
438 interrupt-parent = <&periph_intc>;
445 sdhci1: sdhci@419200 {
446 compatible = "brcm,bcm7425-sdhci";
447 reg = <0x419200 0x100>;
448 interrupt-parent = <&periph_intc>;
455 spi_l2_intc: interrupt-controller@41ad00 {
456 compatible = "brcm,l2-intc";
457 reg = <0x41ad00 0x30>;
458 interrupt-controller;
459 #interrupt-cells = <1>;
460 interrupt-parent = <&periph_intc>;
465 #address-cells = <0x1>;
467 compatible = "brcm,spi-bcm-qspi",
468 "brcm,spi-brcmstb-qspi";
470 reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
471 reg-names = "cs_reg", "hif_mspi", "bspi";
472 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
473 interrupt-parent = <&spi_l2_intc>;
474 interrupt-names = "spi_lr_fullness_reached",
475 "spi_lr_session_aborted",
477 "spi_lr_session_done",
485 #address-cells = <1>;
487 compatible = "brcm,spi-bcm-qspi",
488 "brcm,spi-brcmstb-mspi";
490 reg = <0x409200 0x180>;
493 interrupt-parent = <&upg_aon_irq0_intc>;
494 interrupt-names = "mspi_done";