1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "brcm,bcm7420";
11 mips-hpt-frequency = <93750000>;
14 compatible = "brcm,bmips5000";
20 compatible = "brcm,bmips5000";
30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
35 #interrupt-cells = <1>;
40 compatible = "fixed-clock";
42 clock-frequency = <81000000>;
46 compatible = "fixed-clock";
48 clock-frequency = <27000000>;
56 compatible = "simple-bus";
57 ranges = <0 0x10000000 0x01000000>;
59 periph_intc: interrupt-controller@441400 {
60 compatible = "brcm,bcm7038-l1-intc";
61 reg = <0x441400 0x30>, <0x441600 0x30>;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
67 interrupts = <2>, <3>;
70 sun_l2_intc: interrupt-controller@401800 {
71 compatible = "brcm,l2-intc";
72 reg = <0x401800 0x30>;
74 #interrupt-cells = <1>;
75 interrupt-parent = <&periph_intc>;
80 compatible = "brcm,bcm7400-gisb-arb";
81 reg = <0x400000 0xdc>;
83 interrupt-parent = <&sun_l2_intc>;
84 interrupts = <0>, <2>;
85 brcm,gisb-arb-master-mask = <0x3ff>;
86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
87 "pcie_0", "bsp_0", "rdc_0",
88 "rptd_0", "avd_0", "avd_1",
92 upg_irq0_intc: interrupt-controller@406780 {
93 compatible = "brcm,bcm7120-l2-intc";
96 brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
97 brcm,int-fwd-mask = <0x70000>;
100 #interrupt-cells = <1>;
102 interrupt-parent = <&periph_intc>;
103 interrupts = <18>, <19>, <20>;
104 interrupt-names = "upg_main", "upg_bsc", "upg_spi";
107 sun_top_ctrl: syscon@404000 {
108 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
109 reg = <0x404000 0x60c>;
114 compatible = "brcm,bcm7038-reboot";
115 syscon = <&sun_top_ctrl 0x8 0x14>;
118 uart0: serial@406b00 {
119 compatible = "ns16550a";
120 reg = <0x406b00 0x20>;
121 reg-io-width = <0x4>;
123 interrupt-parent = <&periph_intc>;
125 clocks = <&uart_clk>;
129 uart1: serial@406b40 {
130 compatible = "ns16550a";
131 reg = <0x406b40 0x20>;
132 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart2: serial@406b80 {
141 compatible = "ns16550a";
142 reg = <0x406b80 0x20>;
143 reg-io-width = <0x4>;
145 interrupt-parent = <&periph_intc>;
147 clocks = <&uart_clk>;
152 clock-frequency = <390000>;
153 compatible = "brcm,brcmstb-i2c";
154 interrupt-parent = <&upg_irq0_intc>;
155 reg = <0x406200 0x58>;
157 interrupt-names = "upg_bsca";
162 clock-frequency = <390000>;
163 compatible = "brcm,brcmstb-i2c";
164 interrupt-parent = <&upg_irq0_intc>;
165 reg = <0x406280 0x58>;
167 interrupt-names = "upg_bscb";
172 clock-frequency = <390000>;
173 compatible = "brcm,brcmstb-i2c";
174 interrupt-parent = <&upg_irq0_intc>;
175 reg = <0x406300 0x58>;
177 interrupt-names = "upg_bscc";
182 clock-frequency = <390000>;
183 compatible = "brcm,brcmstb-i2c";
184 interrupt-parent = <&upg_irq0_intc>;
185 reg = <0x406380 0x58>;
187 interrupt-names = "upg_bscd";
192 clock-frequency = <390000>;
193 compatible = "brcm,brcmstb-i2c";
194 interrupt-parent = <&upg_irq0_intc>;
195 reg = <0x406800 0x58>;
197 interrupt-names = "upg_bsce";
202 compatible = "brcm,bcm7038-pwm";
203 reg = <0x406580 0x28>;
210 compatible = "brcm,bcm7038-pwm";
211 reg = <0x406880 0x28>;
217 upg_gio: gpio@406700 {
218 compatible = "brcm,brcmstb-gpio";
219 reg = <0x406700 0x80>;
221 #interrupt-cells = <2>;
223 interrupt-controller;
224 interrupt-parent = <&upg_irq0_intc>;
226 brcm,gpio-bank-widths = <32 32 32 27>;
229 enet0: ethernet@468000 {
230 phy-mode = "internal";
231 phy-handle = <&phy1>;
232 mac-address = [ 00 10 18 36 23 1a ];
233 compatible = "brcm,genet-v1";
234 #address-cells = <0x1>;
236 reg = <0x468000 0x3c8c>;
237 interrupts = <69>, <79>;
238 interrupt-parent = <&periph_intc>;
242 compatible = "brcm,genet-mdio-v1";
243 #address-cells = <0x1>;
247 phy1: ethernet-phy@1 {
250 compatible = "brcm,65nm-ephy",
251 "ethernet-phy-ieee802.3-c22";
257 compatible = "brcm,bcm7420-ehci", "generic-ehci";
258 reg = <0x488300 0x100>;
259 interrupt-parent = <&periph_intc>;
265 compatible = "brcm,bcm7420-ohci", "generic-ohci";
266 reg = <0x488400 0x100>;
269 interrupt-parent = <&periph_intc>;
275 compatible = "brcm,bcm7420-ehci", "generic-ehci";
276 reg = <0x488500 0x100>;
277 interrupt-parent = <&periph_intc>;
283 compatible = "brcm,bcm7420-ohci", "generic-ohci";
284 reg = <0x488600 0x100>;
287 interrupt-parent = <&periph_intc>;
292 spi_l2_intc: interrupt-controller@411d00 {
293 compatible = "brcm,l2-intc";
294 reg = <0x411d00 0x30>;
295 interrupt-controller;
296 #interrupt-cells = <1>;
297 interrupt-parent = <&periph_intc>;
302 #address-cells = <0x1>;
304 compatible = "brcm,spi-bcm-qspi",
305 "brcm,spi-brcmstb-qspi";
307 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
308 reg-names = "cs_reg", "hif_mspi", "bspi";
309 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
310 interrupt-parent = <&spi_l2_intc>;
311 interrupt-names = "spi_lr_fullness_reached",
312 "spi_lr_session_aborted",
314 "spi_lr_session_done",
322 #address-cells = <1>;
324 compatible = "brcm,spi-bcm-qspi",
325 "brcm,spi-brcmstb-mspi";
327 reg = <0x406400 0x180>;
330 interrupt-parent = <&upg_irq0_intc>;
331 interrupt-names = "mspi_done";