4 compatible = "brcm,bcm7358";
10 mips-hpt-frequency = <375000000>;
13 compatible = "brcm,bmips3300";
23 cpu_intc: interrupt-controller {
25 compatible = "mti,cpu-interrupt-controller";
28 #interrupt-cells = <1>;
33 compatible = "fixed-clock";
35 clock-frequency = <81000000>;
39 compatible = "fixed-clock";
41 clock-frequency = <27000000>;
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
52 periph_intc: interrupt-controller@411400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x411400 0x30>;
57 #interrupt-cells = <1>;
59 interrupt-parent = <&cpu_intc>;
63 sun_l2_intc: interrupt-controller@403000 {
64 compatible = "brcm,l2-intc";
65 reg = <0x403000 0x30>;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x2f3>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
84 upg_irq0_intc: interrupt-controller@406600 {
85 compatible = "brcm,bcm7120-l2-intc";
88 brcm,int-map-mask = <0x44>, <0x7000000>;
89 brcm,int-fwd-mask = <0x70000>;
92 #interrupt-cells = <1>;
94 interrupt-parent = <&periph_intc>;
95 interrupts = <56>, <54>;
96 interrupt-names = "upg_main", "upg_bsc";
99 upg_aon_irq0_intc: interrupt-controller@408b80 {
100 compatible = "brcm,bcm7120-l2-intc";
101 reg = <0x408b80 0x8>;
103 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
104 brcm,int-fwd-mask = <0>;
107 interrupt-controller;
108 #interrupt-cells = <1>;
110 interrupt-parent = <&periph_intc>;
111 interrupts = <57>, <55>, <59>;
112 interrupt-names = "upg_main_aon", "upg_bsc_aon",
116 sun_top_ctrl: syscon@404000 {
117 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
118 reg = <0x404000 0x51c>;
123 compatible = "brcm,brcmstb-reboot";
124 syscon = <&sun_top_ctrl 0x304 0x308>;
127 uart0: serial@406800 {
128 compatible = "ns16550a";
129 reg = <0x406800 0x20>;
130 reg-io-width = <0x4>;
133 interrupt-parent = <&periph_intc>;
135 clocks = <&uart_clk>;
139 uart1: serial@406840 {
140 compatible = "ns16550a";
141 reg = <0x406840 0x20>;
142 reg-io-width = <0x4>;
145 interrupt-parent = <&periph_intc>;
147 clocks = <&uart_clk>;
151 uart2: serial@406880 {
152 compatible = "ns16550a";
153 reg = <0x406880 0x20>;
154 reg-io-width = <0x4>;
157 interrupt-parent = <&periph_intc>;
159 clocks = <&uart_clk>;
164 clock-frequency = <390000>;
165 compatible = "brcm,brcmstb-i2c";
166 interrupt-parent = <&upg_irq0_intc>;
167 reg = <0x406200 0x58>;
169 interrupt-names = "upg_bsca";
174 clock-frequency = <390000>;
175 compatible = "brcm,brcmstb-i2c";
176 interrupt-parent = <&upg_irq0_intc>;
177 reg = <0x406280 0x58>;
179 interrupt-names = "upg_bscb";
184 clock-frequency = <390000>;
185 compatible = "brcm,brcmstb-i2c";
186 interrupt-parent = <&upg_irq0_intc>;
187 reg = <0x406300 0x58>;
189 interrupt-names = "upg_bscc";
194 clock-frequency = <390000>;
195 compatible = "brcm,brcmstb-i2c";
196 interrupt-parent = <&upg_aon_irq0_intc>;
197 reg = <0x408980 0x58>;
199 interrupt-names = "upg_bscd";
204 compatible = "brcm,bcm7038-pwm";
205 reg = <0x406400 0x28>;
212 compatible = "brcm,bcm7038-pwm";
213 reg = <0x406700 0x28>;
219 aon_pm_l2_intc: interrupt-controller@408240 {
220 compatible = "brcm,l2-intc";
221 reg = <0x408240 0x30>;
222 interrupt-controller;
223 #interrupt-cells = <1>;
224 interrupt-parent = <&periph_intc>;
229 upg_gio: gpio@406500 {
230 compatible = "brcm,brcmstb-gpio";
231 reg = <0x406500 0xa0>;
233 #interrupt-cells = <2>;
235 interrupt-controller;
236 interrupt-parent = <&upg_irq0_intc>;
238 brcm,gpio-bank-widths = <32 32 32 29 4>;
241 upg_gio_aon: gpio@408c00 {
242 compatible = "brcm,brcmstb-gpio";
243 reg = <0x408c00 0x60>;
245 #interrupt-cells = <2>;
247 interrupt-controller;
248 interrupt-parent = <&upg_aon_irq0_intc>;
250 interrupts-extended = <&upg_aon_irq0_intc 6>,
253 brcm,gpio-bank-widths = <21 32 2>;
256 enet0: ethernet@430000 {
257 phy-mode = "internal";
258 phy-handle = <&phy1>;
259 mac-address = [ 00 10 18 36 23 1a ];
260 compatible = "brcm,genet-v2";
261 #address-cells = <0x1>;
263 reg = <0x430000 0x4c8c>;
264 interrupts = <24>, <25>;
265 interrupt-parent = <&periph_intc>;
269 compatible = "brcm,genet-mdio-v2";
270 #address-cells = <0x1>;
274 phy1: ethernet-phy@1 {
277 compatible = "brcm,40nm-ephy",
278 "ethernet-phy-ieee802.3-c22";
284 compatible = "brcm,bcm7358-ehci", "generic-ehci";
285 reg = <0x480300 0x100>;
287 interrupt-parent = <&periph_intc>;
293 compatible = "brcm,bcm7358-ohci", "generic-ohci";
294 reg = <0x480400 0x100>;
297 interrupt-parent = <&periph_intc>;
302 hif_l2_intc: interrupt-controller@411000 {
303 compatible = "brcm,l2-intc";
304 reg = <0x411000 0x30>;
305 interrupt-controller;
306 #interrupt-cells = <1>;
307 interrupt-parent = <&periph_intc>;
312 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
313 #address-cells = <1>;
316 reg = <0x412800 0x400>;
317 interrupt-parent = <&hif_l2_intc>;