arch/mips/boot/dts/brcm/bcm6368.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include "dt-bindings/clock/bcm6368-clock.h"
   4 #include "dt-bindings/reset/bcm6368-reset.h"
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "brcm,bcm6368";
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 mips-hpt-frequency = <200000000>;
  16
  17                 cpu@0 {
  18                         compatible = "brcm,bmips4350";
  19                         device_type = "cpu";
  20                         reg = <0>;
  21                 };
  22
  23                 cpu@1 {
  24                         compatible = "brcm,bmips4350";
  25                         device_type = "cpu";
  26                         reg = <1>;
  27                 };
  28         };
  29
  30         clocks {
  31                 periph_osc: periph-osc {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <50000000>;
  35                         clock-output-names = "periph";
  36                 };
  37         };
  38
  39         aliases {
  40                 nflash = &nflash;
  41                 pflash = &pflash;
  42                 serial0 = &uart0;
  43                 serial1 = &uart1;
  44                 spi0 = &lsspi;
  45         };
  46
  47         cpu_intc: interrupt-controller {
  48                 #address-cells = <0>;
  49                 compatible = "mti,cpu-interrupt-controller";
  50
  51                 interrupt-controller;
  52                 #interrupt-cells = <1>;
  53         };
  54
  55         ubus {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58
  59                 compatible = "simple-bus";
  60                 ranges;
  61
  62                 periph_clk: clock-controller@10000004 {
  63                         compatible = "brcm,bcm6368-clocks";
  64                         reg = <0x10000004 0x4>;
  65                         #clock-cells = <1>;
  66                 };
  67
  68                 pll_cntl: syscon@100000008 {
  69                         compatible = "syscon";
  70                         reg = <0x10000008 0x4>;
  71                         native-endian;
  72
  73                         reboot {
  74                                 compatible = "syscon-reboot";
  75                                 offset = <0x0>;
  76                                 mask = <0x1>;
  77                         };
  78                 };
  79
  80                 periph_rst: reset-controller@10000010 {
  81                         compatible = "brcm,bcm6345-reset";
  82                         reg = <0x10000010 0x4>;
  83                         #reset-cells = <1>;
  84                 };
  85
  86                 periph_intc: interrupt-controller@10000020 {
  87                         compatible = "brcm,bcm6345-l1-intc";
  88                         reg = <0x10000020 0x10>,
  89                               <0x10000030 0x10>;
  90
  91                         interrupt-controller;
  92                         #interrupt-cells = <1>;
  93
  94                         interrupt-parent = <&cpu_intc>;
  95                         interrupts = <2>, <3>;
  96                 };
  97
  98                 wdt: watchdog@1000005c {
  99                         compatible = "brcm,bcm7038-wdt";
 100                         reg = <0x1000005c 0xc>;
 101
 102                         clocks = <&periph_osc>;
 103                         clock-names = "refclk";
 104
 105                         timeout-sec = <30>;
 106                 };
 107
 108                 leds0: led-controller@100000d0 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         compatible = "brcm,bcm6358-leds";
 112                         reg = <0x100000d0 0x8>;
 113
 114                         status = "disabled";
 115                 };
 116
 117                 uart0: serial@10000100 {
 118                         compatible = "brcm,bcm6345-uart";
 119                         reg = <0x10000100 0x18>;
 120
 121                         interrupt-parent = <&periph_intc>;
 122                         interrupts = <2>;
 123
 124                         clocks = <&periph_osc>;
 125                         clock-names = "refclk";
 126
 127                         status = "disabled";
 128                 };
 129
 130                 uart1: serial@10000120 {
 131                         compatible = "brcm,bcm6345-uart";
 132                         reg = <0x10000120 0x18>;
 133
 134                         interrupt-parent = <&periph_intc>;
 135                         interrupts = <3>;
 136
 137                         clocks = <&periph_osc>;
 138                         clock-names = "refclk";
 139
 140                         status = "disabled";
 141                 };
 142
 143                 nflash: nand@10000200 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         compatible = "brcm,nand-bcm6368",
 147                                      "brcm,brcmnand-v2.1",
 148                                      "brcm,brcmnand";
 149                         reg = <0x10000200 0x180>,
 150                               <0x10000600 0x200>,
 151                               <0x10000070 0x10>;
 152                         reg-names = "nand",
 153                                     "nand-cache",
 154                                     "nand-int-base";
 155
 156                         interrupt-parent = <&periph_intc>;
 157                         interrupts = <10>;
 158
 159                         clocks = <&periph_clk BCM6368_CLK_NAND>;
 160                         clock-names = "nand";
 161
 162                         status = "disabled";
 163                 };
 164
 165                 lsspi: spi@10000800 {
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         compatible = "brcm,bcm6358-spi";
 169                         reg = <0x10000800 0x70c>;
 170
 171                         interrupt-parent = <&periph_intc>;
 172                         interrupts = <1>;
 173
 174                         clocks = <&periph_clk BCM6368_CLK_SPI>;
 175                         clock-names = "spi";
 176
 177                         resets = <&periph_rst BCM6368_RST_SPI>;
 178                         reset-names = "spi";
 179
 180                         status = "disabled";
 181                 };
 182
 183                 ehci: usb@10001500 {
 184                         compatible = "brcm,bcm6368-ehci", "generic-ehci";
 185                         reg = <0x10001500 0x100>;
 186                         big-endian;
 187
 188                         interrupt-parent = <&periph_intc>;
 189                         interrupts = <7>;
 190
 191                         phys = <&usbh 0>;
 192                         phy-names = "usb";
 193
 194                         status = "disabled";
 195                 };
 196
 197                 ohci: usb@10001600 {
 198                         compatible = "brcm,bcm6368-ohci", "generic-ohci";
 199                         reg = <0x10001600 0x100>;
 200                         big-endian;
 201                         no-big-frame-no;
 202
 203                         interrupt-parent = <&periph_intc>;
 204                         interrupts = <5>;
 205
 206                         phys = <&usbh 0>;
 207                         phy-names = "usb";
 208
 209                         status = "disabled";
 210                 };
 211
 212                 usbh: usb-phy@10001700 {
 213                         compatible = "brcm,bcm6368-usbh-phy";
 214                         reg = <0x10001700 0x38>;
 215                         #phy-cells = <1>;
 216
 217                         clocks = <&periph_clk BCM6368_CLK_USBH>;
 218                         clock-names = "usbh";
 219
 220                         resets = <&periph_rst BCM6368_RST_USBH>;
 221                         reset-names = "usbh";
 222
 223                         status = "disabled";
 224                 };
 225
 226                 random: rng@10004180 {
 227                         compatible = "brcm,bcm6368-rng";
 228                         reg = <0x10004180 0x14>;
 229
 230                         clocks = <&periph_clk BCM6368_CLK_IPSEC>;
 231                         clock-names = "ipsec";
 232
 233                         resets = <&periph_rst BCM6368_RST_IPSEC>;
 234                         reset-names = "ipsec";
 235                 };
 236         };
 237
 238         pflash: nor@18000000 {
 239                 #address-cells = <1>;
 240                 #size-cells = <1>;
 241                 compatible = "cfi-flash";
 242                 reg = <0x18000000 0x2000000>;
 243                 bank-width = <2>;
 244
 245                 status = "disabled";
 246         };
 247 };