arch/mips/boot/dts/brcm/bcm63268.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include "dt-bindings/clock/bcm63268-clock.h"
   4 #include "dt-bindings/reset/bcm63268-reset.h"
   5 #include "dt-bindings/soc/bcm63268-pm.h"
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         compatible = "brcm,bcm63268";
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15
  16                 mips-hpt-frequency = <200000000>;
  17
  18                 cpu@0 {
  19                         compatible = "brcm,bmips4350";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu@1 {
  25                         compatible = "brcm,bmips4350";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         clocks {
  32                 periph_osc: periph-osc {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <50000000>;
  36                         clock-output-names = "periph";
  37                 };
  38
  39                 hsspi_osc: hsspi-osc {
  40                         compatible = "fixed-clock";
  41
  42                         #clock-cells = <0>;
  43
  44                         clock-frequency = <400000000>;
  45                         clock-output-names = "hsspi_osc";
  46                 };
  47         };
  48
  49         aliases {
  50                 nflash = &nflash;
  51                 serial0 = &uart0;
  52                 serial1 = &uart1;
  53                 spi0 = &lsspi;
  54                 spi1 = &hsspi;
  55         };
  56
  57         cpu_intc: interrupt-controller {
  58                 #address-cells = <0>;
  59                 compatible = "mti,cpu-interrupt-controller";
  60
  61                 interrupt-controller;
  62                 #interrupt-cells = <1>;
  63         };
  64
  65         ubus {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68
  69                 compatible = "simple-bus";
  70                 ranges;
  71
  72                 periph_clk: clock-controller@10000004 {
  73                         compatible = "brcm,bcm63268-clocks";
  74                         reg = <0x10000004 0x4>;
  75                         #clock-cells = <1>;
  76                 };
  77
  78                 pll_cntl: syscon@10000008 {
  79                         compatible = "syscon";
  80                         reg = <0x10000008 0x4>;
  81                         native-endian;
  82
  83                         reboot {
  84                                 compatible = "syscon-reboot";
  85                                 offset = <0x0>;
  86                                 mask = <0x1>;
  87                         };
  88                 };
  89
  90                 periph_rst: reset-controller@10000010 {
  91                         compatible = "brcm,bcm6345-reset";
  92                         reg = <0x10000010 0x4>;
  93                         #reset-cells = <1>;
  94                 };
  95
  96                 periph_intc: interrupt-controller@10000020 {
  97                         compatible = "brcm,bcm6345-l1-intc";
  98                         reg = <0x10000020 0x20>,
  99                               <0x10000040 0x20>;
 100
 101                         interrupt-controller;
 102                         #interrupt-cells = <1>;
 103
 104                         interrupt-parent = <&cpu_intc>;
 105                         interrupts = <2>, <3>;
 106                 };
 107
 108                 timer-mfd@10000080 {
 109                         compatible = "brcm,bcm7038-twd", "simple-mfd", "syscon";
 110                         reg = <0x10000080 0x30>;
 111                         ranges = <0x0 0x10000080 0x30>;
 112
 113                         wdt: watchdog@1c {
 114                                 compatible = "brcm,bcm7038-wdt";
 115                                 reg = <0x1c 0xc>;
 116
 117                                 clocks = <&periph_osc>;
 118                                 clock-names = "refclk";
 119
 120                                 timeout-sec = <30>;
 121                         };
 122                 };
 123
 124                 uart0: serial@10000180 {
 125                         compatible = "brcm,bcm6345-uart";
 126                         reg = <0x10000180 0x18>;
 127
 128                         interrupt-parent = <&periph_intc>;
 129                         interrupts = <5>;
 130
 131                         clocks = <&periph_osc>;
 132                         clock-names = "refclk";
 133
 134                         status = "disabled";
 135                 };
 136
 137                 nflash: nand@10000200 {
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         compatible = "brcm,nand-bcm6368",
 141                                      "brcm,brcmnand-v4.0",
 142                                      "brcm,brcmnand";
 143                         reg = <0x10000200 0x180>,
 144                               <0x10000600 0x200>,
 145                               <0x100000b0 0x10>;
 146                         reg-names = "nand",
 147                                     "nand-cache",
 148                                     "nand-int-base";
 149
 150                         interrupt-parent = <&periph_intc>;
 151                         interrupts = <50>;
 152
 153                         clocks = <&periph_clk BCM63268_CLK_NAND>;
 154                         clock-names = "nand";
 155
 156                         status = "disabled";
 157                 };
 158
 159                 uart1: serial@100001a0 {
 160                         compatible = "brcm,bcm6345-uart";
 161                         reg = <0x100001a0 0x18>;
 162
 163                         interrupt-parent = <&periph_intc>;
 164                         interrupts = <34>;
 165
 166                         clocks = <&periph_osc>;
 167                         clock-names = "refclk";
 168
 169                         status = "disabled";
 170                 };
 171
 172                 lsspi: spi@10000800 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         compatible = "brcm,bcm6358-spi";
 176                         reg = <0x10000800 0x70c>;
 177
 178                         interrupt-parent = <&periph_intc>;
 179                         interrupts = <80>;
 180
 181                         clocks = <&periph_clk BCM63268_CLK_SPI>;
 182                         clock-names = "spi";
 183
 184                         resets = <&periph_rst BCM63268_RST_SPI>;
 185
 186                         status = "disabled";
 187                 };
 188
 189                 hsspi: spi@10001000 {
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                         compatible = "brcm,bcm6328-hsspi";
 193                         reg = <0x10001000 0x600>;
 194
 195                         interrupt-parent = <&periph_intc>;
 196                         interrupts = <6>;
 197
 198                         clocks = <&periph_clk BCM63268_CLK_HSSPI>,
 199                                  <&hsspi_osc>;
 200                         clock-names = "hsspi",
 201                                       "pll";
 202
 203                         resets = <&periph_rst BCM63268_RST_SPI>;
 204
 205                         status = "disabled";
 206                 };
 207
 208                 periph_pwr: power-controller@1000184c {
 209                         compatible = "brcm,bcm6328-power-controller";
 210                         reg = <0x1000184c 0x4>;
 211                         #power-domain-cells = <1>;
 212                 };
 213
 214                 leds0: led-controller@10001900 {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         compatible = "brcm,bcm6328-leds";
 218                         reg = <0x10001900 0x24>;
 219
 220                         status = "disabled";
 221                 };
 222
 223                 ehci: usb@10002500 {
 224                         compatible = "brcm,bcm63268-ehci", "generic-ehci";
 225                         reg = <0x10002500 0x100>;
 226                         big-endian;
 227
 228                         interrupt-parent = <&periph_intc>;
 229                         interrupts = <10>;
 230
 231                         phys = <&usbh 0>;
 232                         phy-names = "usb";
 233
 234                         status = "disabled";
 235                 };
 236
 237                 ohci: usb@10002600 {
 238                         compatible = "brcm,bcm63268-ohci", "generic-ohci";
 239                         reg = <0x10002600 0x100>;
 240                         big-endian;
 241                         no-big-frame-no;
 242
 243                         interrupt-parent = <&periph_intc>;
 244                         interrupts = <9>;
 245
 246                         phys = <&usbh 0>;
 247                         phy-names = "usb";
 248
 249                         status = "disabled";
 250                 };
 251
 252                 usbh: usb-phy@10002700 {
 253                         compatible = "brcm,bcm63268-usbh-phy";
 254                         reg = <0x10002700 0x38>;
 255                         #phy-cells = <1>;
 256
 257                         clocks = <&periph_clk BCM63268_CLK_USBH>;
 258                         clock-names = "usbh";
 259
 260                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
 261
 262                         resets = <&periph_rst BCM63268_RST_USBH>;
 263                         reset-names = "usbh";
 264
 265                         status = "disabled";
 266                 };
 267         };
 268 };