2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
10 #include <linux/init.h>
11 #include <linux/bitops.h>
12 #include <linux/memblock.h>
13 #include <linux/ioport.h>
14 #include <linux/kernel.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_fdt.h>
19 #include <linux/of_platform.h>
20 #include <linux/libfdt.h>
21 #include <linux/smp.h>
22 #include <asm/addrspace.h>
23 #include <asm/bmips.h>
24 #include <asm/bootinfo.h>
25 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
28 #include <asm/smp-ops.h>
30 #include <asm/traps.h>
32 #define RELO_NORMAL_VEC BIT(18)
34 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
35 #define BCM6328_TP1_DISABLED BIT(9)
37 extern bool bmips_rac_flush_disable;
39 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
42 const char *compatible;
43 void (*quirk_fn)(void);
46 static void kbase_setup(void)
48 __raw_writel(kbase | RELO_NORMAL_VEC,
49 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
53 static void bcm3384_viper_quirks(void)
56 * Some experimental CM boxes are set up to let CM own the Viper TP0
57 * and let Linux own TP1. This requires moving the kernel
58 * load address to a non-conflicting region (e.g. via
59 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
60 * If we detect this condition, we need to move the MIPS exception
61 * vectors up to an area that we own.
63 * This is distinct from the OTHER special case mentioned in
64 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
65 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
67 * Also note that many BMIPS435x CPUs do not have a
68 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
69 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
71 board_ebase_setup = &kbase_setup;
72 bmips_smp_enabled = 0;
75 static void bcm63xx_fixup_cpu1(void)
78 * The bootloader has set up the CPU1 reset vector at
80 * This conflicts with the special interrupt vector (IV).
81 * The bootloader has also set up CPU1 to respond to the wrong
83 * Here we will start up CPU1 in the background and ask it to
84 * reconfigure itself then go back to sleep.
86 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
89 cpumask_set_cpu(1, &bmips_booted_mask);
92 static void bcm6328_quirks(void)
94 /* Check CPU1 status in OTP (it is usually disabled) */
95 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
96 bmips_smp_enabled = 0;
101 static void bcm6358_quirks(void)
104 * BCM3368/BCM6358 need special handling for their shared TLB, so
105 * disable SMP for now
107 bmips_smp_enabled = 0;
110 * RAC flush causes kernel panics on BCM6358 when booting from TP1
111 * because the bootloader is not initializing it properly.
113 bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
116 static void bcm6368_quirks(void)
118 bcm63xx_fixup_cpu1();
121 static const struct bmips_quirk bmips_quirk_list[] = {
122 { "brcm,bcm3368", &bcm6358_quirks },
123 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
124 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
125 { "brcm,bcm6328", &bcm6328_quirks },
126 { "brcm,bcm6358", &bcm6358_quirks },
127 { "brcm,bcm6362", &bcm6368_quirks },
128 { "brcm,bcm6368", &bcm6368_quirks },
129 { "brcm,bcm63168", &bcm6368_quirks },
130 { "brcm,bcm63268", &bcm6368_quirks },
134 void __init prom_init(void)
137 register_bmips_smp_ops();
140 void __init prom_free_prom_memory(void)
144 const char *get_system_type(void)
146 return "Generic BMIPS kernel";
149 void __init plat_time_init(void)
151 struct device_node *np;
154 np = of_find_node_by_name(NULL, "cpus");
156 panic("missing 'cpus' DT node");
157 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
158 panic("missing 'mips-hpt-frequency' property");
161 mips_hpt_frequency = freq;
164 void __init plat_mem_setup(void)
167 const struct bmips_quirk *q;
170 ioport_resource.start = 0;
171 ioport_resource.end = ~0;
173 /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */
174 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
175 dtb = phys_to_virt(fw_arg2);
176 else if (fw_passed_dtb) /* UHI interface or appended dtb */
177 dtb = (void *)fw_passed_dtb;
178 else if (&__dtb_start != &__dtb_end)
179 dtb = (void *)__dtb_start;
181 panic("no dtb found");
183 __dt_setup_arch(dtb);
185 for (q = bmips_quirk_list; q->quirk_fn; q++) {
186 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
193 void __init device_tree_init(void)
195 struct device_node *np;
197 unflatten_and_copy_device_tree();
199 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
200 np = of_find_node_by_name(NULL, "cpus");
201 if (np && of_get_available_child_count(np) <= 1)
202 bmips_smp_enabled = 0;
206 static int __init plat_dev_init(void)
212 device_initcall(plat_dev_init);