arch/mips/alchemy/devboards/db1200.c

   1 /*
   2  * DBAu1200/PBAu1200 board platform device registration
   3  *
   4  * Copyright (C) 2008-2011 Manuel Lauss
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/gpio.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/leds.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/rawnand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/serial_8250.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/flash.h>
  37 #include <linux/smc91x.h>
  38 #include <linux/ata_platform.h>
  39 #include <asm/mach-au1x00/au1000.h>
  40 #include <asm/mach-au1x00/au1100_mmc.h>
  41 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  42 #include <asm/mach-au1x00/au1xxx_psc.h>
  43 #include <asm/mach-au1x00/au1200fb.h>
  44 #include <asm/mach-au1x00/au1550_spi.h>
  45 #include <asm/mach-db1x00/bcsr.h>
  46
  47 #include "platform.h"
  48
  49 #define BCSR_INT_IDE            0x0001
  50 #define BCSR_INT_ETH            0x0002
  51 #define BCSR_INT_PC0            0x0004
  52 #define BCSR_INT_PC0STSCHG      0x0008
  53 #define BCSR_INT_PC1            0x0010
  54 #define BCSR_INT_PC1STSCHG      0x0020
  55 #define BCSR_INT_DC             0x0040
  56 #define BCSR_INT_FLASHBUSY      0x0080
  57 #define BCSR_INT_PC0INSERT      0x0100
  58 #define BCSR_INT_PC0EJECT       0x0200
  59 #define BCSR_INT_PC1INSERT      0x0400
  60 #define BCSR_INT_PC1EJECT       0x0800
  61 #define BCSR_INT_SD0INSERT      0x1000
  62 #define BCSR_INT_SD0EJECT       0x2000
  63 #define BCSR_INT_SD1INSERT      0x4000
  64 #define BCSR_INT_SD1EJECT       0x8000
  65
  66 #define DB1200_IDE_PHYS_ADDR    0x18800000
  67 #define DB1200_IDE_REG_SHIFT    5
  68 #define DB1200_IDE_PHYS_LEN     (16 << DB1200_IDE_REG_SHIFT)
  69 #define DB1200_ETH_PHYS_ADDR    0x19000300
  70 #define DB1200_NAND_PHYS_ADDR   0x20000000
  71
  72 #define PB1200_IDE_PHYS_ADDR    0x0C800000
  73 #define PB1200_ETH_PHYS_ADDR    0x0D000300
  74 #define PB1200_NAND_PHYS_ADDR   0x1C000000
  75
  76 #define DB1200_INT_BEGIN        (AU1000_MAX_INTR + 1)
  77 #define DB1200_IDE_INT          (DB1200_INT_BEGIN + 0)
  78 #define DB1200_ETH_INT          (DB1200_INT_BEGIN + 1)
  79 #define DB1200_PC0_INT          (DB1200_INT_BEGIN + 2)
  80 #define DB1200_PC0_STSCHG_INT   (DB1200_INT_BEGIN + 3)
  81 #define DB1200_PC1_INT          (DB1200_INT_BEGIN + 4)
  82 #define DB1200_PC1_STSCHG_INT   (DB1200_INT_BEGIN + 5)
  83 #define DB1200_DC_INT           (DB1200_INT_BEGIN + 6)
  84 #define DB1200_FLASHBUSY_INT    (DB1200_INT_BEGIN + 7)
  85 #define DB1200_PC0_INSERT_INT   (DB1200_INT_BEGIN + 8)
  86 #define DB1200_PC0_EJECT_INT    (DB1200_INT_BEGIN + 9)
  87 #define DB1200_PC1_INSERT_INT   (DB1200_INT_BEGIN + 10)
  88 #define DB1200_PC1_EJECT_INT    (DB1200_INT_BEGIN + 11)
  89 #define DB1200_SD0_INSERT_INT   (DB1200_INT_BEGIN + 12)
  90 #define DB1200_SD0_EJECT_INT    (DB1200_INT_BEGIN + 13)
  91 #define PB1200_SD1_INSERT_INT   (DB1200_INT_BEGIN + 14)
  92 #define PB1200_SD1_EJECT_INT    (DB1200_INT_BEGIN + 15)
  93 #define DB1200_INT_END          (DB1200_INT_BEGIN + 15)
  94
  95 const char *get_system_type(void);
  96
  97 static int __init db1200_detect_board(void)
  98 {
  99         int bid;
 100
 101         /* try the DB1200 first */
 102         bcsr_init(DB1200_BCSR_PHYS_ADDR,
 103                   DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
 104         if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
 105                 unsigned short t = bcsr_read(BCSR_HEXLEDS);
 106                 bcsr_write(BCSR_HEXLEDS, ~t);
 107                 if (bcsr_read(BCSR_HEXLEDS) != t) {
 108                         bcsr_write(BCSR_HEXLEDS, t);
 109                         return 0;
 110                 }
 111         }
 112
 113         /* okay, try the PB1200 then */
 114         bcsr_init(PB1200_BCSR_PHYS_ADDR,
 115                   PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
 116         bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 117         if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
 118             (bid == BCSR_WHOAMI_PB1200_DDR2)) {
 119                 unsigned short t = bcsr_read(BCSR_HEXLEDS);
 120                 bcsr_write(BCSR_HEXLEDS, ~t);
 121                 if (bcsr_read(BCSR_HEXLEDS) != t) {
 122                         bcsr_write(BCSR_HEXLEDS, t);
 123                         return 0;
 124                 }
 125         }
 126
 127         return 1;       /* it's neither */
 128 }
 129
 130 int __init db1200_board_setup(void)
 131 {
 132         unsigned short whoami;
 133
 134         if (db1200_detect_board())
 135                 return -ENODEV;
 136
 137         whoami = bcsr_read(BCSR_WHOAMI);
 138         switch (BCSR_WHOAMI_BOARD(whoami)) {
 139         case BCSR_WHOAMI_PB1200_DDR1:
 140         case BCSR_WHOAMI_PB1200_DDR2:
 141         case BCSR_WHOAMI_DB1200:
 142                 break;
 143         default:
 144                 return -ENODEV;
 145         }
 146
 147         printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
 148                 "  Board-ID %d  Daughtercard ID %d\n", get_system_type(),
 149                 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 150
 151         return 0;
 152 }
 153
 154 /******************************************************************************/
 155
 156 static struct mtd_partition db1200_spiflash_parts[] = {
 157         {
 158                 .name   = "spi_flash",
 159                 .offset = 0,
 160                 .size   = MTDPART_SIZ_FULL,
 161         },
 162 };
 163
 164 static struct flash_platform_data db1200_spiflash_data = {
 165         .name           = "s25fl001",
 166         .parts          = db1200_spiflash_parts,
 167         .nr_parts       = ARRAY_SIZE(db1200_spiflash_parts),
 168         .type           = "m25p10",
 169 };
 170
 171 static struct spi_board_info db1200_spi_devs[] __initdata = {
 172         {
 173                 /* TI TMP121AIDBVR temp sensor */
 174                 .modalias       = "tmp121",
 175                 .max_speed_hz   = 2000000,
 176                 .bus_num        = 0,
 177                 .chip_select    = 0,
 178                 .mode           = 0,
 179         },
 180         {
 181                 /* Spansion S25FL001D0FMA SPI flash */
 182                 .modalias       = "m25p80",
 183                 .max_speed_hz   = 50000000,
 184                 .bus_num        = 0,
 185                 .chip_select    = 1,
 186                 .mode           = 0,
 187                 .platform_data  = &db1200_spiflash_data,
 188         },
 189 };
 190
 191 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
 192         { I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */
 193         { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
 194         { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
 195 };
 196
 197 /**********************************************************************/
 198
 199 static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 200                                  unsigned int ctrl)
 201 {
 202         struct nand_chip *this = mtd_to_nand(mtd);
 203         unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
 204
 205         ioaddr &= 0xffffff00;
 206
 207         if (ctrl & NAND_CLE) {
 208                 ioaddr += MEM_STNAND_CMD;
 209         } else if (ctrl & NAND_ALE) {
 210                 ioaddr += MEM_STNAND_ADDR;
 211         } else {
 212                 /* assume we want to r/w real data  by default */
 213                 ioaddr += MEM_STNAND_DATA;
 214         }
 215         this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
 216         if (cmd != NAND_CMD_NONE) {
 217                 __raw_writeb(cmd, this->IO_ADDR_W);
 218                 wmb();
 219         }
 220 }
 221
 222 static int au1200_nand_device_ready(struct mtd_info *mtd)
 223 {
 224         return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
 225 }
 226
 227 static struct mtd_partition db1200_nand_parts[] = {
 228         {
 229                 .name   = "NAND FS 0",
 230                 .offset = 0,
 231                 .size   = 8 * 1024 * 1024,
 232         },
 233         {
 234                 .name   = "NAND FS 1",
 235                 .offset = MTDPART_OFS_APPEND,
 236                 .size   = MTDPART_SIZ_FULL
 237         },
 238 };
 239
 240 struct platform_nand_data db1200_nand_platdata = {
 241         .chip = {
 242                 .nr_chips       = 1,
 243                 .chip_offset    = 0,
 244                 .nr_partitions  = ARRAY_SIZE(db1200_nand_parts),
 245                 .partitions     = db1200_nand_parts,
 246                 .chip_delay     = 20,
 247         },
 248         .ctrl = {
 249                 .dev_ready      = au1200_nand_device_ready,
 250                 .cmd_ctrl       = au1200_nand_cmd_ctrl,
 251         },
 252 };
 253
 254 static struct resource db1200_nand_res[] = {
 255         [0] = {
 256                 .start  = DB1200_NAND_PHYS_ADDR,
 257                 .end    = DB1200_NAND_PHYS_ADDR + 0xff,
 258                 .flags  = IORESOURCE_MEM,
 259         },
 260 };
 261
 262 static struct platform_device db1200_nand_dev = {
 263         .name           = "gen_nand",
 264         .num_resources  = ARRAY_SIZE(db1200_nand_res),
 265         .resource       = db1200_nand_res,
 266         .id             = -1,
 267         .dev            = {
 268                 .platform_data = &db1200_nand_platdata,
 269         }
 270 };
 271
 272 /**********************************************************************/
 273
 274 static struct smc91x_platdata db1200_eth_data = {
 275         .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
 276         .leda   = RPC_LED_100_10,
 277         .ledb   = RPC_LED_TX_RX,
 278 };
 279
 280 static struct resource db1200_eth_res[] = {
 281         [0] = {
 282                 .start  = DB1200_ETH_PHYS_ADDR,
 283                 .end    = DB1200_ETH_PHYS_ADDR + 0xf,
 284                 .flags  = IORESOURCE_MEM,
 285         },
 286         [1] = {
 287                 .start  = DB1200_ETH_INT,
 288                 .end    = DB1200_ETH_INT,
 289                 .flags  = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 static struct platform_device db1200_eth_dev = {
 294         .dev    = {
 295                 .platform_data  = &db1200_eth_data,
 296         },
 297         .name           = "smc91x",
 298         .id             = -1,
 299         .num_resources  = ARRAY_SIZE(db1200_eth_res),
 300         .resource       = db1200_eth_res,
 301 };
 302
 303 /**********************************************************************/
 304
 305 static struct pata_platform_info db1200_ide_info = {
 306         .ioport_shift   = DB1200_IDE_REG_SHIFT,
 307 };
 308
 309 #define IDE_ALT_START   (14 << DB1200_IDE_REG_SHIFT)
 310 static struct resource db1200_ide_res[] = {
 311         [0] = {
 312                 .start  = DB1200_IDE_PHYS_ADDR,
 313                 .end    = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
 314                 .flags  = IORESOURCE_MEM,
 315         },
 316         [1] = {
 317                 .start  = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
 318                 .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [2] = {
 322                 .start  = DB1200_IDE_INT,
 323                 .end    = DB1200_IDE_INT,
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
 329
 330 static struct platform_device db1200_ide_dev = {
 331         .name           = "pata_platform",
 332         .id             = 0,
 333         .dev = {
 334                 .dma_mask               = &au1200_ide_dmamask,
 335                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 336                 .platform_data          = &db1200_ide_info,
 337         },
 338         .num_resources  = ARRAY_SIZE(db1200_ide_res),
 339         .resource       = db1200_ide_res,
 340 };
 341
 342 /**********************************************************************/
 343
 344 /* SD carddetects:  they're supposed to be edge-triggered, but ack
 345  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
 346  * is disabled and its counterpart enabled.  The 200ms timeout is
 347  * because the carddetect usually triggers twice, after debounce.
 348  */
 349 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
 350 {
 351         disable_irq_nosync(irq);
 352         return IRQ_WAKE_THREAD;
 353 }
 354
 355 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
 356 {
 357         mmc_detect_change(ptr, msecs_to_jiffies(200));
 358
 359         msleep(100);    /* debounce */
 360         if (irq == DB1200_SD0_INSERT_INT)
 361                 enable_irq(DB1200_SD0_EJECT_INT);
 362         else
 363                 enable_irq(DB1200_SD0_INSERT_INT);
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 static int db1200_mmc_cd_setup(void *mmc_host, int en)
 369 {
 370         int ret;
 371
 372         if (en) {
 373                 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
 374                                 db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
 375                 if (ret)
 376                         goto out;
 377
 378                 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
 379                                 db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
 380                 if (ret) {
 381                         free_irq(DB1200_SD0_INSERT_INT, mmc_host);
 382                         goto out;
 383                 }
 384
 385                 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
 386                         enable_irq(DB1200_SD0_EJECT_INT);
 387                 else
 388                         enable_irq(DB1200_SD0_INSERT_INT);
 389
 390         } else {
 391                 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
 392                 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
 393         }
 394         ret = 0;
 395 out:
 396         return ret;
 397 }
 398
 399 static void db1200_mmc_set_power(void *mmc_host, int state)
 400 {
 401         if (state) {
 402                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
 403                 msleep(400);    /* stabilization time */
 404         } else
 405                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
 406 }
 407
 408 static int db1200_mmc_card_readonly(void *mmc_host)
 409 {
 410         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
 411 }
 412
 413 static int db1200_mmc_card_inserted(void *mmc_host)
 414 {
 415         return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
 416 }
 417
 418 static void db1200_mmcled_set(struct led_classdev *led,
 419                               enum led_brightness brightness)
 420 {
 421         if (brightness != LED_OFF)
 422                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
 423         else
 424                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
 425 }
 426
 427 static struct led_classdev db1200_mmc_led = {
 428         .brightness_set = db1200_mmcled_set,
 429 };
 430
 431 /* -- */
 432
 433 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
 434 {
 435         disable_irq_nosync(irq);
 436         return IRQ_WAKE_THREAD;
 437 }
 438
 439 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
 440 {
 441         mmc_detect_change(ptr, msecs_to_jiffies(200));
 442
 443         msleep(100);    /* debounce */
 444         if (irq == PB1200_SD1_INSERT_INT)
 445                 enable_irq(PB1200_SD1_EJECT_INT);
 446         else
 447                 enable_irq(PB1200_SD1_INSERT_INT);
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
 453 {
 454         int ret;
 455
 456         if (en) {
 457                 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
 458                                 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
 459                 if (ret)
 460                         goto out;
 461
 462                 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
 463                                 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
 464                 if (ret) {
 465                         free_irq(PB1200_SD1_INSERT_INT, mmc_host);
 466                         goto out;
 467                 }
 468
 469                 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
 470                         enable_irq(PB1200_SD1_EJECT_INT);
 471                 else
 472                         enable_irq(PB1200_SD1_INSERT_INT);
 473
 474         } else {
 475                 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
 476                 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
 477         }
 478         ret = 0;
 479 out:
 480         return ret;
 481 }
 482
 483 static void pb1200_mmc1led_set(struct led_classdev *led,
 484                         enum led_brightness brightness)
 485 {
 486         if (brightness != LED_OFF)
 487                         bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
 488         else
 489                         bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
 490 }
 491
 492 static struct led_classdev pb1200_mmc1_led = {
 493         .brightness_set = pb1200_mmc1led_set,
 494 };
 495
 496 static void pb1200_mmc1_set_power(void *mmc_host, int state)
 497 {
 498         if (state) {
 499                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
 500                 msleep(400);    /* stabilization time */
 501         } else
 502                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
 503 }
 504
 505 static int pb1200_mmc1_card_readonly(void *mmc_host)
 506 {
 507         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
 508 }
 509
 510 static int pb1200_mmc1_card_inserted(void *mmc_host)
 511 {
 512         return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
 513 }
 514
 515
 516 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
 517         [0] = {
 518                 .cd_setup       = db1200_mmc_cd_setup,
 519                 .set_power      = db1200_mmc_set_power,
 520                 .card_inserted  = db1200_mmc_card_inserted,
 521                 .card_readonly  = db1200_mmc_card_readonly,
 522                 .led            = &db1200_mmc_led,
 523         },
 524         [1] = {
 525                 .cd_setup       = pb1200_mmc1_cd_setup,
 526                 .set_power      = pb1200_mmc1_set_power,
 527                 .card_inserted  = pb1200_mmc1_card_inserted,
 528                 .card_readonly  = pb1200_mmc1_card_readonly,
 529                 .led            = &pb1200_mmc1_led,
 530         },
 531 };
 532
 533 static struct resource au1200_mmc0_resources[] = {
 534         [0] = {
 535                 .start  = AU1100_SD0_PHYS_ADDR,
 536                 .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
 537                 .flags  = IORESOURCE_MEM,
 538         },
 539         [1] = {
 540                 .start  = AU1200_SD_INT,
 541                 .end    = AU1200_SD_INT,
 542                 .flags  = IORESOURCE_IRQ,
 543         },
 544         [2] = {
 545                 .start  = AU1200_DSCR_CMD0_SDMS_TX0,
 546                 .end    = AU1200_DSCR_CMD0_SDMS_TX0,
 547                 .flags  = IORESOURCE_DMA,
 548         },
 549         [3] = {
 550                 .start  = AU1200_DSCR_CMD0_SDMS_RX0,
 551                 .end    = AU1200_DSCR_CMD0_SDMS_RX0,
 552                 .flags  = IORESOURCE_DMA,
 553         }
 554 };
 555
 556 static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
 557
 558 static struct platform_device db1200_mmc0_dev = {
 559         .name           = "au1xxx-mmc",
 560         .id             = 0,
 561         .dev = {
 562                 .dma_mask               = &au1xxx_mmc_dmamask,
 563                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 564                 .platform_data          = &db1200_mmc_platdata[0],
 565         },
 566         .num_resources  = ARRAY_SIZE(au1200_mmc0_resources),
 567         .resource       = au1200_mmc0_resources,
 568 };
 569
 570 static struct resource au1200_mmc1_res[] = {
 571         [0] = {
 572                 .start  = AU1100_SD1_PHYS_ADDR,
 573                 .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
 574                 .flags  = IORESOURCE_MEM,
 575         },
 576         [1] = {
 577                 .start  = AU1200_SD_INT,
 578                 .end    = AU1200_SD_INT,
 579                 .flags  = IORESOURCE_IRQ,
 580         },
 581         [2] = {
 582                 .start  = AU1200_DSCR_CMD0_SDMS_TX1,
 583                 .end    = AU1200_DSCR_CMD0_SDMS_TX1,
 584                 .flags  = IORESOURCE_DMA,
 585         },
 586         [3] = {
 587                 .start  = AU1200_DSCR_CMD0_SDMS_RX1,
 588                 .end    = AU1200_DSCR_CMD0_SDMS_RX1,
 589                 .flags  = IORESOURCE_DMA,
 590         }
 591 };
 592
 593 static struct platform_device pb1200_mmc1_dev = {
 594         .name           = "au1xxx-mmc",
 595         .id             = 1,
 596         .dev = {
 597                 .dma_mask               = &au1xxx_mmc_dmamask,
 598                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 599                 .platform_data          = &db1200_mmc_platdata[1],
 600         },
 601         .num_resources  = ARRAY_SIZE(au1200_mmc1_res),
 602         .resource       = au1200_mmc1_res,
 603 };
 604
 605 /**********************************************************************/
 606
 607 static int db1200fb_panel_index(void)
 608 {
 609         return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
 610 }
 611
 612 static int db1200fb_panel_init(void)
 613 {
 614         /* Apply power */
 615         bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
 616                                 BCSR_BOARD_LCDBL);
 617         return 0;
 618 }
 619
 620 static int db1200fb_panel_shutdown(void)
 621 {
 622         /* Remove power */
 623         bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
 624                              BCSR_BOARD_LCDBL, 0);
 625         return 0;
 626 }
 627
 628 static struct au1200fb_platdata db1200fb_pd = {
 629         .panel_index    = db1200fb_panel_index,
 630         .panel_init     = db1200fb_panel_init,
 631         .panel_shutdown = db1200fb_panel_shutdown,
 632 };
 633
 634 static struct resource au1200_lcd_res[] = {
 635         [0] = {
 636                 .start  = AU1200_LCD_PHYS_ADDR,
 637                 .end    = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
 638                 .flags  = IORESOURCE_MEM,
 639         },
 640         [1] = {
 641                 .start  = AU1200_LCD_INT,
 642                 .end    = AU1200_LCD_INT,
 643                 .flags  = IORESOURCE_IRQ,
 644         }
 645 };
 646
 647 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
 648
 649 static struct platform_device au1200_lcd_dev = {
 650         .name           = "au1200-lcd",
 651         .id             = 0,
 652         .dev = {
 653                 .dma_mask               = &au1200_lcd_dmamask,
 654                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 655                 .platform_data          = &db1200fb_pd,
 656         },
 657         .num_resources  = ARRAY_SIZE(au1200_lcd_res),
 658         .resource       = au1200_lcd_res,
 659 };
 660
 661 /**********************************************************************/
 662
 663 static struct resource au1200_psc0_res[] = {
 664         [0] = {
 665                 .start  = AU1550_PSC0_PHYS_ADDR,
 666                 .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
 667                 .flags  = IORESOURCE_MEM,
 668         },
 669         [1] = {
 670                 .start  = AU1200_PSC0_INT,
 671                 .end    = AU1200_PSC0_INT,
 672                 .flags  = IORESOURCE_IRQ,
 673         },
 674         [2] = {
 675                 .start  = AU1200_DSCR_CMD0_PSC0_TX,
 676                 .end    = AU1200_DSCR_CMD0_PSC0_TX,
 677                 .flags  = IORESOURCE_DMA,
 678         },
 679         [3] = {
 680                 .start  = AU1200_DSCR_CMD0_PSC0_RX,
 681                 .end    = AU1200_DSCR_CMD0_PSC0_RX,
 682                 .flags  = IORESOURCE_DMA,
 683         },
 684 };
 685
 686 static struct platform_device db1200_i2c_dev = {
 687         .name           = "au1xpsc_smbus",
 688         .id             = 0,    /* bus number */
 689         .num_resources  = ARRAY_SIZE(au1200_psc0_res),
 690         .resource       = au1200_psc0_res,
 691 };
 692
 693 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
 694 {
 695         if (cs)
 696                 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
 697         else
 698                 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
 699 }
 700
 701 static struct au1550_spi_info db1200_spi_platdata = {
 702         .mainclk_hz     = 50000000,     /* PSC0 clock */
 703         .num_chipselect = 2,
 704         .activate_cs    = db1200_spi_cs_en,
 705 };
 706
 707 static u64 spi_dmamask = DMA_BIT_MASK(32);
 708
 709 static struct platform_device db1200_spi_dev = {
 710         .dev    = {
 711                 .dma_mask               = &spi_dmamask,
 712                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 713                 .platform_data          = &db1200_spi_platdata,
 714         },
 715         .name           = "au1550-spi",
 716         .id             = 0,    /* bus number */
 717         .num_resources  = ARRAY_SIZE(au1200_psc0_res),
 718         .resource       = au1200_psc0_res,
 719 };
 720
 721 static struct resource au1200_psc1_res[] = {
 722         [0] = {
 723                 .start  = AU1550_PSC1_PHYS_ADDR,
 724                 .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
 725                 .flags  = IORESOURCE_MEM,
 726         },
 727         [1] = {
 728                 .start  = AU1200_PSC1_INT,
 729                 .end    = AU1200_PSC1_INT,
 730                 .flags  = IORESOURCE_IRQ,
 731         },
 732         [2] = {
 733                 .start  = AU1200_DSCR_CMD0_PSC1_TX,
 734                 .end    = AU1200_DSCR_CMD0_PSC1_TX,
 735                 .flags  = IORESOURCE_DMA,
 736         },
 737         [3] = {
 738                 .start  = AU1200_DSCR_CMD0_PSC1_RX,
 739                 .end    = AU1200_DSCR_CMD0_PSC1_RX,
 740                 .flags  = IORESOURCE_DMA,
 741         },
 742 };
 743
 744 /* AC97 or I2S device */
 745 static struct platform_device db1200_audio_dev = {
 746         /* name assigned later based on switch setting */
 747         .id             = 1,    /* PSC ID */
 748         .num_resources  = ARRAY_SIZE(au1200_psc1_res),
 749         .resource       = au1200_psc1_res,
 750 };
 751
 752 /* DB1200 ASoC card device */
 753 static struct platform_device db1200_sound_dev = {
 754         /* name assigned later based on switch setting */
 755         .id             = 1,    /* PSC ID */
 756 };
 757
 758 static struct platform_device db1200_stac_dev = {
 759         .name           = "ac97-codec",
 760         .id             = 1,    /* on PSC1 */
 761 };
 762
 763 static struct platform_device db1200_audiodma_dev = {
 764         .name           = "au1xpsc-pcm",
 765         .id             = 1,    /* PSC ID */
 766 };
 767
 768 static struct platform_device *db1200_devs[] __initdata = {
 769         NULL,           /* PSC0, selected by S6.8 */
 770         &db1200_ide_dev,
 771         &db1200_mmc0_dev,
 772         &au1200_lcd_dev,
 773         &db1200_eth_dev,
 774         &db1200_nand_dev,
 775         &db1200_audiodma_dev,
 776         &db1200_audio_dev,
 777         &db1200_stac_dev,
 778         &db1200_sound_dev,
 779 };
 780
 781 static struct platform_device *pb1200_devs[] __initdata = {
 782         &pb1200_mmc1_dev,
 783 };
 784
 785 /* Some peripheral base addresses differ on the PB1200 */
 786 static int __init pb1200_res_fixup(void)
 787 {
 788         /* CPLD Revs earlier than 4 cause problems */
 789         if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
 790                 printk(KERN_ERR "WARNING!!!\n");
 791                 printk(KERN_ERR "WARNING!!!\n");
 792                 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
 793                 printk(KERN_ERR "the board updated to latest revisions.\n");
 794                 printk(KERN_ERR "This software will not work reliably\n");
 795                 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
 796                 printk(KERN_ERR "WARNING!!!\n");
 797                 printk(KERN_ERR "WARNING!!!\n");
 798                 return 1;
 799         }
 800
 801         db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
 802         db1200_nand_res[0].end   = PB1200_NAND_PHYS_ADDR + 0xff;
 803         db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
 804         db1200_ide_res[0].end   = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
 805         db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
 806         db1200_eth_res[0].end   = PB1200_ETH_PHYS_ADDR + 0xff;
 807         return 0;
 808 }
 809
 810 int __init db1200_dev_setup(void)
 811 {
 812         unsigned long pfc;
 813         unsigned short sw;
 814         int swapped, bid;
 815         struct clk *c;
 816
 817         bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 818         if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
 819             (bid == BCSR_WHOAMI_PB1200_DDR2)) {
 820                 if (pb1200_res_fixup())
 821                         return -ENODEV;
 822         }
 823
 824         /* GPIO7 is low-level triggered CPLD cascade */
 825         irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
 826         bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
 827
 828         /* SMBus/SPI on PSC0, Audio on PSC1 */
 829         pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
 830         pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
 831         pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
 832         pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
 833         alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
 834
 835         /* get 50MHz for I2C driver on PSC0 */
 836         c = clk_get(NULL, "psc0_intclk");
 837         if (!IS_ERR(c)) {
 838                 pfc = clk_round_rate(c, 50000000);
 839                 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
 840                         pr_warn("DB1200: cant get I2C close to 50MHz\n");
 841                 else
 842                         clk_set_rate(c, pfc);
 843                 clk_prepare_enable(c);
 844                 clk_put(c);
 845         }
 846
 847         /* insert/eject pairs: one of both is always screaming.  To avoid
 848          * issues they must not be automatically enabled when initially
 849          * requested.
 850          */
 851         irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
 852         irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
 853         irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
 854         irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
 855         irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
 856         irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
 857
 858         i2c_register_board_info(0, db1200_i2c_devs,
 859                                 ARRAY_SIZE(db1200_i2c_devs));
 860         spi_register_board_info(db1200_spi_devs,
 861                                 ARRAY_SIZE(db1200_i2c_devs));
 862
 863         /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
 864          *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
 865          *              or S12 on the PB1200.
 866          */
 867
 868         /* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
 869          * this pin is claimed by PSC0 (unused though, but pinmux doesn't
 870          * allow to free it without crippling the SPI interface).
 871          * As a result, in SPI mode, OTG simply won't work (PSC0 uses
 872          * it as an input pin which is pulled high on the boards).
 873          */
 874         pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
 875
 876         /* switch off OTG VBUS supply */
 877         gpio_request(215, "otg-vbus");
 878         gpio_direction_output(215, 1);
 879
 880         printk(KERN_INFO "%s device configuration:\n", get_system_type());
 881
 882         sw = bcsr_read(BCSR_SWITCHES);
 883         if (sw & BCSR_SWITCHES_DIP_8) {
 884                 db1200_devs[0] = &db1200_i2c_dev;
 885                 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
 886
 887                 pfc |= (2 << 17);       /* GPIO2 block owns GPIO215 */
 888
 889                 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
 890                 printk(KERN_INFO "   OTG port VBUS supply available!\n");
 891         } else {
 892                 db1200_devs[0] = &db1200_spi_dev;
 893                 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
 894
 895                 pfc |= (1 << 17);       /* PSC0 owns GPIO215 */
 896
 897                 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
 898                 printk(KERN_INFO "   OTG port VBUS supply disabled\n");
 899         }
 900         alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
 901
 902         /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
 903          * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
 904          */
 905         sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
 906         if (sw == BCSR_SWITCHES_DIP_8) {
 907                 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
 908                 db1200_audio_dev.name = "au1xpsc_i2s";
 909                 db1200_sound_dev.name = "db1200-i2s";
 910                 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
 911         } else {
 912                 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
 913                 db1200_audio_dev.name = "au1xpsc_ac97";
 914                 db1200_sound_dev.name = "db1200-ac97";
 915                 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
 916         }
 917
 918         /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
 919         __raw_writel(PSC_SEL_CLK_SERCLK,
 920             (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
 921         wmb();
 922
 923         db1x_register_pcmcia_socket(
 924                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 925                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 926                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 927                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 928                 AU1000_PCMCIA_IO_PHYS_ADDR,
 929                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 930                 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
 931                 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
 932
 933         db1x_register_pcmcia_socket(
 934                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 935                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 936                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 937                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 938                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 939                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 940                 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
 941                 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
 942
 943         swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
 944         db1x_register_norflash(64 << 20, 2, swapped);
 945
 946         platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
 947
 948         /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
 949         if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
 950             (bid == BCSR_WHOAMI_PB1200_DDR2))
 951                 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
 952
 953         return 0;
 954 }