arch/mips/alchemy/devboards/db1000.c

   1 /*
   2  * DBAu1000/1500/1100 PBAu1100/1500 board support
   3  *
   4  * Copyright 2000, 2008 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gpio.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/leds.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm.h>
  31 #include <linux/spi/spi.h>
  32 #include <linux/spi/spi_gpio.h>
  33 #include <linux/spi/ads7846.h>
  34 #include <asm/mach-au1x00/au1000.h>
  35 #include <asm/mach-au1x00/gpio-au1000.h>
  36 #include <asm/mach-au1x00/au1000_dma.h>
  37 #include <asm/mach-au1x00/au1100_mmc.h>
  38 #include <asm/mach-db1x00/bcsr.h>
  39 #include <asm/reboot.h>
  40 #include <prom.h>
  41 #include "platform.h"
  42
  43 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
  44
  45 const char *get_system_type(void);
  46
  47 int __init db1000_board_setup(void)
  48 {
  49         /* initialize board register space */
  50         bcsr_init(DB1000_BCSR_PHYS_ADDR,
  51                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
  52
  53         switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
  54         case BCSR_WHOAMI_DB1000:
  55         case BCSR_WHOAMI_DB1500:
  56         case BCSR_WHOAMI_DB1100:
  57         case BCSR_WHOAMI_PB1500:
  58         case BCSR_WHOAMI_PB1500R2:
  59         case BCSR_WHOAMI_PB1100:
  60                 pr_info("AMD Alchemy %s Board\n", get_system_type());
  61                 return 0;
  62         }
  63         return -ENODEV;
  64 }
  65
  66 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  67 {
  68         if ((slot < 12) || (slot > 13) || pin == 0)
  69                 return -1;
  70         if (slot == 12)
  71                 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
  72         if (slot == 13) {
  73                 switch (pin) {
  74                 case 1: return AU1500_PCI_INTA;
  75                 case 2: return AU1500_PCI_INTB;
  76                 case 3: return AU1500_PCI_INTC;
  77                 case 4: return AU1500_PCI_INTD;
  78                 }
  79         }
  80         return -1;
  81 }
  82
  83 static struct resource alchemy_pci_host_res[] = {
  84         [0] = {
  85                 .start  = AU1500_PCI_PHYS_ADDR,
  86                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
  87                 .flags  = IORESOURCE_MEM,
  88         },
  89 };
  90
  91 static struct alchemy_pci_platdata db1500_pci_pd = {
  92         .board_map_irq  = db1500_map_pci_irq,
  93 };
  94
  95 static struct platform_device db1500_pci_host_dev = {
  96         .dev.platform_data = &db1500_pci_pd,
  97         .name           = "alchemy-pci",
  98         .id             = 0,
  99         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 100         .resource       = alchemy_pci_host_res,
 101 };
 102
 103 int __init db1500_pci_setup(void)
 104 {
 105         return platform_device_register(&db1500_pci_host_dev);
 106 }
 107
 108 static struct resource au1100_lcd_resources[] = {
 109         [0] = {
 110                 .start  = AU1100_LCD_PHYS_ADDR,
 111                 .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
 112                 .flags  = IORESOURCE_MEM,
 113         },
 114         [1] = {
 115                 .start  = AU1100_LCD_INT,
 116                 .end    = AU1100_LCD_INT,
 117                 .flags  = IORESOURCE_IRQ,
 118         }
 119 };
 120
 121 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
 122
 123 static struct platform_device au1100_lcd_device = {
 124         .name           = "au1100-lcd",
 125         .id             = 0,
 126         .dev = {
 127                 .dma_mask               = &au1100_lcd_dmamask,
 128                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 129         },
 130         .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
 131         .resource       = au1100_lcd_resources,
 132 };
 133
 134 static struct resource alchemy_ac97c_res[] = {
 135         [0] = {
 136                 .start  = AU1000_AC97_PHYS_ADDR,
 137                 .end    = AU1000_AC97_PHYS_ADDR + 0xfff,
 138                 .flags  = IORESOURCE_MEM,
 139         },
 140         [1] = {
 141                 .start  = DMA_ID_AC97C_TX,
 142                 .end    = DMA_ID_AC97C_TX,
 143                 .flags  = IORESOURCE_DMA,
 144         },
 145         [2] = {
 146                 .start  = DMA_ID_AC97C_RX,
 147                 .end    = DMA_ID_AC97C_RX,
 148                 .flags  = IORESOURCE_DMA,
 149         },
 150 };
 151
 152 static struct platform_device alchemy_ac97c_dev = {
 153         .name           = "alchemy-ac97c",
 154         .id             = -1,
 155         .resource       = alchemy_ac97c_res,
 156         .num_resources  = ARRAY_SIZE(alchemy_ac97c_res),
 157 };
 158
 159 static struct platform_device alchemy_ac97c_dma_dev = {
 160         .name           = "alchemy-pcm-dma",
 161         .id             = 0,
 162 };
 163
 164 static struct platform_device db1x00_codec_dev = {
 165         .name           = "ac97-codec",
 166         .id             = -1,
 167 };
 168
 169 static struct platform_device db1x00_audio_dev = {
 170         .name           = "db1000-audio",
 171 };
 172
 173 /******************************************************************************/
 174
 175 static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
 176 {
 177         mmc_detect_change(ptr, msecs_to_jiffies(500));
 178         return IRQ_HANDLED;
 179 }
 180
 181 static int db1100_mmc_cd_setup(void *mmc_host, int en)
 182 {
 183         int ret = 0, irq;
 184
 185         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 186                 irq = AU1100_GPIO19_INT;
 187         else
 188                 irq = AU1100_GPIO14_INT;        /* PB1100 SD0 CD# */
 189
 190         if (en) {
 191                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
 192                 ret = request_irq(irq, db1100_mmc_cd, 0,
 193                                   "sd0_cd", mmc_host);
 194         } else
 195                 free_irq(irq, mmc_host);
 196         return ret;
 197 }
 198
 199 static int db1100_mmc1_cd_setup(void *mmc_host, int en)
 200 {
 201         int ret = 0, irq;
 202
 203         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 204                 irq = AU1100_GPIO20_INT;
 205         else
 206                 irq = AU1100_GPIO15_INT;        /* PB1100 SD1 CD# */
 207
 208         if (en) {
 209                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
 210                 ret = request_irq(irq, db1100_mmc_cd, 0,
 211                                   "sd1_cd", mmc_host);
 212         } else
 213                 free_irq(irq, mmc_host);
 214         return ret;
 215 }
 216
 217 static int db1100_mmc_card_readonly(void *mmc_host)
 218 {
 219         /* testing suggests that this bit is inverted */
 220         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
 221 }
 222
 223 static int db1100_mmc_card_inserted(void *mmc_host)
 224 {
 225         return !alchemy_gpio_get_value(19);
 226 }
 227
 228 static void db1100_mmc_set_power(void *mmc_host, int state)
 229 {
 230         int bit;
 231
 232         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 233                 bit = BCSR_BOARD_SD0PWR;
 234         else
 235                 bit = BCSR_BOARD_PB1100_SD0PWR;
 236
 237         if (state) {
 238                 bcsr_mod(BCSR_BOARD, 0, bit);
 239                 msleep(400);    /* stabilization time */
 240         } else
 241                 bcsr_mod(BCSR_BOARD, bit, 0);
 242 }
 243
 244 static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
 245 {
 246         if (b != LED_OFF)
 247                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
 248         else
 249                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
 250 }
 251
 252 static struct led_classdev db1100_mmc_led = {
 253         .brightness_set = db1100_mmcled_set,
 254 };
 255
 256 static int db1100_mmc1_card_readonly(void *mmc_host)
 257 {
 258         return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
 259 }
 260
 261 static int db1100_mmc1_card_inserted(void *mmc_host)
 262 {
 263         return !alchemy_gpio_get_value(20);
 264 }
 265
 266 static void db1100_mmc1_set_power(void *mmc_host, int state)
 267 {
 268         int bit;
 269
 270         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 271                 bit = BCSR_BOARD_SD1PWR;
 272         else
 273                 bit = BCSR_BOARD_PB1100_SD1PWR;
 274
 275         if (state) {
 276                 bcsr_mod(BCSR_BOARD, 0, bit);
 277                 msleep(400);    /* stabilization time */
 278         } else
 279                 bcsr_mod(BCSR_BOARD, bit, 0);
 280 }
 281
 282 static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
 283 {
 284         if (b != LED_OFF)
 285                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
 286         else
 287                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
 288 }
 289
 290 static struct led_classdev db1100_mmc1_led = {
 291         .brightness_set = db1100_mmc1led_set,
 292 };
 293
 294 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
 295         [0] = {
 296                 .cd_setup       = db1100_mmc_cd_setup,
 297                 .set_power      = db1100_mmc_set_power,
 298                 .card_inserted  = db1100_mmc_card_inserted,
 299                 .card_readonly  = db1100_mmc_card_readonly,
 300                 .led            = &db1100_mmc_led,
 301         },
 302         [1] = {
 303                 .cd_setup       = db1100_mmc1_cd_setup,
 304                 .set_power      = db1100_mmc1_set_power,
 305                 .card_inserted  = db1100_mmc1_card_inserted,
 306                 .card_readonly  = db1100_mmc1_card_readonly,
 307                 .led            = &db1100_mmc1_led,
 308         },
 309 };
 310
 311 static struct resource au1100_mmc0_resources[] = {
 312         [0] = {
 313                 .start  = AU1100_SD0_PHYS_ADDR,
 314                 .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
 315                 .flags  = IORESOURCE_MEM,
 316         },
 317         [1] = {
 318                 .start  = AU1100_SD_INT,
 319                 .end    = AU1100_SD_INT,
 320                 .flags  = IORESOURCE_IRQ,
 321         },
 322         [2] = {
 323                 .start  = DMA_ID_SD0_TX,
 324                 .end    = DMA_ID_SD0_TX,
 325                 .flags  = IORESOURCE_DMA,
 326         },
 327         [3] = {
 328                 .start  = DMA_ID_SD0_RX,
 329                 .end    = DMA_ID_SD0_RX,
 330                 .flags  = IORESOURCE_DMA,
 331         }
 332 };
 333
 334 static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
 335
 336 static struct platform_device db1100_mmc0_dev = {
 337         .name           = "au1xxx-mmc",
 338         .id             = 0,
 339         .dev = {
 340                 .dma_mask               = &au1xxx_mmc_dmamask,
 341                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 342                 .platform_data          = &db1100_mmc_platdata[0],
 343         },
 344         .num_resources  = ARRAY_SIZE(au1100_mmc0_resources),
 345         .resource       = au1100_mmc0_resources,
 346 };
 347
 348 static struct resource au1100_mmc1_res[] = {
 349         [0] = {
 350                 .start  = AU1100_SD1_PHYS_ADDR,
 351                 .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
 352                 .flags  = IORESOURCE_MEM,
 353         },
 354         [1] = {
 355                 .start  = AU1100_SD_INT,
 356                 .end    = AU1100_SD_INT,
 357                 .flags  = IORESOURCE_IRQ,
 358         },
 359         [2] = {
 360                 .start  = DMA_ID_SD1_TX,
 361                 .end    = DMA_ID_SD1_TX,
 362                 .flags  = IORESOURCE_DMA,
 363         },
 364         [3] = {
 365                 .start  = DMA_ID_SD1_RX,
 366                 .end    = DMA_ID_SD1_RX,
 367                 .flags  = IORESOURCE_DMA,
 368         }
 369 };
 370
 371 static struct platform_device db1100_mmc1_dev = {
 372         .name           = "au1xxx-mmc",
 373         .id             = 1,
 374         .dev = {
 375                 .dma_mask               = &au1xxx_mmc_dmamask,
 376                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 377                 .platform_data          = &db1100_mmc_platdata[1],
 378         },
 379         .num_resources  = ARRAY_SIZE(au1100_mmc1_res),
 380         .resource       = au1100_mmc1_res,
 381 };
 382
 383 /******************************************************************************/
 384
 385 static void db1000_irda_set_phy_mode(int mode)
 386 {
 387         unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL;
 388
 389         switch (mode) {
 390         case AU1000_IRDA_PHY_MODE_OFF:
 391                 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF);
 392                 break;
 393         case AU1000_IRDA_PHY_MODE_SIR:
 394                 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL);
 395                 break;
 396         case AU1000_IRDA_PHY_MODE_FIR:
 397                 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL |
 398                                             BCSR_RESETS_FIR_SEL);
 399                 break;
 400         }
 401 }
 402
 403 static struct au1k_irda_platform_data db1000_irda_platdata = {
 404         .set_phy_mode   = db1000_irda_set_phy_mode,
 405 };
 406
 407 static struct resource au1000_irda_res[] = {
 408         [0] = {
 409                 .start  = AU1000_IRDA_PHYS_ADDR,
 410                 .end    = AU1000_IRDA_PHYS_ADDR + 0x0fff,
 411                 .flags  = IORESOURCE_MEM,
 412         },
 413         [1] = {
 414                 .start  = AU1000_IRDA_TX_INT,
 415                 .end    = AU1000_IRDA_TX_INT,
 416                 .flags  = IORESOURCE_IRQ,
 417         },
 418         [2] = {
 419                 .start  = AU1000_IRDA_RX_INT,
 420                 .end    = AU1000_IRDA_RX_INT,
 421                 .flags  = IORESOURCE_IRQ,
 422         },
 423 };
 424
 425 static struct platform_device db1000_irda_dev = {
 426         .name   = "au1000-irda",
 427         .id     = -1,
 428         .dev    = {
 429                 .platform_data = &db1000_irda_platdata,
 430         },
 431         .resource       = au1000_irda_res,
 432         .num_resources  = ARRAY_SIZE(au1000_irda_res),
 433 };
 434
 435 /******************************************************************************/
 436
 437 static struct ads7846_platform_data db1100_touch_pd = {
 438         .model          = 7846,
 439         .vref_mv        = 3300,
 440         .gpio_pendown   = 21,
 441 };
 442
 443 static struct spi_gpio_platform_data db1100_spictl_pd = {
 444         .sck            = 209,
 445         .mosi           = 208,
 446         .miso           = 207,
 447         .num_chipselect = 1,
 448 };
 449
 450 static struct spi_board_info db1100_spi_info[] __initdata = {
 451         [0] = {
 452                 .modalias        = "ads7846",
 453                 .max_speed_hz    = 3250000,
 454                 .bus_num         = 0,
 455                 .chip_select     = 0,
 456                 .mode            = 0,
 457                 .irq             = AU1100_GPIO21_INT,
 458                 .platform_data   = &db1100_touch_pd,
 459                 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
 460         },
 461 };
 462
 463 static struct platform_device db1100_spi_dev = {
 464         .name           = "spi_gpio",
 465         .id             = 0,
 466         .dev            = {
 467                 .platform_data  = &db1100_spictl_pd,
 468         },
 469 };
 470
 471
 472 static struct platform_device *db1x00_devs[] = {
 473         &db1x00_codec_dev,
 474         &alchemy_ac97c_dma_dev,
 475         &alchemy_ac97c_dev,
 476         &db1x00_audio_dev,
 477 };
 478
 479 static struct platform_device *db1000_devs[] = {
 480         &db1000_irda_dev,
 481 };
 482
 483 static struct platform_device *db1100_devs[] = {
 484         &au1100_lcd_device,
 485         &db1100_mmc0_dev,
 486         &db1100_mmc1_dev,
 487         &db1000_irda_dev,
 488 };
 489
 490 int __init db1000_dev_setup(void)
 491 {
 492         int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 493         int c0, c1, d0, d1, s0, s1, flashsize = 32,  twosocks = 1;
 494         unsigned long pfc;
 495         struct clk *c, *p;
 496
 497         if (board == BCSR_WHOAMI_DB1500) {
 498                 c0 = AU1500_GPIO2_INT;
 499                 c1 = AU1500_GPIO5_INT;
 500                 d0 = 0; /* GPIO number, NOT irq! */
 501                 d1 = 3; /* GPIO number, NOT irq! */
 502                 s0 = AU1500_GPIO1_INT;
 503                 s1 = AU1500_GPIO4_INT;
 504         } else if (board == BCSR_WHOAMI_DB1100) {
 505                 c0 = AU1100_GPIO2_INT;
 506                 c1 = AU1100_GPIO5_INT;
 507                 d0 = 0; /* GPIO number, NOT irq! */
 508                 d1 = 3; /* GPIO number, NOT irq! */
 509                 s0 = AU1100_GPIO1_INT;
 510                 s1 = AU1100_GPIO4_INT;
 511
 512                 gpio_request(19, "sd0_cd");
 513                 gpio_request(20, "sd1_cd");
 514                 gpio_direction_input(19);       /* sd0 cd# */
 515                 gpio_direction_input(20);       /* sd1 cd# */
 516
 517                 /* spi_gpio on SSI0 pins */
 518                 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
 519                 pfc |= (1 << 0);        /* SSI0 pins as GPIOs */
 520                 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
 521
 522                 spi_register_board_info(db1100_spi_info,
 523                                         ARRAY_SIZE(db1100_spi_info));
 524
 525                 /* link LCD clock to AUXPLL */
 526                 p = clk_get(NULL, "auxpll_clk");
 527                 c = clk_get(NULL, "lcd_intclk");
 528                 if (!IS_ERR(c) && !IS_ERR(p)) {
 529                         clk_set_parent(c, p);
 530                         clk_set_rate(c, clk_get_rate(p));
 531                 }
 532                 if (!IS_ERR(c))
 533                         clk_put(c);
 534                 if (!IS_ERR(p))
 535                         clk_put(p);
 536
 537                 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
 538                 platform_device_register(&db1100_spi_dev);
 539         } else if (board == BCSR_WHOAMI_DB1000) {
 540                 c0 = AU1000_GPIO2_INT;
 541                 c1 = AU1000_GPIO5_INT;
 542                 d0 = 0; /* GPIO number, NOT irq! */
 543                 d1 = 3; /* GPIO number, NOT irq! */
 544                 s0 = AU1000_GPIO1_INT;
 545                 s1 = AU1000_GPIO4_INT;
 546                 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
 547         } else if ((board == BCSR_WHOAMI_PB1500) ||
 548                    (board == BCSR_WHOAMI_PB1500R2)) {
 549                 c0 = AU1500_GPIO203_INT;
 550                 d0 = 1; /* GPIO number, NOT irq! */
 551                 s0 = AU1500_GPIO202_INT;
 552                 twosocks = 0;
 553                 flashsize = 64;
 554                 /* RTC and daughtercard irqs */
 555                 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
 556                 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
 557                 /* EPSON S1D13806 0x1b000000
 558                  * SRAM 1MB/2MB   0x1a000000
 559                  * DS1693 RTC     0x0c000000
 560                  */
 561         } else if (board == BCSR_WHOAMI_PB1100) {
 562                 c0 = AU1100_GPIO11_INT;
 563                 d0 = 9; /* GPIO number, NOT irq! */
 564                 s0 = AU1100_GPIO10_INT;
 565                 twosocks = 0;
 566                 flashsize = 64;
 567                 /* pendown, rtc, daughtercard irqs */
 568                 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
 569                 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
 570                 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
 571                 /* EPSON S1D13806 0x1b000000
 572                  * SRAM 1MB/2MB   0x1a000000
 573                  * DiskOnChip     0x0d000000
 574                  * DS1693 RTC     0x0c000000
 575                  */
 576                 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
 577         } else
 578                 return 0; /* unknown board, no further dev setup to do */
 579
 580         irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
 581         irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
 582
 583         db1x_register_pcmcia_socket(
 584                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 585                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 586                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 587                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 588                 AU1000_PCMCIA_IO_PHYS_ADDR,
 589                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 590                 c0, d0, /*s0*/0, 0, 0);
 591
 592         if (twosocks) {
 593                 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
 594                 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
 595
 596                 db1x_register_pcmcia_socket(
 597                         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 598                         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 599                         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 600                         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 601                         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 602                         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 603                         c1, d1, /*s1*/0, 0, 1);
 604         }
 605
 606         platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
 607         db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
 608         return 0;
 609 }