4 * Exposes all configurable internal clock sources to the clk framework.
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
36 #include <linux/init.h>
38 #include <linux/clk.h>
39 #include <linux/clk-provider.h>
40 #include <linux/clkdev.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
44 #include <asm/mach-au1x00/au1000.h>
46 /* Base clock: 12MHz is the default in all databooks, and I haven't
47 * found any board yet which uses a different rate.
49 #define ALCHEMY_ROOTCLK_RATE 12000000
52 * the internal sources which can be driven by the PLLs and dividers.
53 * Names taken from the databooks, refer to them for more information,
54 * especially which ones are share a clock line.
56 static const char * const alchemy_au1300_intclknames[] = {
57 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
61 static const char * const alchemy_au1200_intclknames[] = {
62 "lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
65 static const char * const alchemy_au1550_intclknames[] = {
66 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
70 static const char * const alchemy_au1100_intclknames[] = {
71 "usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
74 static const char * const alchemy_au1500_intclknames[] = {
75 NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
78 static const char * const alchemy_au1000_intclknames[] = {
79 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
83 /* aliases for a few on-chip sources which are either shared
84 * or have gone through name changes.
86 static struct clk_aliastable {
90 } alchemy_clk_aliases[] __initdata = {
91 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
92 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
93 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
94 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
95 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
96 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
97 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
98 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
99 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
100 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
101 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
102 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
103 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
108 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
110 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
111 static spinlock_t alchemy_clk_fg0_lock;
112 static spinlock_t alchemy_clk_fg1_lock;
113 static spinlock_t alchemy_clk_csrc_lock;
115 /* CPU Core clock *****************************************************/
117 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
118 unsigned long parent_rate)
123 * On early Au1000, sys_cpupll was write-only. Since these
124 * silicon versions of Au1000 are not sold, we don't bend
125 * over backwards trying to determine the frequency.
127 if (unlikely(au1xxx_cpu_has_pll_wo()))
130 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
131 if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
139 void __init alchemy_set_lpj(void)
141 preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
142 preset_lpj /= 2 * HZ;
145 static struct clk_ops alchemy_clkops_cpu = {
146 .recalc_rate = alchemy_clk_cpu_recalc,
149 static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
152 struct clk_init_data id;
156 h = kzalloc(sizeof(*h), GFP_KERNEL);
158 return ERR_PTR(-ENOMEM);
160 id.name = ALCHEMY_CPU_CLK;
161 id.parent_names = &parent_name;
163 id.flags = CLK_IS_BASIC;
164 id.ops = &alchemy_clkops_cpu;
167 clk = clk_register(NULL, h);
169 pr_err("failed to register clock\n");
176 /* AUXPLLs ************************************************************/
178 struct alchemy_auxpll_clk {
180 unsigned long reg; /* au1300 has also AUXPLL2 */
181 int maxmult; /* max multiplier */
183 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
185 static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
186 unsigned long parent_rate)
188 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
190 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
193 static int alchemy_clk_aux_setr(struct clk_hw *hw,
195 unsigned long parent_rate)
197 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
198 unsigned long d = rate;
205 /* minimum is 84MHz, max is 756-1032 depending on variant */
206 if (((d < 7) && (d != 0)) || (d > a->maxmult))
209 alchemy_wrsys(d, a->reg);
213 static long alchemy_clk_aux_roundr(struct clk_hw *hw,
215 unsigned long *parent_rate)
217 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
220 if (!rate || !*parent_rate)
223 mult = rate / (*parent_rate);
225 if (mult && (mult < 7))
227 if (mult > a->maxmult)
230 return (*parent_rate) * mult;
233 static struct clk_ops alchemy_clkops_aux = {
234 .recalc_rate = alchemy_clk_aux_recalc,
235 .set_rate = alchemy_clk_aux_setr,
236 .round_rate = alchemy_clk_aux_roundr,
239 static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
240 char *name, int maxmult,
243 struct clk_init_data id;
245 struct alchemy_auxpll_clk *a;
247 a = kzalloc(sizeof(*a), GFP_KERNEL);
249 return ERR_PTR(-ENOMEM);
252 id.parent_names = &parent_name;
254 id.flags = CLK_GET_RATE_NOCACHE;
255 id.ops = &alchemy_clkops_aux;
258 a->maxmult = maxmult;
261 c = clk_register(NULL, &a->hw);
263 clk_register_clkdev(c, name, NULL);
270 /* sysbus_clk *********************************************************/
272 static struct clk __init *alchemy_clk_setup_sysbus(const char *pn)
274 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
277 c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
280 clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
284 /* Peripheral Clock ***************************************************/
286 static struct clk __init *alchemy_clk_setup_periph(const char *pn)
288 /* Peripheral clock runs at half the rate of sysbus clk */
291 c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
294 clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
298 /* mem clock **********************************************************/
300 static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
302 void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
308 case ALCHEMY_CPU_AU1550:
309 case ALCHEMY_CPU_AU1200:
310 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
311 div = (v & (1 << 15)) ? 1 : 2;
313 case ALCHEMY_CPU_AU1300:
314 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
315 div = (v & (1 << 31)) ? 1 : 2;
317 case ALCHEMY_CPU_AU1000:
318 case ALCHEMY_CPU_AU1500:
319 case ALCHEMY_CPU_AU1100:
325 c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
328 clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
332 /* lrclk: external synchronous static bus clock ***********************/
334 static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
336 /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
337 * otherwise lrclk=pclk/4.
338 * All other variants: MEM_STCFG0[15:13] = divisor.
339 * L/RCLK = periph_clk / (divisor + 1)
340 * On Au1000, Au1500, Au1100 it's called LCLK,
341 * on later models it's called RCLK, but it's the same thing.
344 unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
347 case ALCHEMY_CPU_AU1000:
348 case ALCHEMY_CPU_AU1500:
349 v = 4 + ((v >> 11) & 1);
351 default: /* all other models */
352 v = ((v >> 13) & 7) + 1;
354 c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
357 clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
361 /* Clock dividers and muxes *******************************************/
363 /* data for fgen and csrc mux-dividers */
364 struct alchemy_fgcs_clk {
366 spinlock_t *reglock; /* register lock */
367 unsigned long reg; /* SYS_FREQCTRL0/1 */
368 int shift; /* offset in register */
369 int parent; /* parent before disable [Au1300] */
370 int isen; /* is it enabled? */
371 int *dt; /* dividertable for csrc */
373 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
375 static long alchemy_calc_div(unsigned long rate, unsigned long prate,
376 int scale, int maxdiv, unsigned long *rv)
381 if ((prate / div1) > rate)
384 if (scale == 2) { /* only div-by-multiple-of-2 possible */
386 div1++; /* stay <=prate */
389 div2 = (div1 / scale) - 1; /* value to write to register */
396 div1 = ((div2 + 1) * scale);
400 static int alchemy_clk_fgcs_detr(struct clk_hw *hw,
401 struct clk_rate_request *req,
402 int scale, int maxdiv)
404 struct clk_hw *pc, *bpc, *free;
405 long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
414 /* look at the rates each enabled parent supplies and select
415 * the one that gets closest to but not over the requested rate.
417 for (j = 0; j < 7; j++) {
418 pc = clk_hw_get_parent_by_index(hw, j);
422 /* if this parent is currently unused, remember it.
423 * XXX: we would actually want clk_has_active_children()
424 * but this is a good-enough approximation for now.
426 if (!clk_hw_is_prepared(pc)) {
431 pr = clk_hw_get_rate(pc);
435 /* what can hardware actually provide */
436 tdv = alchemy_calc_div(req->rate, pr, scale, maxdiv, NULL);
438 diff = req->rate - nr;
442 if (diff < lastdiff) {
452 /* if we couldn't get the exact rate we wanted from the enabled
453 * parents, maybe we can tell an available disabled/inactive one
454 * to give us a rate we can divide down to the requested rate.
456 if (lastdiff && free) {
457 for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
461 pr = clk_hw_round_rate(free, tpr);
463 tdv = alchemy_calc_div(req->rate, pr, scale, maxdiv,
466 diff = req->rate - nr;
469 if (diff < lastdiff) {
483 req->best_parent_rate = bpr;
484 req->best_parent_hw = bpc;
490 static int alchemy_clk_fgv1_en(struct clk_hw *hw)
492 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
493 unsigned long v, flags;
495 spin_lock_irqsave(c->reglock, flags);
496 v = alchemy_rdsys(c->reg);
497 v |= (1 << 1) << c->shift;
498 alchemy_wrsys(v, c->reg);
499 spin_unlock_irqrestore(c->reglock, flags);
504 static int alchemy_clk_fgv1_isen(struct clk_hw *hw)
506 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
507 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
512 static void alchemy_clk_fgv1_dis(struct clk_hw *hw)
514 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
515 unsigned long v, flags;
517 spin_lock_irqsave(c->reglock, flags);
518 v = alchemy_rdsys(c->reg);
519 v &= ~((1 << 1) << c->shift);
520 alchemy_wrsys(v, c->reg);
521 spin_unlock_irqrestore(c->reglock, flags);
524 static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index)
526 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
527 unsigned long v, flags;
529 spin_lock_irqsave(c->reglock, flags);
530 v = alchemy_rdsys(c->reg);
532 v |= (1 << c->shift);
534 v &= ~(1 << c->shift);
535 alchemy_wrsys(v, c->reg);
536 spin_unlock_irqrestore(c->reglock, flags);
541 static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw)
543 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
545 return (alchemy_rdsys(c->reg) >> c->shift) & 1;
548 static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
549 unsigned long parent_rate)
551 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
552 unsigned long div, v, flags, ret;
553 int sh = c->shift + 2;
555 if (!rate || !parent_rate || rate > (parent_rate / 2))
557 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
558 spin_lock_irqsave(c->reglock, flags);
559 v = alchemy_rdsys(c->reg);
562 alchemy_wrsys(v, c->reg);
563 spin_unlock_irqrestore(c->reglock, flags);
568 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
569 unsigned long parent_rate)
571 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
572 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
574 v = ((v & 0xff) + 1) * 2;
575 return parent_rate / v;
578 static int alchemy_clk_fgv1_detr(struct clk_hw *hw,
579 struct clk_rate_request *req)
581 return alchemy_clk_fgcs_detr(hw, req, 2, 512);
584 /* Au1000, Au1100, Au15x0, Au12x0 */
585 static struct clk_ops alchemy_clkops_fgenv1 = {
586 .recalc_rate = alchemy_clk_fgv1_recalc,
587 .determine_rate = alchemy_clk_fgv1_detr,
588 .set_rate = alchemy_clk_fgv1_setr,
589 .set_parent = alchemy_clk_fgv1_setp,
590 .get_parent = alchemy_clk_fgv1_getp,
591 .enable = alchemy_clk_fgv1_en,
592 .disable = alchemy_clk_fgv1_dis,
593 .is_enabled = alchemy_clk_fgv1_isen,
596 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)
598 unsigned long v = alchemy_rdsys(c->reg);
600 v &= ~(3 << c->shift);
601 v |= (c->parent & 3) << c->shift;
602 alchemy_wrsys(v, c->reg);
606 static int alchemy_clk_fgv2_en(struct clk_hw *hw)
608 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
611 /* enable by setting the previous parent clock */
612 spin_lock_irqsave(c->reglock, flags);
613 __alchemy_clk_fgv2_en(c);
614 spin_unlock_irqrestore(c->reglock, flags);
619 static int alchemy_clk_fgv2_isen(struct clk_hw *hw)
621 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
623 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;
626 static void alchemy_clk_fgv2_dis(struct clk_hw *hw)
628 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
629 unsigned long v, flags;
631 spin_lock_irqsave(c->reglock, flags);
632 v = alchemy_rdsys(c->reg);
633 v &= ~(3 << c->shift); /* set input mux to "disabled" state */
634 alchemy_wrsys(v, c->reg);
636 spin_unlock_irqrestore(c->reglock, flags);
639 static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index)
641 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
644 spin_lock_irqsave(c->reglock, flags);
645 c->parent = index + 1; /* value to write to register */
647 __alchemy_clk_fgv2_en(c);
648 spin_unlock_irqrestore(c->reglock, flags);
653 static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw)
655 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
656 unsigned long flags, v;
658 spin_lock_irqsave(c->reglock, flags);
660 spin_unlock_irqrestore(c->reglock, flags);
664 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
665 * dividers behave exactly as on previous models (dividers are multiples
666 * of 2); with the bit set, dividers are multiples of 1, halving their
667 * range, but making them also much more flexible.
669 static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
670 unsigned long parent_rate)
672 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
673 int sh = c->shift + 2;
674 unsigned long div, v, flags, ret;
676 if (!rate || !parent_rate || rate > parent_rate)
679 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
680 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
681 v ? 256 : 512, &div);
683 spin_lock_irqsave(c->reglock, flags);
684 v = alchemy_rdsys(c->reg);
686 v |= (div & 0xff) << sh;
687 alchemy_wrsys(v, c->reg);
688 spin_unlock_irqrestore(c->reglock, flags);
693 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
694 unsigned long parent_rate)
696 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
697 int sh = c->shift + 2;
700 v = alchemy_rdsys(c->reg);
701 t = parent_rate / (((v >> sh) & 0xff) + 1);
702 if ((v & (1 << 30)) == 0) /* test scale bit */
708 static int alchemy_clk_fgv2_detr(struct clk_hw *hw,
709 struct clk_rate_request *req)
711 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
714 if (alchemy_rdsys(c->reg) & (1 << 30)) {
722 return alchemy_clk_fgcs_detr(hw, req, scale, maxdiv);
725 /* Au1300 larger input mux, no separate disable bit, flexible divider */
726 static struct clk_ops alchemy_clkops_fgenv2 = {
727 .recalc_rate = alchemy_clk_fgv2_recalc,
728 .determine_rate = alchemy_clk_fgv2_detr,
729 .set_rate = alchemy_clk_fgv2_setr,
730 .set_parent = alchemy_clk_fgv2_setp,
731 .get_parent = alchemy_clk_fgv2_getp,
732 .enable = alchemy_clk_fgv2_en,
733 .disable = alchemy_clk_fgv2_dis,
734 .is_enabled = alchemy_clk_fgv2_isen,
737 static const char * const alchemy_clk_fgv1_parents[] = {
738 ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
741 static const char * const alchemy_clk_fgv2_parents[] = {
742 ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
745 static const char * const alchemy_clk_fgen_names[] = {
746 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
747 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK };
749 static int __init alchemy_clk_init_fgens(int ctype)
752 struct clk_init_data id;
753 struct alchemy_fgcs_clk *a;
758 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
759 id.ops = &alchemy_clkops_fgenv1;
760 id.parent_names = alchemy_clk_fgv1_parents;
763 case ALCHEMY_CPU_AU1300:
764 id.ops = &alchemy_clkops_fgenv2;
765 id.parent_names = alchemy_clk_fgv2_parents;
771 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
773 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
777 spin_lock_init(&alchemy_clk_fg0_lock);
778 spin_lock_init(&alchemy_clk_fg1_lock);
780 for (i = 0; i < 6; i++) {
781 id.name = alchemy_clk_fgen_names[i];
782 a->shift = 10 * (i < 3 ? i : i - 3);
784 a->reg = AU1000_SYS_FREQCTRL1;
785 a->reglock = &alchemy_clk_fg1_lock;
787 a->reg = AU1000_SYS_FREQCTRL0;
788 a->reglock = &alchemy_clk_fg0_lock;
791 /* default to first parent if bootloader has set
792 * the mux to disabled state.
794 if (ctype == ALCHEMY_CPU_AU1300) {
795 v = alchemy_rdsys(a->reg);
796 a->parent = (v >> a->shift) & 3;
805 c = clk_register(NULL, &a->hw);
809 clk_register_clkdev(c, id.name, NULL);
816 /* internal sources muxes *********************************************/
818 static int alchemy_clk_csrc_isen(struct clk_hw *hw)
820 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
821 unsigned long v = alchemy_rdsys(c->reg);
823 return (((v >> c->shift) >> 2) & 7) != 0;
826 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)
828 unsigned long v = alchemy_rdsys(c->reg);
830 v &= ~((7 << 2) << c->shift);
831 v |= ((c->parent & 7) << 2) << c->shift;
832 alchemy_wrsys(v, c->reg);
836 static int alchemy_clk_csrc_en(struct clk_hw *hw)
838 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
841 /* enable by setting the previous parent clock */
842 spin_lock_irqsave(c->reglock, flags);
843 __alchemy_clk_csrc_en(c);
844 spin_unlock_irqrestore(c->reglock, flags);
849 static void alchemy_clk_csrc_dis(struct clk_hw *hw)
851 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
852 unsigned long v, flags;
854 spin_lock_irqsave(c->reglock, flags);
855 v = alchemy_rdsys(c->reg);
856 v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
857 alchemy_wrsys(v, c->reg);
859 spin_unlock_irqrestore(c->reglock, flags);
862 static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index)
864 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
867 spin_lock_irqsave(c->reglock, flags);
868 c->parent = index + 1; /* value to write to register */
870 __alchemy_clk_csrc_en(c);
871 spin_unlock_irqrestore(c->reglock, flags);
876 static u8 alchemy_clk_csrc_getp(struct clk_hw *hw)
878 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
880 return c->parent - 1;
883 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw,
884 unsigned long parent_rate)
886 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
887 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
889 return parent_rate / c->dt[v];
892 static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
893 unsigned long parent_rate)
895 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
896 unsigned long d, v, flags;
899 if (!rate || !parent_rate || rate > parent_rate)
902 d = (parent_rate + (rate / 2)) / rate;
905 if ((d == 3) && (c->dt[2] != 3))
908 for (i = 0; i < 4; i++)
913 return -EINVAL; /* oops */
915 spin_lock_irqsave(c->reglock, flags);
916 v = alchemy_rdsys(c->reg);
917 v &= ~(3 << c->shift);
918 v |= (i & 3) << c->shift;
919 alchemy_wrsys(v, c->reg);
920 spin_unlock_irqrestore(c->reglock, flags);
925 static int alchemy_clk_csrc_detr(struct clk_hw *hw,
926 struct clk_rate_request *req)
928 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
929 int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
931 return alchemy_clk_fgcs_detr(hw, req, scale, 4);
934 static struct clk_ops alchemy_clkops_csrc = {
935 .recalc_rate = alchemy_clk_csrc_recalc,
936 .determine_rate = alchemy_clk_csrc_detr,
937 .set_rate = alchemy_clk_csrc_setr,
938 .set_parent = alchemy_clk_csrc_setp,
939 .get_parent = alchemy_clk_csrc_getp,
940 .enable = alchemy_clk_csrc_en,
941 .disable = alchemy_clk_csrc_dis,
942 .is_enabled = alchemy_clk_csrc_isen,
945 static const char * const alchemy_clk_csrc_parents[] = {
946 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK,
947 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
948 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK
952 static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
953 static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
955 static int __init alchemy_clk_setup_imux(int ctype)
957 struct alchemy_fgcs_clk *a;
958 const char * const *names;
959 struct clk_init_data id;
964 id.ops = &alchemy_clkops_csrc;
965 id.parent_names = alchemy_clk_csrc_parents;
967 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
969 dt = alchemy_csrc_dt1;
971 case ALCHEMY_CPU_AU1000:
972 names = alchemy_au1000_intclknames;
974 case ALCHEMY_CPU_AU1500:
975 names = alchemy_au1500_intclknames;
977 case ALCHEMY_CPU_AU1100:
978 names = alchemy_au1100_intclknames;
980 case ALCHEMY_CPU_AU1550:
981 names = alchemy_au1550_intclknames;
983 case ALCHEMY_CPU_AU1200:
984 names = alchemy_au1200_intclknames;
986 case ALCHEMY_CPU_AU1300:
987 dt = alchemy_csrc_dt2;
988 names = alchemy_au1300_intclknames;
994 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
998 spin_lock_init(&alchemy_clk_csrc_lock);
1001 for (i = 0; i < 6; i++) {
1007 a->reg = AU1000_SYS_CLKSRC;
1008 a->reglock = &alchemy_clk_csrc_lock;
1011 /* default to first parent clock if mux is initially
1012 * set to disabled state.
1014 v = alchemy_rdsys(a->reg);
1015 a->parent = ((v >> a->shift) >> 2) & 7;
1023 c = clk_register(NULL, &a->hw);
1027 clk_register_clkdev(c, id.name, NULL);
1036 /**********************************************************************/
1045 static int __init alchemy_clk_init(void)
1047 int ctype = alchemy_get_cputype(), ret, i;
1048 struct clk_aliastable *t = alchemy_clk_aliases;
1051 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1052 c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
1054 ALCHEMY_ROOTCLK_RATE);
1057 /* CPU core clock */
1058 c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);
1061 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1062 i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63;
1063 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,
1064 i, AU1000_SYS_AUXPLL);
1067 if (ctype == ALCHEMY_CPU_AU1300) {
1068 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,
1069 ALCHEMY_AUXPLL2_CLK, i,
1070 AU1300_SYS_AUXPLL2);
1074 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1075 c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);
1078 /* peripheral clock: runs at half rate of sysbus clk */
1079 c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);
1082 /* SDR/DDR memory clock */
1083 c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);
1086 /* L/RCLK: external static bus clock for synchronous mode */
1087 c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
1090 /* Frequency dividers 0-5 */
1091 ret = alchemy_clk_init_fgens(ctype);
1097 /* diving muxes for internal sources */
1098 ret = alchemy_clk_setup_imux(ctype);
1104 /* set up aliases drivers might look for */
1106 if (t->cputype == ctype)
1107 clk_add_alias(t->alias, NULL, t->base, NULL);
1111 pr_info("Alchemy clocktree installed\n");
1117 postcore_initcall(alchemy_clk_init);