1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNLEN_USER
16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
17 select ARCH_HAS_UBSAN_SANITIZE_ALL
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_KEEP_MEMBLOCK
20 select ARCH_USE_BUILTIN_BSWAP
21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
22 select ARCH_USE_MEMTEST
23 select ARCH_USE_QUEUED_RWLOCKS
24 select ARCH_USE_QUEUED_SPINLOCKS
25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
27 select ARCH_WANT_IPC_PARSE_VERSION
28 select ARCH_WANT_LD_ORPHAN_WARN
29 select BUILDTIME_TABLE_SORT
30 select CLONE_BACKWARDS
31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
32 select CPU_PM if CPU_IDLE
33 select GENERIC_ATOMIC64 if !64BIT
34 select GENERIC_CMOS_UPDATE
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_GETTIMEOFDAY
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_ISA_DMA if EISA
41 select GENERIC_LIB_ASHLDI3
42 select GENERIC_LIB_ASHRDI3
43 select GENERIC_LIB_CMPDI2
44 select GENERIC_LIB_LSHRDI3
45 select GENERIC_LIB_UCMPDI2
46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_IDLE_POLL_SETUP
49 select GENERIC_TIME_VSYSCALL
50 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
51 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
52 select HAVE_ARCH_COMPILER_H
53 select HAVE_ARCH_JUMP_LABEL
54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
55 select HAVE_ARCH_MMAP_RND_BITS if MMU
56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
60 select HAVE_ASM_MODVERSIONS
61 select HAVE_CONTEXT_TRACKING_USER
63 select HAVE_C_RECORDMCOUNT
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DEBUG_STACKOVERFLOW
66 select HAVE_DMA_CONTIGUOUS
67 select HAVE_DYNAMIC_FTRACE
68 select HAVE_EBPF_JIT if !CPU_MICROMIPS
69 select HAVE_EXIT_THREAD
71 select HAVE_FTRACE_MCOUNT_RECORD
72 select HAVE_FUNCTION_GRAPH_TRACER
73 select HAVE_FUNCTION_TRACER
74 select HAVE_GCC_PLUGINS
75 select HAVE_GENERIC_VDSO
76 select HAVE_IOREMAP_PROT
77 select HAVE_IRQ_EXIT_ON_IRQ_STACK
78 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_KRETPROBES
81 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
82 select HAVE_MOD_ARCH_SPECIFIC
84 select HAVE_PERF_EVENTS
86 select HAVE_PERF_USER_STACK_DUMP
87 select HAVE_REGS_AND_STACK_ACCESS_API
89 select HAVE_SPARSE_SYSCALL_NR
90 select HAVE_STACKPROTECTOR
91 select HAVE_SYSCALL_TRACEPOINTS
92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
93 select IRQ_FORCED_THREADING
95 select LOCK_MM_AND_FIND_VMA
96 select MODULES_USE_ELF_REL if MODULES
97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
98 select PERF_USE_VMALLOC
99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
101 select SYSCTL_EXCEPTION_TRACE
102 select TRACE_IRQFLAGS_SUPPORT
103 select ARCH_HAS_ELFCORE_COMPAT
104 select HAVE_ARCH_KCSAN if 64BIT
106 config MIPS_FIXUP_BIGPHYS_ADDR
114 select SYS_SUPPORTS_32BIT_KERNEL
115 select SYS_SUPPORTS_LITTLE_ENDIAN
116 select SYS_SUPPORTS_ZBOOT
117 select DMA_NONCOHERENT
122 select GENERIC_IRQ_CHIP
123 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
125 select CPU_SUPPORTS_CPUFREQ
126 select MIPS_EXTERNAL_TIMER
128 menu "Machine selection"
132 default MIPS_GENERIC_KERNEL
134 config MIPS_GENERIC_KERNEL
135 bool "Generic board-agnostic MIPS kernel"
140 select CLKSRC_MIPS_GIC
142 select CPU_MIPSR2_IRQ_EI
143 select CPU_MIPSR2_IRQ_VI
145 select DMA_NONCOHERENT
148 select MIPS_AUTO_PFN_OFFSET
149 select MIPS_CPU_SCACHE
151 select MIPS_L1_CACHE_SHIFT_7
152 select NO_EXCEPT_FILL
153 select PCI_DRIVERS_GENERIC
156 select SYS_HAS_CPU_MIPS32_R1
157 select SYS_HAS_CPU_MIPS32_R2
158 select SYS_HAS_CPU_MIPS32_R5
159 select SYS_HAS_CPU_MIPS32_R6
160 select SYS_HAS_CPU_MIPS64_R1
161 select SYS_HAS_CPU_MIPS64_R2
162 select SYS_HAS_CPU_MIPS64_R5
163 select SYS_HAS_CPU_MIPS64_R6
164 select SYS_SUPPORTS_32BIT_KERNEL
165 select SYS_SUPPORTS_64BIT_KERNEL
166 select SYS_SUPPORTS_BIG_ENDIAN
167 select SYS_SUPPORTS_HIGHMEM
168 select SYS_SUPPORTS_LITTLE_ENDIAN
169 select SYS_SUPPORTS_MICROMIPS
170 select SYS_SUPPORTS_MIPS16
171 select SYS_SUPPORTS_MIPS_CPS
172 select SYS_SUPPORTS_MULTITHREADING
173 select SYS_SUPPORTS_RELOCATABLE
174 select SYS_SUPPORTS_SMARTMIPS
175 select SYS_SUPPORTS_ZBOOT
177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
185 Select this to build a kernel which aims to support multiple boards,
186 generally using a flattened device tree passed from the bootloader
187 using the boot protocol defined in the UHI (Unified Hosting
188 Interface) specification.
191 bool "Alchemy processor based machines"
192 select PHYS_ADDR_T_64BIT
196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
198 select SYS_HAS_CPU_MIPS32_R1
199 select SYS_SUPPORTS_32BIT_KERNEL
200 select SYS_SUPPORTS_APM_EMULATION
202 select SYS_SUPPORTS_ZBOOT
206 bool "Atheros AR231x/AR531x SoC support"
209 select DMA_NONCOHERENT
212 select SYS_HAS_CPU_MIPS32_R1
213 select SYS_SUPPORTS_BIG_ENDIAN
214 select SYS_SUPPORTS_32BIT_KERNEL
215 select SYS_HAS_EARLY_PRINTK
217 Support for Atheros AR231x and Atheros AR531x based boards
220 bool "Atheros AR71XX/AR724X/AR913X based boards"
221 select ARCH_HAS_RESET_CONTROLLER
225 select DMA_NONCOHERENT
230 select SYS_HAS_CPU_MIPS32_R2
231 select SYS_HAS_EARLY_PRINTK
232 select SYS_SUPPORTS_32BIT_KERNEL
233 select SYS_SUPPORTS_BIG_ENDIAN
234 select SYS_SUPPORTS_MIPS16
235 select SYS_SUPPORTS_ZBOOT_UART_PROM
237 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
239 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
242 bool "Broadcom Generic BMIPS kernel"
243 select ARCH_HAS_RESET_CONTROLLER
244 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
246 select NO_EXCEPT_FILL
252 select BCM6345_L1_IRQ
253 select BCM7038_L1_IRQ
254 select BCM7120_L2_IRQ
255 select BRCMSTB_L2_IRQ
257 select DMA_NONCOHERENT
258 select SYS_SUPPORTS_32BIT_KERNEL
259 select SYS_SUPPORTS_LITTLE_ENDIAN
260 select SYS_SUPPORTS_BIG_ENDIAN
261 select SYS_SUPPORTS_HIGHMEM
262 select SYS_HAS_CPU_BMIPS32_3300
263 select SYS_HAS_CPU_BMIPS4350
264 select SYS_HAS_CPU_BMIPS4380
265 select SYS_HAS_CPU_BMIPS5000
267 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
268 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
269 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
270 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
271 select HARDIRQS_SW_RESEND
273 select PCI_DRIVERS_GENERIC
276 Build a generic DT-based kernel image that boots on select
277 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
278 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
279 must be set appropriately for your board.
282 bool "Broadcom BCM47XX based boards"
286 select DMA_NONCOHERENT
289 select SYS_HAS_CPU_MIPS32_R1
290 select NO_EXCEPT_FILL
291 select SYS_SUPPORTS_32BIT_KERNEL
292 select SYS_SUPPORTS_LITTLE_ENDIAN
293 select SYS_SUPPORTS_MIPS16
294 select SYS_SUPPORTS_ZBOOT
295 select SYS_HAS_EARLY_PRINTK
296 select USE_GENERIC_EARLY_PRINTK_8250
298 select LEDS_GPIO_REGISTER
301 select BCM47XX_SSB if !BCM47XX_BCMA
303 Support for BCM47XX based boards
306 bool "Broadcom BCM63XX based boards"
311 select DMA_NONCOHERENT
313 select SYS_SUPPORTS_32BIT_KERNEL
314 select SYS_SUPPORTS_BIG_ENDIAN
315 select SYS_HAS_EARLY_PRINTK
316 select SYS_HAS_CPU_BMIPS32_3300
317 select SYS_HAS_CPU_BMIPS4350
318 select SYS_HAS_CPU_BMIPS4380
321 select MIPS_L1_CACHE_SHIFT_4
322 select HAVE_LEGACY_CLK
324 Support for BCM63XX based boards
331 select DMA_NONCOHERENT
337 select PCI_GT64XXX_PCI0
338 select SYS_HAS_CPU_NEVADA
339 select SYS_HAS_EARLY_PRINTK
340 select SYS_SUPPORTS_32BIT_KERNEL
341 select SYS_SUPPORTS_64BIT_KERNEL
342 select SYS_SUPPORTS_LITTLE_ENDIAN
343 select USE_GENERIC_EARLY_PRINTK_8250
345 config MACH_DECSTATION
349 select CEVT_R4K if CPU_R4X00
351 select CSRC_R4K if CPU_R4X00
352 select CPU_DADDI_WORKAROUNDS if 64BIT
353 select CPU_R4000_WORKAROUNDS if 64BIT
354 select CPU_R4400_WORKAROUNDS if 64BIT
355 select DMA_NONCOHERENT
358 select SYS_HAS_CPU_R3000
359 select SYS_HAS_CPU_R4X00
360 select SYS_SUPPORTS_32BIT_KERNEL
361 select SYS_SUPPORTS_64BIT_KERNEL
362 select SYS_SUPPORTS_LITTLE_ENDIAN
363 select SYS_SUPPORTS_128HZ
364 select SYS_SUPPORTS_256HZ
365 select SYS_SUPPORTS_1024HZ
366 select MIPS_L1_CACHE_SHIFT_4
368 This enables support for DEC's MIPS based workstations. For details
369 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
370 DECstation porting pages on <http://decstation.unix-ag.org/>.
372 If you have one of the following DECstation Models you definitely
373 want to choose R4xx0 for the CPU Type:
380 otherwise choose R3000.
383 bool "Jazz family of machines"
386 select ARCH_MIGHT_HAVE_PC_PARPORT
387 select ARCH_MIGHT_HAVE_PC_SERIO
391 select ARCH_MAY_HAVE_PC_FDC
394 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
395 select GENERIC_ISA_DMA
396 select HAVE_PCSPKR_PLATFORM
401 select SYS_HAS_CPU_R4X00
402 select SYS_SUPPORTS_32BIT_KERNEL
403 select SYS_SUPPORTS_64BIT_KERNEL
404 select SYS_SUPPORTS_100HZ
405 select SYS_SUPPORTS_LITTLE_ENDIAN
407 This a family of machines based on the MIPS R4030 chipset which was
408 used by several vendors to build RISC/os and Windows NT workstations.
409 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
410 Olivetti M700-10 workstations.
412 config MACH_INGENIC_SOC
413 bool "Ingenic SoC based machines"
416 select SYS_SUPPORTS_ZBOOT_UART16550
417 select CPU_SUPPORTS_CPUFREQ
418 select MIPS_EXTERNAL_TIMER
421 bool "Lantiq based platforms"
422 select DMA_NONCOHERENT
426 select NO_EXCEPT_FILL
427 select SYS_HAS_CPU_MIPS32_R1
428 select SYS_HAS_CPU_MIPS32_R2
429 select SYS_SUPPORTS_BIG_ENDIAN
430 select SYS_SUPPORTS_32BIT_KERNEL
431 select SYS_SUPPORTS_MIPS16
432 select SYS_SUPPORTS_MULTITHREADING
433 select SYS_SUPPORTS_VPE_LOADER
434 select SYS_HAS_EARLY_PRINTK
438 select HAVE_LEGACY_CLK
441 select PINCTRL_LANTIQ
442 select ARCH_HAS_RESET_CONTROLLER
443 select RESET_CONTROLLER
445 config MACH_LOONGSON32
446 bool "Loongson 32-bit family of machines"
447 select SYS_SUPPORTS_ZBOOT
449 This enables support for the Loongson-1 family of machines.
451 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
452 the Institute of Computing Technology (ICT), Chinese Academy of
455 config MACH_LOONGSON2EF
456 bool "Loongson-2E/F family of machines"
457 select SYS_SUPPORTS_ZBOOT
459 This enables the support of early Loongson-2E/F family of machines.
461 config MACH_LOONGSON64
462 bool "Loongson 64-bit family of machines"
463 select ARCH_DMA_DEFAULT_COHERENT
464 select ARCH_SPARSEMEM_ENABLE
465 select ARCH_MIGHT_HAVE_PC_PARPORT
466 select ARCH_MIGHT_HAVE_PC_SERIO
467 select GENERIC_ISA_DMA_SUPPORT_BROKEN
476 select NO_EXCEPT_FILL
477 select NR_CPUS_DEFAULT_64
478 select USE_GENERIC_EARLY_PRINTK_8250
479 select PCI_DRIVERS_GENERIC
480 select SYS_HAS_CPU_LOONGSON64
481 select SYS_HAS_EARLY_PRINTK
482 select SYS_SUPPORTS_SMP
483 select SYS_SUPPORTS_HOTPLUG_CPU
484 select SYS_SUPPORTS_NUMA
485 select SYS_SUPPORTS_64BIT_KERNEL
486 select SYS_SUPPORTS_HIGHMEM
487 select SYS_SUPPORTS_LITTLE_ENDIAN
488 select SYS_SUPPORTS_ZBOOT
489 select SYS_SUPPORTS_RELOCATABLE
494 select PCI_HOST_GENERIC
495 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
497 This enables the support of Loongson-2/3 family of machines.
499 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
500 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
501 and Loongson-2F which will be removed), developed by the Institute
502 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
505 bool "MIPS Malta board"
506 select ARCH_MAY_HAVE_PC_FDC
507 select ARCH_MIGHT_HAVE_PC_PARPORT
508 select ARCH_MIGHT_HAVE_PC_SERIO
513 select CLKSRC_MIPS_GIC
516 select DMA_NONCOHERENT
517 select GENERIC_ISA_DMA
518 select HAVE_PCSPKR_PLATFORM
524 select MIPS_CPU_SCACHE
526 select MIPS_L1_CACHE_SHIFT_6
528 select PCI_GT64XXX_PCI0
531 select SYS_HAS_CPU_MIPS32_R1
532 select SYS_HAS_CPU_MIPS32_R2
533 select SYS_HAS_CPU_MIPS32_R3_5
534 select SYS_HAS_CPU_MIPS32_R5
535 select SYS_HAS_CPU_MIPS32_R6
536 select SYS_HAS_CPU_MIPS64_R1
537 select SYS_HAS_CPU_MIPS64_R2
538 select SYS_HAS_CPU_MIPS64_R6
539 select SYS_HAS_CPU_NEVADA
540 select SYS_HAS_CPU_RM7000
541 select SYS_SUPPORTS_32BIT_KERNEL
542 select SYS_SUPPORTS_64BIT_KERNEL
543 select SYS_SUPPORTS_BIG_ENDIAN
544 select SYS_SUPPORTS_HIGHMEM
545 select SYS_SUPPORTS_LITTLE_ENDIAN
546 select SYS_SUPPORTS_MICROMIPS
547 select SYS_SUPPORTS_MIPS16
548 select SYS_SUPPORTS_MIPS_CPS
549 select SYS_SUPPORTS_MULTITHREADING
550 select SYS_SUPPORTS_RELOCATABLE
551 select SYS_SUPPORTS_SMARTMIPS
552 select SYS_SUPPORTS_VPE_LOADER
553 select SYS_SUPPORTS_ZBOOT
555 select WAR_ICACHE_REFILLS
556 select ZONE_DMA32 if 64BIT
558 This enables support for the MIPS Technologies Malta evaluation
562 bool "Microchip PIC32 Family"
564 This enables support for the Microchip PIC32 family of platforms.
566 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
569 config MACH_NINTENDO64
570 bool "Nintendo 64 console"
573 select SYS_HAS_CPU_R4300
574 select SYS_SUPPORTS_BIG_ENDIAN
575 select SYS_SUPPORTS_ZBOOT
576 select SYS_SUPPORTS_32BIT_KERNEL
577 select SYS_SUPPORTS_64BIT_KERNEL
578 select DMA_NONCOHERENT
582 bool "Ralink based machines"
587 select DMA_NONCOHERENT
590 select SYS_HAS_CPU_MIPS32_R2
591 select SYS_SUPPORTS_32BIT_KERNEL
592 select SYS_SUPPORTS_LITTLE_ENDIAN
593 select SYS_SUPPORTS_MIPS16
594 select SYS_SUPPORTS_ZBOOT
595 select SYS_HAS_EARLY_PRINTK
596 select ARCH_HAS_RESET_CONTROLLER
597 select RESET_CONTROLLER
599 config MACH_REALTEK_RTL
600 bool "Realtek RTL838x/RTL839x based machines"
602 select DMA_NONCOHERENT
606 select SYS_HAS_CPU_MIPS32_R1
607 select SYS_HAS_CPU_MIPS32_R2
608 select SYS_SUPPORTS_BIG_ENDIAN
609 select SYS_SUPPORTS_32BIT_KERNEL
610 select SYS_SUPPORTS_MIPS16
611 select SYS_SUPPORTS_MULTITHREADING
612 select SYS_SUPPORTS_VPE_LOADER
618 bool "SGI IP22 (Indy/Indigo2)"
623 select ARCH_MIGHT_HAVE_PC_SERIO
627 select DEFAULT_SGI_PARTITION
628 select DMA_NONCOHERENT
632 select IP22_CPU_SCACHE
634 select GENERIC_ISA_DMA_SUPPORT_BROKEN
636 select SGI_HAS_INDYDOG
642 select SYS_HAS_CPU_R4X00
643 select SYS_HAS_CPU_R5000
644 select SYS_HAS_EARLY_PRINTK
645 select SYS_SUPPORTS_32BIT_KERNEL
646 select SYS_SUPPORTS_64BIT_KERNEL
647 select SYS_SUPPORTS_BIG_ENDIAN
648 select WAR_R4600_V1_INDEX_ICACHEOP
649 select WAR_R4600_V1_HIT_CACHEOP
650 select WAR_R4600_V2_HIT_CACHEOP
651 select MIPS_L1_CACHE_SHIFT_7
653 This are the SGI Indy, Challenge S and Indigo2, as well as certain
654 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
655 that runs on these, say Y here.
658 bool "SGI IP27 (Origin200/2000)"
659 select ARCH_HAS_PHYS_TO_DMA
660 select ARCH_SPARSEMEM_ENABLE
663 select ARC_CMDLINE_ONLY
665 select DEFAULT_SGI_PARTITION
667 select SYS_HAS_EARLY_PRINTK
670 select IRQ_DOMAIN_HIERARCHY
671 select NR_CPUS_DEFAULT_64
672 select PCI_DRIVERS_GENERIC
673 select PCI_XTALK_BRIDGE
674 select SYS_HAS_CPU_R10000
675 select SYS_SUPPORTS_64BIT_KERNEL
676 select SYS_SUPPORTS_BIG_ENDIAN
677 select SYS_SUPPORTS_NUMA
678 select SYS_SUPPORTS_SMP
679 select WAR_R10000_LLSC
680 select MIPS_L1_CACHE_SHIFT_7
682 select HAVE_ARCH_NODEDATA_EXTENSION
684 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
685 workstations. To compile a Linux kernel that runs on these, say Y
689 bool "SGI IP28 (Indigo2 R10k)"
694 select ARCH_MIGHT_HAVE_PC_SERIO
698 select DEFAULT_SGI_PARTITION
699 select DMA_NONCOHERENT
700 select GENERIC_ISA_DMA_SUPPORT_BROKEN
706 select SGI_HAS_INDYDOG
712 select SYS_HAS_CPU_R10000
713 select SYS_HAS_EARLY_PRINTK
714 select SYS_SUPPORTS_64BIT_KERNEL
715 select SYS_SUPPORTS_BIG_ENDIAN
716 select WAR_R10000_LLSC
717 select MIPS_L1_CACHE_SHIFT_7
719 This is the SGI Indigo2 with R10000 processor. To compile a Linux
720 kernel that runs on these, say Y here.
723 bool "SGI IP30 (Octane/Octane2)"
724 select ARCH_HAS_PHYS_TO_DMA
731 select SYNC_R4K if SMP
735 select IRQ_DOMAIN_HIERARCHY
736 select PCI_DRIVERS_GENERIC
737 select PCI_XTALK_BRIDGE
738 select SYS_HAS_EARLY_PRINTK
739 select SYS_HAS_CPU_R10000
740 select SYS_SUPPORTS_64BIT_KERNEL
741 select SYS_SUPPORTS_BIG_ENDIAN
742 select SYS_SUPPORTS_SMP
743 select WAR_R10000_LLSC
744 select MIPS_L1_CACHE_SHIFT_7
747 These are the SGI Octane and Octane2 graphics workstations. To
748 compile a Linux kernel that runs on these, say Y here.
754 select ARCH_HAS_PHYS_TO_DMA
760 select DMA_NONCOHERENT
763 select R5000_CPU_SCACHE
764 select RM7000_CPU_SCACHE
765 select SYS_HAS_CPU_R5000
766 select SYS_HAS_CPU_R10000 if BROKEN
767 select SYS_HAS_CPU_RM7000
768 select SYS_HAS_CPU_NEVADA
769 select SYS_SUPPORTS_64BIT_KERNEL
770 select SYS_SUPPORTS_BIG_ENDIAN
771 select WAR_ICACHE_REFILLS
773 If you want this kernel to run on SGI O2 workstation, say Y here.
776 bool "Sibyte BCM91125C-CRhone"
778 select SIBYTE_BCM1125
780 select SYS_HAS_CPU_SB1
781 select SYS_SUPPORTS_BIG_ENDIAN
782 select SYS_SUPPORTS_HIGHMEM
783 select SYS_SUPPORTS_LITTLE_ENDIAN
786 bool "Sibyte BCM91125E-Rhone"
790 select SYS_HAS_CPU_SB1
791 select SYS_SUPPORTS_BIG_ENDIAN
792 select SYS_SUPPORTS_LITTLE_ENDIAN
795 bool "Sibyte BCM91250A-SWARM"
797 select HAVE_PATA_PLATFORM
800 select SYS_HAS_CPU_SB1
801 select SYS_SUPPORTS_BIG_ENDIAN
802 select SYS_SUPPORTS_HIGHMEM
803 select SYS_SUPPORTS_LITTLE_ENDIAN
804 select ZONE_DMA32 if 64BIT
805 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
807 config SIBYTE_LITTLESUR
808 bool "Sibyte BCM91250C2-LittleSur"
810 select HAVE_PATA_PLATFORM
813 select SYS_HAS_CPU_SB1
814 select SYS_SUPPORTS_BIG_ENDIAN
815 select SYS_SUPPORTS_HIGHMEM
816 select SYS_SUPPORTS_LITTLE_ENDIAN
817 select ZONE_DMA32 if 64BIT
819 config SIBYTE_SENTOSA
820 bool "Sibyte BCM91250E-Sentosa"
824 select SYS_HAS_CPU_SB1
825 select SYS_SUPPORTS_BIG_ENDIAN
826 select SYS_SUPPORTS_LITTLE_ENDIAN
827 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
830 bool "Sibyte BCM91480B-BigSur"
832 select NR_CPUS_DEFAULT_4
833 select SIBYTE_BCM1x80
835 select SYS_HAS_CPU_SB1
836 select SYS_SUPPORTS_BIG_ENDIAN
837 select SYS_SUPPORTS_HIGHMEM
838 select SYS_SUPPORTS_LITTLE_ENDIAN
839 select ZONE_DMA32 if 64BIT
840 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
843 bool "SNI RM200/300/400"
846 select FW_ARC if CPU_LITTLE_ENDIAN
847 select FW_ARC32 if CPU_LITTLE_ENDIAN
848 select FW_SNIPROM if CPU_BIG_ENDIAN
849 select ARCH_MAY_HAVE_PC_FDC
850 select ARCH_MIGHT_HAVE_PC_PARPORT
851 select ARCH_MIGHT_HAVE_PC_SERIO
855 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
856 select DMA_NONCOHERENT
857 select GENERIC_ISA_DMA
859 select HAVE_PCSPKR_PLATFORM
865 select MIPS_L1_CACHE_SHIFT_6
866 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
867 select SYS_HAS_CPU_R4X00
868 select SYS_HAS_CPU_R5000
869 select SYS_HAS_CPU_R10000
870 select R5000_CPU_SCACHE
871 select SYS_HAS_EARLY_PRINTK
872 select SYS_SUPPORTS_32BIT_KERNEL
873 select SYS_SUPPORTS_64BIT_KERNEL
874 select SYS_SUPPORTS_BIG_ENDIAN
875 select SYS_SUPPORTS_HIGHMEM
876 select SYS_SUPPORTS_LITTLE_ENDIAN
877 select WAR_R4600_V2_HIT_CACHEOP
879 The SNI RM200/300/400 are MIPS-based machines manufactured by
880 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
881 Technology and now in turn merged with Fujitsu. Say Y here to
882 support this machine type.
885 bool "Toshiba TX49 series based machines"
886 select WAR_TX49XX_ICACHE_INDEX_INV
888 config MIKROTIK_RB532
889 bool "Mikrotik RB532 boards"
892 select DMA_NONCOHERENT
895 select SYS_HAS_CPU_MIPS32_R1
896 select SYS_SUPPORTS_32BIT_KERNEL
897 select SYS_SUPPORTS_LITTLE_ENDIAN
901 select MIPS_L1_CACHE_SHIFT_4
903 Support the Mikrotik(tm) RouterBoard 532 series,
904 based on the IDT RC32434 SoC.
906 config CAVIUM_OCTEON_SOC
907 bool "Cavium Networks Octeon SoC based boards"
909 select ARCH_HAS_PHYS_TO_DMA
911 select PHYS_ADDR_T_64BIT
912 select SYS_SUPPORTS_64BIT_KERNEL
913 select SYS_SUPPORTS_BIG_ENDIAN
915 select EDAC_ATOMIC_SCRUB
916 select SYS_SUPPORTS_LITTLE_ENDIAN
917 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
918 select SYS_HAS_EARLY_PRINTK
919 select SYS_HAS_CPU_CAVIUM_OCTEON
921 select HAVE_PLAT_DELAY
922 select HAVE_PLAT_FW_INIT_CMDLINE
923 select HAVE_PLAT_MEMCPY
927 select ARCH_SPARSEMEM_ENABLE
928 select SYS_SUPPORTS_SMP
929 select NR_CPUS_DEFAULT_64
930 select MIPS_NR_CPU_NR_MAP_1024
933 select MTD_COMPLEX_MAPPINGS
935 select SYS_SUPPORTS_RELOCATABLE
937 This option supports all of the Octeon reference boards from Cavium
938 Networks. It builds a kernel that dynamically determines the Octeon
939 CPU type and supports all known board reference implementations.
940 Some of the supported boards are:
947 Say Y here for most Octeon reference boards.
951 source "arch/mips/alchemy/Kconfig"
952 source "arch/mips/ath25/Kconfig"
953 source "arch/mips/ath79/Kconfig"
954 source "arch/mips/bcm47xx/Kconfig"
955 source "arch/mips/bcm63xx/Kconfig"
956 source "arch/mips/bmips/Kconfig"
957 source "arch/mips/generic/Kconfig"
958 source "arch/mips/ingenic/Kconfig"
959 source "arch/mips/jazz/Kconfig"
960 source "arch/mips/lantiq/Kconfig"
961 source "arch/mips/pic32/Kconfig"
962 source "arch/mips/ralink/Kconfig"
963 source "arch/mips/sgi-ip27/Kconfig"
964 source "arch/mips/sibyte/Kconfig"
965 source "arch/mips/txx9/Kconfig"
966 source "arch/mips/cavium-octeon/Kconfig"
967 source "arch/mips/loongson2ef/Kconfig"
968 source "arch/mips/loongson32/Kconfig"
969 source "arch/mips/loongson64/Kconfig"
973 config GENERIC_HWEIGHT
977 config GENERIC_CALIBRATE_DELAY
981 config SCHED_OMIT_FRAME_POINTER
986 # Select some configuration options automatically based on user selections.
991 config ARCH_MAY_HAVE_PC_FDC
1022 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1028 config MIPS_CLOCK_VSYSCALL
1029 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
1038 config ARCH_SUPPORTS_UPROBES
1041 config DMA_NONCOHERENT
1044 # MIPS allows mixing "slightly different" Cacheability and Coherency
1045 # Attribute bits. It is believed that the uncached access through
1046 # KSEG1 and the implementation specific "uncached accelerated" used
1047 # by pgprot_writcombine can be mixed, and the latter sometimes provides
1048 # significant advantages.
1050 select ARCH_HAS_SETUP_DMA_OPS
1051 select ARCH_HAS_DMA_WRITE_COMBINE
1052 select ARCH_HAS_DMA_PREP_COHERENT
1053 select ARCH_HAS_SYNC_DMA_FOR_CPU
1054 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1055 select ARCH_HAS_DMA_SET_UNCACHED
1056 select DMA_NONCOHERENT_MMAP
1057 select NEED_DMA_MAP_STATE
1059 config SYS_HAS_EARLY_PRINTK
1062 config SYS_SUPPORTS_HOTPLUG_CPU
1065 config MIPS_BONITO64
1074 config NO_IOPORT_MAP
1078 def_bool CPU_NO_LOAD_STORE_LR
1080 config GENERIC_ISA_DMA
1082 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
1085 config GENERIC_ISA_DMA_SUPPORT_BROKEN
1087 select GENERIC_ISA_DMA
1089 config HAVE_PLAT_DELAY
1092 config HAVE_PLAT_FW_INIT_CMDLINE
1095 config HAVE_PLAT_MEMCPY
1101 config SYS_SUPPORTS_RELOCATABLE
1104 Selected if the platform supports relocating the kernel.
1105 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1106 to allow access to command line and entropy sources.
1109 # Endianness selection. Sufficiently obscure so many users don't know what to
1110 # answer,so we try hard to limit the available choices. Also the use of a
1111 # choice statement should be more obvious to the user.
1114 prompt "Endianness selection"
1116 Some MIPS machines can be configured for either little or big endian
1117 byte order. These modes require different kernels and a different
1118 Linux distribution. In general there is one preferred byteorder for a
1119 particular system but some systems are just as commonly used in the
1120 one or the other endianness.
1122 config CPU_BIG_ENDIAN
1124 depends on SYS_SUPPORTS_BIG_ENDIAN
1126 config CPU_LITTLE_ENDIAN
1127 bool "Little endian"
1128 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1135 config SYS_SUPPORTS_APM_EMULATION
1138 config SYS_SUPPORTS_BIG_ENDIAN
1141 config SYS_SUPPORTS_LITTLE_ENDIAN
1144 config MIPS_HUGE_TLB_SUPPORT
1145 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
1153 config PCI_GT64XXX_PCI0
1156 config PCI_XTALK_BRIDGE
1159 config NO_EXCEPT_FILL
1165 config SWAP_IO_SPACE
1168 config SGI_HAS_INDYDOG
1180 config SGI_HAS_ZILOG
1183 config SGI_HAS_I8042
1186 config DEFAULT_SGI_PARTITION
1198 config MIPS_L1_CACHE_SHIFT_4
1201 config MIPS_L1_CACHE_SHIFT_5
1204 config MIPS_L1_CACHE_SHIFT_6
1207 config MIPS_L1_CACHE_SHIFT_7
1210 config MIPS_L1_CACHE_SHIFT
1212 default "7" if MIPS_L1_CACHE_SHIFT_7
1213 default "6" if MIPS_L1_CACHE_SHIFT_6
1214 default "5" if MIPS_L1_CACHE_SHIFT_5
1215 default "4" if MIPS_L1_CACHE_SHIFT_4
1218 config ARC_CMDLINE_ONLY
1222 bool "ARC console support"
1223 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1237 menu "CPU selection"
1243 config CPU_LOONGSON64
1244 bool "Loongson 64-bit CPU"
1245 depends on SYS_HAS_CPU_LOONGSON64
1246 select ARCH_HAS_PHYS_TO_DMA
1248 select CPU_HAS_PREFETCH
1249 select CPU_SUPPORTS_64BIT_KERNEL
1250 select CPU_SUPPORTS_HIGHMEM
1251 select CPU_SUPPORTS_HUGEPAGES
1252 select CPU_SUPPORTS_MSA
1253 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
1254 select CPU_MIPSR2_IRQ_VI
1255 select DMA_NONCOHERENT
1256 select WEAK_ORDERING
1257 select WEAK_REORDERING_BEYOND_LLSC
1258 select MIPS_ASID_BITS_VARIABLE
1259 select MIPS_PGD_C0_CONTEXT
1260 select MIPS_L1_CACHE_SHIFT_6
1261 select MIPS_FP_SUPPORT
1266 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1267 cores implements the MIPS64R2 instruction set with many extensions,
1268 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1269 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1270 Loongson-2E/2F is not covered here and will be removed in future.
1272 config LOONGSON3_ENHANCEMENT
1273 bool "New Loongson-3 CPU Enhancements"
1275 depends on CPU_LOONGSON64
1277 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1278 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1279 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1280 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1281 Fast TLB refill support, etc.
1283 This option enable those enhancements which are not probed at run
1284 time. If you want a generic kernel to run on all Loongson 3 machines,
1285 please say 'N' here. If you want a high-performance kernel to run on
1286 new Loongson-3 machines only, please say 'Y' here.
1288 config CPU_LOONGSON3_WORKAROUNDS
1289 bool "Loongson-3 LLSC Workarounds"
1291 depends on CPU_LOONGSON64
1293 Loongson-3 processors have the llsc issues which require workarounds.
1294 Without workarounds the system may hang unexpectedly.
1296 Say Y, unless you know what you are doing.
1298 config CPU_LOONGSON3_CPUCFG_EMULATION
1299 bool "Emulate the CPUCFG instruction on older Loongson cores"
1301 depends on CPU_LOONGSON64
1303 Loongson-3A R4 and newer have the CPUCFG instruction available for
1304 userland to query CPU capabilities, much like CPUID on x86. This
1305 option provides emulation of the instruction on older Loongson
1306 cores, back to Loongson-3A1000.
1308 If unsure, please say Y.
1310 config CPU_LOONGSON2E
1312 depends on SYS_HAS_CPU_LOONGSON2E
1313 select CPU_LOONGSON2EF
1315 The Loongson 2E processor implements the MIPS III instruction set
1316 with many extensions.
1318 It has an internal FPGA northbridge, which is compatible to
1321 config CPU_LOONGSON2F
1323 depends on SYS_HAS_CPU_LOONGSON2F
1324 select CPU_LOONGSON2EF
1326 The Loongson 2F processor implements the MIPS III instruction set
1327 with many extensions.
1329 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1330 have a similar programming interface with FPGA northbridge used in
1333 config CPU_LOONGSON1B
1335 depends on SYS_HAS_CPU_LOONGSON1B
1336 select CPU_LOONGSON32
1337 select LEDS_GPIO_REGISTER
1339 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1340 Release 1 instruction set and part of the MIPS32 Release 2
1343 config CPU_LOONGSON1C
1345 depends on SYS_HAS_CPU_LOONGSON1C
1346 select CPU_LOONGSON32
1347 select LEDS_GPIO_REGISTER
1349 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1350 Release 1 instruction set and part of the MIPS32 Release 2
1353 config CPU_MIPS32_R1
1354 bool "MIPS32 Release 1"
1355 depends on SYS_HAS_CPU_MIPS32_R1
1356 select CPU_HAS_PREFETCH
1357 select CPU_SUPPORTS_32BIT_KERNEL
1358 select CPU_SUPPORTS_HIGHMEM
1360 Choose this option to build a kernel for release 1 or later of the
1361 MIPS32 architecture. Most modern embedded systems with a 32-bit
1362 MIPS processor are based on a MIPS32 processor. If you know the
1363 specific type of processor in your system, choose those that one
1364 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1365 Release 2 of the MIPS32 architecture is available since several
1366 years so chances are you even have a MIPS32 Release 2 processor
1367 in which case you should choose CPU_MIPS32_R2 instead for better
1370 config CPU_MIPS32_R2
1371 bool "MIPS32 Release 2"
1372 depends on SYS_HAS_CPU_MIPS32_R2
1373 select CPU_HAS_PREFETCH
1374 select CPU_SUPPORTS_32BIT_KERNEL
1375 select CPU_SUPPORTS_HIGHMEM
1376 select CPU_SUPPORTS_MSA
1379 Choose this option to build a kernel for release 2 or later of the
1380 MIPS32 architecture. Most modern embedded systems with a 32-bit
1381 MIPS processor are based on a MIPS32 processor. If you know the
1382 specific type of processor in your system, choose those that one
1383 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1385 config CPU_MIPS32_R5
1386 bool "MIPS32 Release 5"
1387 depends on SYS_HAS_CPU_MIPS32_R5
1388 select CPU_HAS_PREFETCH
1389 select CPU_SUPPORTS_32BIT_KERNEL
1390 select CPU_SUPPORTS_HIGHMEM
1391 select CPU_SUPPORTS_MSA
1393 select MIPS_O32_FP64_SUPPORT
1395 Choose this option to build a kernel for release 5 or later of the
1396 MIPS32 architecture. New MIPS processors, starting with the Warrior
1397 family, are based on a MIPS32r5 processor. If you own an older
1398 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1400 config CPU_MIPS32_R6
1401 bool "MIPS32 Release 6"
1402 depends on SYS_HAS_CPU_MIPS32_R6
1403 select CPU_HAS_PREFETCH
1404 select CPU_NO_LOAD_STORE_LR
1405 select CPU_SUPPORTS_32BIT_KERNEL
1406 select CPU_SUPPORTS_HIGHMEM
1407 select CPU_SUPPORTS_MSA
1409 select MIPS_O32_FP64_SUPPORT
1411 Choose this option to build a kernel for release 6 or later of the
1412 MIPS32 architecture. New MIPS processors, starting with the Warrior
1413 family, are based on a MIPS32r6 processor. If you own an older
1414 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1416 config CPU_MIPS64_R1
1417 bool "MIPS64 Release 1"
1418 depends on SYS_HAS_CPU_MIPS64_R1
1419 select CPU_HAS_PREFETCH
1420 select CPU_SUPPORTS_32BIT_KERNEL
1421 select CPU_SUPPORTS_64BIT_KERNEL
1422 select CPU_SUPPORTS_HIGHMEM
1423 select CPU_SUPPORTS_HUGEPAGES
1425 Choose this option to build a kernel for release 1 or later of the
1426 MIPS64 architecture. Many modern embedded systems with a 64-bit
1427 MIPS processor are based on a MIPS64 processor. If you know the
1428 specific type of processor in your system, choose those that one
1429 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1430 Release 2 of the MIPS64 architecture is available since several
1431 years so chances are you even have a MIPS64 Release 2 processor
1432 in which case you should choose CPU_MIPS64_R2 instead for better
1435 config CPU_MIPS64_R2
1436 bool "MIPS64 Release 2"
1437 depends on SYS_HAS_CPU_MIPS64_R2
1438 select CPU_HAS_PREFETCH
1439 select CPU_SUPPORTS_32BIT_KERNEL
1440 select CPU_SUPPORTS_64BIT_KERNEL
1441 select CPU_SUPPORTS_HIGHMEM
1442 select CPU_SUPPORTS_HUGEPAGES
1443 select CPU_SUPPORTS_MSA
1446 Choose this option to build a kernel for release 2 or later of the
1447 MIPS64 architecture. Many modern embedded systems with a 64-bit
1448 MIPS processor are based on a MIPS64 processor. If you know the
1449 specific type of processor in your system, choose those that one
1450 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1452 config CPU_MIPS64_R5
1453 bool "MIPS64 Release 5"
1454 depends on SYS_HAS_CPU_MIPS64_R5
1455 select CPU_HAS_PREFETCH
1456 select CPU_SUPPORTS_32BIT_KERNEL
1457 select CPU_SUPPORTS_64BIT_KERNEL
1458 select CPU_SUPPORTS_HIGHMEM
1459 select CPU_SUPPORTS_HUGEPAGES
1460 select CPU_SUPPORTS_MSA
1461 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1464 Choose this option to build a kernel for release 5 or later of the
1465 MIPS64 architecture. This is a intermediate MIPS architecture
1466 release partly implementing release 6 features. Though there is no
1467 any hardware known to be based on this release.
1469 config CPU_MIPS64_R6
1470 bool "MIPS64 Release 6"
1471 depends on SYS_HAS_CPU_MIPS64_R6
1472 select CPU_HAS_PREFETCH
1473 select CPU_NO_LOAD_STORE_LR
1474 select CPU_SUPPORTS_32BIT_KERNEL
1475 select CPU_SUPPORTS_64BIT_KERNEL
1476 select CPU_SUPPORTS_HIGHMEM
1477 select CPU_SUPPORTS_HUGEPAGES
1478 select CPU_SUPPORTS_MSA
1479 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1482 Choose this option to build a kernel for release 6 or later of the
1483 MIPS64 architecture. New MIPS processors, starting with the Warrior
1484 family, are based on a MIPS64r6 processor. If you own an older
1485 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1488 bool "MIPS Warrior P5600"
1489 depends on SYS_HAS_CPU_P5600
1490 select CPU_HAS_PREFETCH
1491 select CPU_SUPPORTS_32BIT_KERNEL
1492 select CPU_SUPPORTS_HIGHMEM
1493 select CPU_SUPPORTS_MSA
1494 select CPU_SUPPORTS_CPUFREQ
1495 select CPU_MIPSR2_IRQ_VI
1496 select CPU_MIPSR2_IRQ_EI
1498 select MIPS_O32_FP64_SUPPORT
1500 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1501 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1502 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1503 level features like up to six P5600 calculation cores, CM2 with L2
1504 cache, IOCU/IOMMU (though might be unused depending on the system-
1505 specific IP core configuration), GIC, CPC, virtualisation module,
1510 depends on SYS_HAS_CPU_R3000
1513 select CPU_SUPPORTS_32BIT_KERNEL
1514 select CPU_SUPPORTS_HIGHMEM
1516 Please make sure to pick the right CPU type. Linux/MIPS is not
1517 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1518 *not* work on R4000 machines and vice versa. However, since most
1519 of the supported machines have an R4000 (or similar) CPU, R4x00
1520 might be a safe bet. If the resulting kernel does not work,
1521 try to recompile with R3000.
1525 depends on SYS_HAS_CPU_R4300
1526 select CPU_SUPPORTS_32BIT_KERNEL
1527 select CPU_SUPPORTS_64BIT_KERNEL
1529 MIPS Technologies R4300-series processors.
1533 depends on SYS_HAS_CPU_R4X00
1534 select CPU_SUPPORTS_32BIT_KERNEL
1535 select CPU_SUPPORTS_64BIT_KERNEL
1536 select CPU_SUPPORTS_HUGEPAGES
1538 MIPS Technologies R4000-series processors other than 4300, including
1539 the R4000, R4400, R4600, and 4700.
1543 depends on SYS_HAS_CPU_TX49XX
1544 select CPU_HAS_PREFETCH
1545 select CPU_SUPPORTS_32BIT_KERNEL
1546 select CPU_SUPPORTS_64BIT_KERNEL
1547 select CPU_SUPPORTS_HUGEPAGES
1551 depends on SYS_HAS_CPU_R5000
1552 select CPU_SUPPORTS_32BIT_KERNEL
1553 select CPU_SUPPORTS_64BIT_KERNEL
1554 select CPU_SUPPORTS_HUGEPAGES
1556 MIPS Technologies R5000-series processors other than the Nevada.
1560 depends on SYS_HAS_CPU_R5500
1561 select CPU_SUPPORTS_32BIT_KERNEL
1562 select CPU_SUPPORTS_64BIT_KERNEL
1563 select CPU_SUPPORTS_HUGEPAGES
1565 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1570 depends on SYS_HAS_CPU_NEVADA
1571 select CPU_SUPPORTS_32BIT_KERNEL
1572 select CPU_SUPPORTS_64BIT_KERNEL
1573 select CPU_SUPPORTS_HUGEPAGES
1575 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1579 depends on SYS_HAS_CPU_R10000
1580 select CPU_HAS_PREFETCH
1581 select CPU_SUPPORTS_32BIT_KERNEL
1582 select CPU_SUPPORTS_64BIT_KERNEL
1583 select CPU_SUPPORTS_HIGHMEM
1584 select CPU_SUPPORTS_HUGEPAGES
1586 MIPS Technologies R10000-series processors.
1590 depends on SYS_HAS_CPU_RM7000
1591 select CPU_HAS_PREFETCH
1592 select CPU_SUPPORTS_32BIT_KERNEL
1593 select CPU_SUPPORTS_64BIT_KERNEL
1594 select CPU_SUPPORTS_HIGHMEM
1595 select CPU_SUPPORTS_HUGEPAGES
1599 depends on SYS_HAS_CPU_SB1
1600 select CPU_SUPPORTS_32BIT_KERNEL
1601 select CPU_SUPPORTS_64BIT_KERNEL
1602 select CPU_SUPPORTS_HIGHMEM
1603 select CPU_SUPPORTS_HUGEPAGES
1604 select WEAK_ORDERING
1606 config CPU_CAVIUM_OCTEON
1607 bool "Cavium Octeon processor"
1608 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1609 select CPU_HAS_PREFETCH
1610 select CPU_SUPPORTS_64BIT_KERNEL
1611 select WEAK_ORDERING
1612 select CPU_SUPPORTS_HIGHMEM
1613 select CPU_SUPPORTS_HUGEPAGES
1614 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1615 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1616 select MIPS_L1_CACHE_SHIFT_7
1619 The Cavium Octeon processor is a highly integrated chip containing
1620 many ethernet hardware widgets for networking tasks. The processor
1621 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1622 Full details can be found at http://www.caviumnetworks.com.
1625 bool "Broadcom BMIPS"
1626 depends on SYS_HAS_CPU_BMIPS
1628 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1629 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1630 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1631 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1632 select CPU_SUPPORTS_32BIT_KERNEL
1633 select DMA_NONCOHERENT
1635 select SWAP_IO_SPACE
1636 select WEAK_ORDERING
1637 select CPU_SUPPORTS_HIGHMEM
1638 select CPU_HAS_PREFETCH
1639 select CPU_SUPPORTS_CPUFREQ
1640 select MIPS_EXTERNAL_TIMER
1641 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1643 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1647 config CPU_MIPS32_3_5_FEATURES
1648 bool "MIPS32 Release 3.5 Features"
1649 depends on SYS_HAS_CPU_MIPS32_R3_5
1650 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
1653 Choose this option to build a kernel for release 2 or later of the
1654 MIPS32 architecture including features from the 3.5 release such as
1655 support for Enhanced Virtual Addressing (EVA).
1657 config CPU_MIPS32_3_5_EVA
1658 bool "Enhanced Virtual Addressing (EVA)"
1659 depends on CPU_MIPS32_3_5_FEATURES
1663 Choose this option if you want to enable the Enhanced Virtual
1664 Addressing (EVA) on your MIPS32 core (such as proAptiv).
1665 One of its primary benefits is an increase in the maximum size
1666 of lowmem (up to 3GB). If unsure, say 'N' here.
1668 config CPU_MIPS32_R5_FEATURES
1669 bool "MIPS32 Release 5 Features"
1670 depends on SYS_HAS_CPU_MIPS32_R5
1671 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
1673 Choose this option to build a kernel for release 2 or later of the
1674 MIPS32 architecture including features from release 5 such as
1675 support for Extended Physical Addressing (XPA).
1677 config CPU_MIPS32_R5_XPA
1678 bool "Extended Physical Addressing (XPA)"
1679 depends on CPU_MIPS32_R5_FEATURES
1681 depends on !PAGE_SIZE_4KB
1682 depends on SYS_SUPPORTS_HIGHMEM
1685 select PHYS_ADDR_T_64BIT
1688 Choose this option if you want to enable the Extended Physical
1689 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1690 benefit is to increase physical addressing equal to or greater
1691 than 40 bits. Note that this has the side effect of turning on
1692 64-bit addressing which in turn makes the PTEs 64-bit in size.
1693 If unsure, say 'N' here.
1696 config CPU_NOP_WORKAROUNDS
1699 config CPU_JUMP_WORKAROUNDS
1702 config CPU_LOONGSON2F_WORKAROUNDS
1703 bool "Loongson 2F Workarounds"
1705 select CPU_NOP_WORKAROUNDS
1706 select CPU_JUMP_WORKAROUNDS
1708 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1709 require workarounds. Without workarounds the system may hang
1710 unexpectedly. For more information please refer to the gas
1711 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1713 Loongson 2F03 and later have fixed these issues and no workarounds
1714 are needed. The workarounds have no significant side effect on them
1715 but may decrease the performance of the system so this option should
1716 be disabled unless the kernel is intended to be run on 2F01 or 2F02
1719 If unsure, please say Y.
1720 endif # CPU_LOONGSON2F
1722 config SYS_SUPPORTS_ZBOOT
1724 select HAVE_KERNEL_GZIP
1725 select HAVE_KERNEL_BZIP2
1726 select HAVE_KERNEL_LZ4
1727 select HAVE_KERNEL_LZMA
1728 select HAVE_KERNEL_LZO
1729 select HAVE_KERNEL_XZ
1730 select HAVE_KERNEL_ZSTD
1732 config SYS_SUPPORTS_ZBOOT_UART16550
1734 select SYS_SUPPORTS_ZBOOT
1736 config SYS_SUPPORTS_ZBOOT_UART_PROM
1738 select SYS_SUPPORTS_ZBOOT
1740 config CPU_LOONGSON2EF
1742 select CPU_SUPPORTS_32BIT_KERNEL
1743 select CPU_SUPPORTS_64BIT_KERNEL
1744 select CPU_SUPPORTS_HIGHMEM
1745 select CPU_SUPPORTS_HUGEPAGES
1747 config CPU_LOONGSON32
1751 select CPU_HAS_PREFETCH
1752 select CPU_SUPPORTS_32BIT_KERNEL
1753 select CPU_SUPPORTS_HIGHMEM
1754 select CPU_SUPPORTS_CPUFREQ
1756 config CPU_BMIPS32_3300
1757 select SMP_UP if SMP
1760 config CPU_BMIPS4350
1762 select SYS_SUPPORTS_SMP
1763 select SYS_SUPPORTS_HOTPLUG_CPU
1765 config CPU_BMIPS4380
1767 select MIPS_L1_CACHE_SHIFT_6
1768 select SYS_SUPPORTS_SMP
1769 select SYS_SUPPORTS_HOTPLUG_CPU
1772 config CPU_BMIPS5000
1774 select MIPS_CPU_SCACHE
1775 select MIPS_L1_CACHE_SHIFT_7
1776 select SYS_SUPPORTS_SMP
1777 select SYS_SUPPORTS_HOTPLUG_CPU
1780 config SYS_HAS_CPU_LOONGSON64
1782 select CPU_SUPPORTS_CPUFREQ
1785 config SYS_HAS_CPU_LOONGSON2E
1788 config SYS_HAS_CPU_LOONGSON2F
1790 select CPU_SUPPORTS_CPUFREQ
1791 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1793 config SYS_HAS_CPU_LOONGSON1B
1796 config SYS_HAS_CPU_LOONGSON1C
1799 config SYS_HAS_CPU_MIPS32_R1
1802 config SYS_HAS_CPU_MIPS32_R2
1805 config SYS_HAS_CPU_MIPS32_R3_5
1808 config SYS_HAS_CPU_MIPS32_R5
1811 config SYS_HAS_CPU_MIPS32_R6
1814 config SYS_HAS_CPU_MIPS64_R1
1817 config SYS_HAS_CPU_MIPS64_R2
1820 config SYS_HAS_CPU_MIPS64_R5
1823 config SYS_HAS_CPU_MIPS64_R6
1826 config SYS_HAS_CPU_P5600
1829 config SYS_HAS_CPU_R3000
1832 config SYS_HAS_CPU_R4300
1835 config SYS_HAS_CPU_R4X00
1838 config SYS_HAS_CPU_TX49XX
1841 config SYS_HAS_CPU_R5000
1844 config SYS_HAS_CPU_R5500
1847 config SYS_HAS_CPU_NEVADA
1850 config SYS_HAS_CPU_R10000
1853 config SYS_HAS_CPU_RM7000
1856 config SYS_HAS_CPU_SB1
1859 config SYS_HAS_CPU_CAVIUM_OCTEON
1862 config SYS_HAS_CPU_BMIPS
1865 config SYS_HAS_CPU_BMIPS32_3300
1867 select SYS_HAS_CPU_BMIPS
1869 config SYS_HAS_CPU_BMIPS4350
1871 select SYS_HAS_CPU_BMIPS
1873 config SYS_HAS_CPU_BMIPS4380
1875 select SYS_HAS_CPU_BMIPS
1877 config SYS_HAS_CPU_BMIPS5000
1879 select SYS_HAS_CPU_BMIPS
1882 # CPU may reorder R->R, R->W, W->R, W->W
1883 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1885 config WEAK_ORDERING
1889 # CPU may reorder reads and writes beyond LL/SC
1890 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1892 config WEAK_REORDERING_BEYOND_LLSC
1897 # These two indicate any level of the MIPS32 and MIPS64 architecture
1901 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1902 CPU_MIPS32_R6 || CPU_P5600
1906 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1907 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1910 # These indicate the revision of the architecture
1914 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1918 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1920 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1925 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1927 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1932 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1934 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1935 select HAVE_ARCH_BITREVERSE
1936 select MIPS_ASID_BITS_VARIABLE
1937 select MIPS_CRC_SUPPORT
1940 config TARGET_ISA_REV
1942 default 1 if CPU_MIPSR1
1943 default 2 if CPU_MIPSR2
1944 default 5 if CPU_MIPSR5
1945 default 6 if CPU_MIPSR6
1948 Reflects the ISA revision being targeted by the kernel build. This
1949 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1957 config SYS_SUPPORTS_32BIT_KERNEL
1959 config SYS_SUPPORTS_64BIT_KERNEL
1961 config CPU_SUPPORTS_32BIT_KERNEL
1963 config CPU_SUPPORTS_64BIT_KERNEL
1965 config CPU_SUPPORTS_CPUFREQ
1967 config CPU_SUPPORTS_ADDRWINCFG
1969 config CPU_SUPPORTS_HUGEPAGES
1971 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
1972 config MIPS_PGD_C0_CONTEXT
1975 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1978 # Set to y for ptrace access to watch registers.
1980 config HARDWARE_WATCHPOINTS
1982 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1987 prompt "Kernel code model"
1989 You should only select this option if you have a workload that
1990 actually benefits from 64-bit processing or if your machine has
1991 large memory. You will only be presented a single option in this
1992 menu if your system does not support both 32-bit and 64-bit kernels.
1995 bool "32-bit kernel"
1996 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1999 Select this option if you want to build a 32-bit kernel.
2002 bool "64-bit kernel"
2003 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
2005 Select this option if you want to build a 64-bit kernel.
2009 config MIPS_VA_BITS_48
2010 bool "48 bits virtual memory"
2013 Support a maximum at least 48 bits of application virtual
2014 memory. Default is 40 bits or less, depending on the CPU.
2015 For page sizes 16k and above, this option results in a small
2016 memory overhead for page tables. For 4k page size, a fourth
2017 level of page tables is added which imposes both a memory
2018 overhead as well as slower TLB fault handling.
2022 config ZBOOT_LOAD_ADDRESS
2023 hex "Compressed kernel load address"
2024 default 0xffffffff80400000 if BCM47XX
2026 depends on SYS_SUPPORTS_ZBOOT
2028 The address to load compressed kernel, aka vmlinuz.
2030 This is only used if non-zero.
2033 prompt "Kernel page size"
2034 default PAGE_SIZE_4KB
2036 config PAGE_SIZE_4KB
2038 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
2040 This option select the standard 4kB Linux page size. On some
2041 R3000-family processors this is the only available page size. Using
2042 4kB page size will minimize memory consumption and is therefore
2043 recommended for low memory systems.
2045 config PAGE_SIZE_8KB
2047 depends on CPU_CAVIUM_OCTEON
2048 depends on !MIPS_VA_BITS_48
2050 Using 8kB page size will result in higher performance kernel at
2051 the price of higher memory consumption. This option is available
2052 only on cnMIPS processors. Note that you will need a suitable Linux
2053 distribution to support this.
2055 config PAGE_SIZE_16KB
2057 depends on !CPU_R3000
2059 Using 16kB page size will result in higher performance kernel at
2060 the price of higher memory consumption. This option is available on
2061 all non-R3000 family processors. Note that you will need a suitable
2062 Linux distribution to support this.
2064 config PAGE_SIZE_32KB
2066 depends on CPU_CAVIUM_OCTEON
2067 depends on !MIPS_VA_BITS_48
2069 Using 32kB page size will result in higher performance kernel at
2070 the price of higher memory consumption. This option is available
2071 only on cnMIPS cores. Note that you will need a suitable Linux
2072 distribution to support this.
2074 config PAGE_SIZE_64KB
2076 depends on !CPU_R3000
2078 Using 64kB page size will result in higher performance kernel at
2079 the price of higher memory consumption. This option is available on
2080 all non-R3000 family processor. Not that at the time of this
2081 writing this option is still high experimental.
2085 config ARCH_FORCE_MAX_ORDER
2086 int "Maximum zone order"
2087 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2088 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2089 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2092 The kernel memory allocator divides physically contiguous memory
2093 blocks into "zones", where each zone is a power of two number of
2094 pages. This option selects the largest power of two that the kernel
2095 keeps in the memory allocator. If you need to allocate very large
2096 blocks of physically contiguous memory, then you may need to
2097 increase this value.
2099 The page size is not necessarily 4KB. Keep this in mind
2100 when choosing a value for this option.
2105 config IP22_CPU_SCACHE
2110 # Support for a MIPS32 / MIPS64 style S-caches
2112 config MIPS_CPU_SCACHE
2116 config R5000_CPU_SCACHE
2120 config RM7000_CPU_SCACHE
2124 config SIBYTE_DMA_PAGEOPS
2125 bool "Use DMA to clear/copy pages"
2128 Instead of using the CPU to zero and copy pages, use a Data Mover
2129 channel. These DMA channels are otherwise unused by the standard
2130 SiByte Linux port. Seems to give a small performance benefit.
2132 config CPU_HAS_PREFETCH
2135 config CPU_GENERIC_DUMP_TLB
2137 default y if !CPU_R3000
2139 config MIPS_FP_SUPPORT
2140 bool "Floating Point support" if EXPERT
2143 Select y to include support for floating point in the kernel
2144 including initialization of FPU hardware, FP context save & restore
2145 and emulation of an FPU where necessary. Without this support any
2146 userland program attempting to use floating point instructions will
2149 If you know that your userland will not attempt to use floating point
2150 instructions then you can say n here to shrink the kernel a little.
2154 config CPU_R2300_FPU
2156 depends on MIPS_FP_SUPPORT
2157 default y if CPU_R3000
2164 depends on MIPS_FP_SUPPORT
2165 default y if !CPU_R2300_FPU
2167 config CPU_R4K_CACHE_TLB
2169 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2172 bool "MIPS MT SMP support (1 TC on each available VPE)"
2174 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
2175 select CPU_MIPSR2_IRQ_VI
2176 select CPU_MIPSR2_IRQ_EI
2181 select SYS_SUPPORTS_SMP
2182 select SYS_SUPPORTS_SCHED_SMT
2183 select MIPS_PERF_SHARED_TC_COUNTERS
2185 This is a kernel model which is known as SMVP. This is supported
2186 on cores with the MT ASE and uses the available VPEs to implement
2187 virtual processors which supports SMP. This is equivalent to the
2188 Intel Hyperthreading feature. For further information go to
2189 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2195 bool "SMT (multithreading) scheduler support"
2196 depends on SYS_SUPPORTS_SCHED_SMT
2199 SMT scheduler support improves the CPU scheduler's decision making
2200 when dealing with MIPS MT enabled cores at a cost of slightly
2201 increased overhead in some places. If unsure say N here.
2203 config SYS_SUPPORTS_SCHED_SMT
2206 config SYS_SUPPORTS_MULTITHREADING
2209 config MIPS_MT_FPAFF
2210 bool "Dynamic FPU affinity for FP-intensive threads"
2212 depends on MIPS_MT_SMP
2214 config MIPSR2_TO_R6_EMULATOR
2215 bool "MIPS R2-to-R6 emulator"
2216 depends on CPU_MIPSR6
2217 depends on MIPS_FP_SUPPORT
2220 Choose this option if you want to run non-R6 MIPS userland code.
2221 Even if you say 'Y' here, the emulator will still be disabled by
2222 default. You can enable it using the 'mipsr2emu' kernel option.
2223 The only reason this is a build-time option is to save ~14K from the
2226 config SYS_SUPPORTS_VPE_LOADER
2228 depends on SYS_SUPPORTS_MULTITHREADING
2230 Indicates that the platform supports the VPE loader, and provides
2233 config MIPS_VPE_LOADER
2234 bool "VPE loader support."
2235 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
2236 select CPU_MIPSR2_IRQ_VI
2237 select CPU_MIPSR2_IRQ_EI
2240 Includes a loader for loading an elf relocatable object
2241 onto another VPE and running it.
2243 config MIPS_VPE_LOADER_MT
2246 depends on MIPS_VPE_LOADER
2248 config MIPS_VPE_LOADER_TOM
2249 bool "Load VPE program into memory hidden from linux"
2250 depends on MIPS_VPE_LOADER
2253 The loader can use memory that is present but has been hidden from
2254 Linux using the kernel command line option "mem=xxMB". It's up to
2255 you to ensure the amount you put in the option and the space your
2256 program requires is less or equal to the amount physically present.
2258 config MIPS_VPE_APSP_API
2259 bool "Enable support for AP/SP API (RTLX)"
2260 depends on MIPS_VPE_LOADER
2262 config MIPS_VPE_APSP_API_MT
2265 depends on MIPS_VPE_APSP_API
2268 bool "MIPS Coherent Processing System support"
2269 depends on SYS_SUPPORTS_MIPS_CPS
2271 select MIPS_CPS_PM if HOTPLUG_CPU
2273 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
2274 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2275 select SYS_SUPPORTS_HOTPLUG_CPU
2276 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2277 select SYS_SUPPORTS_SMP
2278 select WEAK_ORDERING
2279 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
2281 Select this if you wish to run an SMP kernel across multiple cores
2282 within a MIPS Coherent Processing System. When this option is
2283 enabled the kernel will probe for other cores and boot them with
2284 no external assistance. It is safe to enable this when hardware
2285 support is unavailable.
2298 config SB1_PASS_2_WORKAROUNDS
2300 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
2303 config SB1_PASS_2_1_WORKAROUNDS
2305 depends on CPU_SB1 && CPU_SB1_PASS_2
2309 prompt "SmartMIPS or microMIPS ASE support"
2311 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2314 Select this if you want neither microMIPS nor SmartMIPS support
2316 config CPU_HAS_SMARTMIPS
2317 depends on SYS_SUPPORTS_SMARTMIPS
2320 SmartMIPS is a extension of the MIPS32 architecture aimed at
2321 increased security at both hardware and software level for
2322 smartcards. Enabling this option will allow proper use of the
2323 SmartMIPS instructions by Linux applications. However a kernel with
2324 this option will not work on a MIPS core without SmartMIPS core. If
2325 you don't know you probably don't have SmartMIPS and should say N
2328 config CPU_MICROMIPS
2329 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
2332 When this option is enabled the kernel will be built using the
2338 bool "Support for the MIPS SIMD Architecture"
2339 depends on CPU_SUPPORTS_MSA
2340 depends on MIPS_FP_SUPPORT
2341 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2343 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2344 and a set of SIMD instructions to operate on them. When this option
2345 is enabled the kernel will support allocating & switching MSA
2346 vector register contexts. If you know that your kernel will only be
2347 running on CPUs which do not support MSA or that your userland will
2348 not be making use of it then you may wish to say N here to reduce
2349 the size & complexity of your kernel.
2360 depends on !CPU_DIEI_BROKEN
2363 config CPU_DIEI_BROKEN
2369 config CPU_NO_LOAD_STORE_LR
2372 CPU lacks support for unaligned load and store instructions:
2373 LWL, LWR, SWL, SWR (Load/store word left/right).
2374 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2378 # Vectored interrupt mode is an R2 feature
2380 config CPU_MIPSR2_IRQ_VI
2384 # Extended interrupt mode is an R2 feature
2386 config CPU_MIPSR2_IRQ_EI
2391 depends on !CPU_R3000
2398 # Work around the "daddi" and "daddiu" CPU errata:
2400 # - The `daddi' instruction fails to trap on overflow.
2401 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2404 # - The `daddiu' instruction can produce an incorrect result.
2405 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2407 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2409 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2410 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2411 config CPU_DADDI_WORKAROUNDS
2414 # Work around certain R4000 CPU errata (as implemented by GCC):
2416 # - A double-word or a variable shift may give an incorrect result
2417 # if executed immediately after starting an integer division:
2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2420 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2423 # - A double-word or a variable shift may give an incorrect result
2424 # if executed while an integer multiplication is in progress:
2425 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2428 # - An integer division may give an incorrect result if started in
2429 # a delay slot of a taken branch or a jump:
2430 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2432 config CPU_R4000_WORKAROUNDS
2434 select CPU_R4400_WORKAROUNDS
2436 # Work around certain R4400 CPU errata (as implemented by GCC):
2438 # - A double-word or a variable shift may give an incorrect result
2439 # if executed immediately after starting an integer division:
2440 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2441 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2442 config CPU_R4400_WORKAROUNDS
2445 config CPU_R4X00_BUGS64
2447 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2449 config MIPS_ASID_SHIFT
2451 default 6 if CPU_R3000
2454 config MIPS_ASID_BITS
2456 default 0 if MIPS_ASID_BITS_VARIABLE
2457 default 6 if CPU_R3000
2460 config MIPS_ASID_BITS_VARIABLE
2463 config MIPS_CRC_SUPPORT
2466 # R4600 erratum. Due to the lack of errata information the exact
2467 # technical details aren't known. I've experimentally found that disabling
2468 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2470 config WAR_R4600_V1_INDEX_ICACHEOP
2473 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2475 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2476 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2477 # executed if there is no other dcache activity. If the dcache is
2478 # accessed for another instruction immediately preceding when these
2479 # cache instructions are executing, it is possible that the dcache
2480 # tag match outputs used by these cache instructions will be
2481 # incorrect. These cache instructions should be preceded by at least
2482 # four instructions that are not any kind of load or store
2485 # This is not allowed: lw
2489 # cache Hit_Writeback_Invalidate_D
2491 # This is allowed: lw
2496 # cache Hit_Writeback_Invalidate_D
2497 config WAR_R4600_V1_HIT_CACHEOP
2500 # Writeback and invalidate the primary cache dcache before DMA.
2502 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2503 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2504 # operate correctly if the internal data cache refill buffer is empty. These
2505 # CACHE instructions should be separated from any potential data cache miss
2506 # by a load instruction to an uncached address to empty the response buffer."
2507 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2509 config WAR_R4600_V2_HIT_CACHEOP
2512 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2513 # the line which this instruction itself exists, the following
2514 # operation is not guaranteed."
2516 # Workaround: do two phase flushing for Index_Invalidate_I
2517 config WAR_TX49XX_ICACHE_INDEX_INV
2520 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2521 # opposes it being called that) where invalid instructions in the same
2522 # I-cache line worth of instructions being fetched may case spurious
2524 config WAR_ICACHE_REFILLS
2527 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2528 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2529 config WAR_R10000_LLSC
2532 # 34K core erratum: "Problems Executing the TLBR Instruction"
2533 config WAR_MIPS34K_MISSED_ITLB
2537 # - Highmem only makes sense for the 32-bit kernel.
2538 # - The current highmem code will only work properly on physically indexed
2539 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2540 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2541 # moment we protect the user and offer the highmem option only on machines
2542 # where it's known to be safe. This will not offer highmem on a few systems
2543 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2544 # indexed CPUs but we're playing safe.
2545 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2546 # know they might have memory configurations that could make use of highmem
2550 bool "High Memory Support"
2551 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2554 config CPU_SUPPORTS_HIGHMEM
2557 config SYS_SUPPORTS_HIGHMEM
2560 config SYS_SUPPORTS_SMARTMIPS
2563 config SYS_SUPPORTS_MICROMIPS
2566 config SYS_SUPPORTS_MIPS16
2569 This option must be set if a kernel might be executed on a MIPS16-
2570 enabled CPU even if MIPS16 is not actually being used. In other
2571 words, it makes the kernel MIPS16-tolerant.
2573 config CPU_SUPPORTS_MSA
2576 config ARCH_FLATMEM_ENABLE
2578 depends on !NUMA && !CPU_LOONGSON2EF
2580 config ARCH_SPARSEMEM_ENABLE
2585 depends on SYS_SUPPORTS_NUMA
2587 select HAVE_SETUP_PER_CPU_AREA
2588 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2590 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2591 Access). This option improves performance on systems with more
2592 than two nodes; on two node systems it is generally better to
2593 leave it disabled; on single node systems leave this option
2596 config SYS_SUPPORTS_NUMA
2599 config HAVE_ARCH_NODEDATA_EXTENSION
2603 bool "Relocatable kernel"
2604 depends on SYS_SUPPORTS_RELOCATABLE
2605 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2606 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2607 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2608 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2611 This builds a kernel image that retains relocation information
2612 so it can be loaded someplace besides the default 1MB.
2613 The relocations make the kernel binary about 15% larger,
2614 but are discarded at runtime
2616 config RELOCATION_TABLE_SIZE
2617 hex "Relocation table size"
2618 depends on RELOCATABLE
2619 range 0x0 0x01000000
2620 default "0x00200000" if CPU_LOONGSON64
2621 default "0x00100000"
2623 A table of relocation data will be appended to the kernel binary
2624 and parsed at boot to fix up the relocated kernel.
2626 This option allows the amount of space reserved for the table to be
2627 adjusted, although the default of 1Mb should be ok in most cases.
2629 The build will fail and a valid size suggested if this is too small.
2631 If unsure, leave at the default value.
2633 config RANDOMIZE_BASE
2634 bool "Randomize the address of the kernel image"
2635 depends on RELOCATABLE
2637 Randomizes the physical and virtual address at which the
2638 kernel image is loaded, as a security feature that
2639 deters exploit attempts relying on knowledge of the location
2640 of kernel internals.
2642 Entropy is generated using any coprocessor 0 registers available.
2644 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2648 config RANDOMIZE_BASE_MAX_OFFSET
2649 hex "Maximum kASLR offset" if EXPERT
2650 depends on RANDOMIZE_BASE
2651 range 0x0 0x40000000 if EVA || 64BIT
2652 range 0x0 0x08000000
2653 default "0x01000000"
2655 When kASLR is active, this provides the maximum offset that will
2656 be applied to the kernel image. It should be set according to the
2657 amount of physical RAM available in the target system minus
2658 PHYSICAL_START and must be a power of 2.
2660 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2661 EVA or 64-bit. The default is 16Mb.
2668 config HW_PERF_EVENTS
2669 bool "Enable hardware performance counter support for perf events"
2670 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2673 Enable hardware performance counter support for perf events. If
2674 disabled, perf events will use software events only.
2677 bool "Enable DMI scanning"
2678 depends on MACH_LOONGSON64
2679 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2682 Enabled scanning of DMI to identify machine quirks. Say Y
2683 here unless you have verified that your setup is not
2684 affected by entries in the DMI blacklist. Required by PNP
2688 bool "Multi-Processing support"
2689 depends on SYS_SUPPORTS_SMP
2691 This enables support for systems with more than one CPU. If you have
2692 a system with only one CPU, say N. If you have a system with more
2693 than one CPU, say Y.
2695 If you say N here, the kernel will run on uni- and multiprocessor
2696 machines, but will use only one CPU of a multiprocessor machine. If
2697 you say Y here, the kernel will run on many, but not all,
2698 uniprocessor machines. On a uniprocessor machine, the kernel
2699 will run faster if you say N here.
2701 People using multiprocessor machines who say Y here should also say
2702 Y to "Enhanced Real Time Clock Support", below.
2704 See also the SMP-HOWTO available at
2705 <https://www.tldp.org/docs.html#howto>.
2707 If you don't know what to do here, say N.
2710 bool "Support for hot-pluggable CPUs"
2711 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2713 Say Y here to allow turning CPUs off and on. CPUs can be
2714 controlled through /sys/devices/system/cpu.
2715 (Note: power management support will enable this option
2716 automatically on SMP systems. )
2717 Say N if you want to disable CPU hotplug.
2722 config SYS_SUPPORTS_MIPS_CPS
2725 config SYS_SUPPORTS_SMP
2728 config NR_CPUS_DEFAULT_4
2731 config NR_CPUS_DEFAULT_8
2734 config NR_CPUS_DEFAULT_16
2737 config NR_CPUS_DEFAULT_32
2740 config NR_CPUS_DEFAULT_64
2744 int "Maximum number of CPUs (2-256)"
2747 default "4" if NR_CPUS_DEFAULT_4
2748 default "8" if NR_CPUS_DEFAULT_8
2749 default "16" if NR_CPUS_DEFAULT_16
2750 default "32" if NR_CPUS_DEFAULT_32
2751 default "64" if NR_CPUS_DEFAULT_64
2753 This allows you to specify the maximum number of CPUs which this
2754 kernel will support. The maximum supported value is 32 for 32-bit
2755 kernel and 64 for 64-bit kernels; the minimum value which makes
2756 sense is 1 for Qemu (useful only for kernel debugging purposes)
2757 and 2 for all others.
2759 This is purely to save memory - each supported CPU adds
2760 approximately eight kilobytes to the kernel image. For best
2761 performance should round up your number of processors to the next
2764 config MIPS_PERF_SHARED_TC_COUNTERS
2767 config MIPS_NR_CPU_NR_MAP_1024
2770 config MIPS_NR_CPU_NR_MAP
2773 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2774 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2777 # Timer Interrupt Frequency Configuration
2781 prompt "Timer frequency"
2784 Allows the configuration of the timer frequency.
2787 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2790 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2793 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2796 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2799 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2802 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2805 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2808 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2812 config SYS_SUPPORTS_24HZ
2815 config SYS_SUPPORTS_48HZ
2818 config SYS_SUPPORTS_100HZ
2821 config SYS_SUPPORTS_128HZ
2824 config SYS_SUPPORTS_250HZ
2827 config SYS_SUPPORTS_256HZ
2830 config SYS_SUPPORTS_1000HZ
2833 config SYS_SUPPORTS_1024HZ
2836 config SYS_SUPPORTS_ARBIT_HZ
2838 default y if !SYS_SUPPORTS_24HZ && \
2839 !SYS_SUPPORTS_48HZ && \
2840 !SYS_SUPPORTS_100HZ && \
2841 !SYS_SUPPORTS_128HZ && \
2842 !SYS_SUPPORTS_250HZ && \
2843 !SYS_SUPPORTS_256HZ && \
2844 !SYS_SUPPORTS_1000HZ && \
2845 !SYS_SUPPORTS_1024HZ
2851 default 100 if HZ_100
2852 default 128 if HZ_128
2853 default 250 if HZ_250
2854 default 256 if HZ_256
2855 default 1000 if HZ_1000
2856 default 1024 if HZ_1024
2859 def_bool HIGH_RES_TIMERS
2861 config ARCH_SUPPORTS_KEXEC
2864 config ARCH_SUPPORTS_CRASH_DUMP
2867 config PHYSICAL_START
2868 hex "Physical address where the kernel is loaded"
2869 default "0xffffffff84000000"
2870 depends on CRASH_DUMP
2872 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2873 If you plan to use kernel for capturing the crash dump change
2874 this value to start of the reserved region (the "X" value as
2875 specified in the "crashkernel=YM@XM" command line boot parameter
2876 passed to the panic-ed kernel).
2878 config MIPS_O32_FP64_SUPPORT
2879 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2880 depends on 32BIT || MIPS32_O32
2882 When this is enabled, the kernel will support use of 64-bit floating
2883 point registers with binaries using the O32 ABI along with the
2884 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2885 32-bit MIPS systems this support is at the cost of increasing the
2886 size and complexity of the compiled FPU emulator. Thus if you are
2887 running a MIPS32 system and know that none of your userland binaries
2888 will require 64-bit floating point, you may wish to reduce the size
2889 of your kernel & potentially improve FP emulation performance by
2892 Although binutils currently supports use of this flag the details
2893 concerning its effect upon the O32 ABI in userland are still being
2894 worked on. In order to avoid userland becoming dependent upon current
2895 behaviour before the details have been finalised, this option should
2896 be considered experimental and only enabled by those working upon
2904 select OF_EARLY_FLATTREE
2914 prompt "Kernel appended dtb support" if USE_OF
2915 default MIPS_NO_APPENDED_DTB
2917 config MIPS_NO_APPENDED_DTB
2920 Do not enable appended dtb support.
2922 config MIPS_ELF_APPENDED_DTB
2925 With this option, the boot code will look for a device tree binary
2926 DTB) included in the vmlinux ELF section .appended_dtb. By default
2927 it is empty and the DTB can be appended using binutils command
2930 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2932 This is meant as a backward compatibility convenience for those
2933 systems with a bootloader that can't be upgraded to accommodate
2934 the documented boot protocol using a device tree.
2936 config MIPS_RAW_APPENDED_DTB
2937 bool "vmlinux.bin or vmlinuz.bin"
2939 With this option, the boot code will look for a device tree binary
2940 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
2941 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
2943 This is meant as a backward compatibility convenience for those
2944 systems with a bootloader that can't be upgraded to accommodate
2945 the documented boot protocol using a device tree.
2947 Beware that there is very little in terms of protection against
2948 this option being confused by leftover garbage in memory that might
2949 look like a DTB header after a reboot if no actual DTB is appended
2950 to vmlinux.bin. Do not leave this option active in a production kernel
2951 if you don't intend to always append a DTB.
2955 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2956 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2957 !MACH_LOONGSON64 && !MIPS_MALTA && \
2959 default MIPS_CMDLINE_FROM_BOOTLOADER
2961 config MIPS_CMDLINE_FROM_DTB
2963 bool "Dtb kernel arguments if available"
2965 config MIPS_CMDLINE_DTB_EXTEND
2967 bool "Extend dtb kernel arguments with bootloader arguments"
2969 config MIPS_CMDLINE_FROM_BOOTLOADER
2970 bool "Bootloader kernel arguments if available"
2972 config MIPS_CMDLINE_BUILTIN_EXTEND
2973 depends on CMDLINE_BOOL
2974 bool "Extend builtin kernel arguments with bootloader arguments"
2979 config LOCKDEP_SUPPORT
2983 config STACKTRACE_SUPPORT
2987 config PGTABLE_LEVELS
2989 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2990 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
2993 config MIPS_AUTO_PFN_OFFSET
2996 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2998 config PCI_DRIVERS_GENERIC
2999 select PCI_DOMAINS_GENERIC if PCI
3002 config PCI_DRIVERS_LEGACY
3003 def_bool !PCI_DRIVERS_GENERIC
3004 select NO_GENERIC_PCI_IOPORT_MAP
3005 select PCI_DOMAINS if PCI
3008 # ISA support is now enabled via select. Too many systems still have the one
3009 # or other ISA chip on the board that users don't know about so don't expect
3010 # users to choose the right thing ...
3016 bool "TURBOchannel support"
3017 depends on MACH_DECSTATION
3019 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
3020 processors. TURBOchannel programming specifications are available
3022 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
3024 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3025 Linux driver support status is documented at:
3026 <http://www.linux-mips.org/wiki/DECstation>
3032 config ARCH_MMAP_RND_BITS_MIN
3036 config ARCH_MMAP_RND_BITS_MAX
3040 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3043 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3050 select MIPS_EXTERNAL_TIMER
3056 config MIPS32_COMPAT
3063 bool "Kernel support for o32 binaries"
3065 select ARCH_WANT_OLD_COMPAT_IPC
3067 select MIPS32_COMPAT
3069 Select this option if you want to run o32 binaries. These are pure
3070 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3071 existing binaries are in this format.
3076 bool "Kernel support for n32 binaries"
3078 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3080 select MIPS32_COMPAT
3082 Select this option if you want to run n32 binaries. These are
3083 64-bit binaries using 32-bit quantities for addressing and certain
3084 data that would normally be 64-bit. They are used in special
3089 config CC_HAS_MNO_BRANCH_LIKELY
3091 depends on $(cc-option,-mno-branch-likely)
3093 # https://github.com/llvm/llvm-project/issues/61045
3094 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3095 def_bool y if CC_IS_CLANG
3097 menu "Power management options"
3099 config ARCH_HIBERNATION_POSSIBLE
3101 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3103 config ARCH_SUSPEND_POSSIBLE
3105 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3107 source "kernel/power/Kconfig"
3111 config MIPS_EXTERNAL_TIMER
3114 menu "CPU Power Management"
3116 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3117 source "drivers/cpufreq/Kconfig"
3118 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3120 source "drivers/cpuidle/Kconfig"
3124 source "arch/mips/kvm/Kconfig"
3126 source "arch/mips/vdso/Kconfig"