1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for indirect PCI bridges.
5 * Copyright (C) 1998 Gabriel Paubert.
8 #include <linux/kernel.h>
10 #include <linux/delay.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
15 #include <asm/pci-bridge.h>
18 indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
21 struct pci_controller *hose = pci_bus_to_host(bus);
22 volatile void __iomem *cfg_data;
26 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
27 if (bus->number != hose->first_busno)
28 return PCIBIOS_DEVICE_NOT_FOUND;
30 return PCIBIOS_DEVICE_NOT_FOUND;
33 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
34 if (bus->number != hose->first_busno)
37 bus_no = (bus->number == hose->first_busno) ?
38 hose->self_busno : bus->number;
40 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
41 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
43 reg = offset & 0xfc; /* Only 3 bits for function */
45 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
46 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
47 (devfn << 8) | reg | cfg_type));
49 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
50 (devfn << 8) | reg | cfg_type));
53 * Note: the caller has already checked that offset is
54 * suitably aligned and that len is 1, 2 or 4.
56 cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
59 *val = in_8(cfg_data);
62 *val = in_le16(cfg_data);
65 *val = in_le32(cfg_data);
68 return PCIBIOS_SUCCESSFUL;
72 indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
75 struct pci_controller *hose = pci_bus_to_host(bus);
76 volatile void __iomem *cfg_data;
80 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
81 if (bus->number != hose->first_busno)
82 return PCIBIOS_DEVICE_NOT_FOUND;
84 return PCIBIOS_DEVICE_NOT_FOUND;
87 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
88 if (bus->number != hose->first_busno)
91 bus_no = (bus->number == hose->first_busno) ?
92 hose->self_busno : bus->number;
94 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
95 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
99 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
100 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
101 (devfn << 8) | reg | cfg_type));
103 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
104 (devfn << 8) | reg | cfg_type));
106 /* suppress setting of PCI_PRIMARY_BUS */
107 if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
108 if ((offset == PCI_PRIMARY_BUS) &&
109 (bus->number == hose->first_busno))
112 /* Workaround for PCI_28 Errata in 440EPx/GRx */
113 if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
114 offset == PCI_CACHE_LINE_SIZE) {
119 * Note: the caller has already checked that offset is
120 * suitably aligned and that len is 1, 2 or 4.
122 cfg_data = hose->cfg_data + (offset & 3);
125 out_8(cfg_data, val);
128 out_le16(cfg_data, val);
131 out_le32(cfg_data, val);
135 return PCIBIOS_SUCCESSFUL;
138 static struct pci_ops indirect_pci_ops = {
139 .read = indirect_read_config,
140 .write = indirect_write_config,
144 setup_indirect_pci(struct pci_controller *hose,
145 resource_size_t cfg_addr,
146 resource_size_t cfg_data, u32 flags)
148 resource_size_t base = cfg_addr & PAGE_MASK;
151 mbase = ioremap(base, PAGE_SIZE);
152 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
153 if ((cfg_data & PAGE_MASK) != base)
154 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
155 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
156 hose->ops = &indirect_pci_ops;
157 hose->indirect_type = flags;