2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/errno.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
27 #include <linux/bcd.h>
28 #include <linux/platform_device.h>
31 #include <asm/bootinfo.h>
32 #include <asm/setup.h>
34 #include <asm/traps.h>
35 #include <asm/machdep.h>
36 #include <asm/q40_master.h>
37 #include <asm/config.h>
39 extern void q40_init_IRQ(void);
40 static void q40_get_model(char *model);
41 extern void q40_sched_init(void);
43 static int q40_hwclk(int, struct rtc_time *);
44 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
45 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
47 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
49 static void q40_mem_console_write(struct console *co, const char *b,
54 static struct console q40_console_driver = {
56 .write = q40_mem_console_write,
57 .flags = CON_PRINTBUFFER,
62 /* early debugging function:*/
63 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
66 static void q40_mem_console_write(struct console *co, const char *s,
71 if (count < _cpleft) {
80 static int __init q40_debug_setup(char *arg)
82 /* useful for early debugging stages - writes kernel messages into SRAM */
83 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
84 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
85 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
86 register_console(&q40_console_driver);
91 early_param("debug", q40_debug_setup);
94 void printq40(char *str)
97 char *p = q40_mem_cptr;
99 while (l-- > 0 && _cpleft-- > 0) {
109 #ifdef CONFIG_HEARTBEAT
110 static void q40_heartbeat(int on)
122 static void q40_reset(void)
125 pr_info("*******************************************\n"
126 "Called q40_reset : press the RESET button!!\n"
127 "*******************************************\n");
133 static void q40_halt(void)
136 pr_info("*******************\n"
138 "*******************\n");
144 static void q40_get_model(char *model)
146 sprintf(model, "Q40");
149 static unsigned int serports[] =
151 0x3f8,0x2f8,0x3e8,0x2e8,0
154 static void __init q40_disable_irqs(void)
159 while ((i = serports[j++]))
160 outb(0, i + UART_IER);
161 master_outb(0, EXT_ENABLE_REG);
162 master_outb(0, KEY_IRQ_ENABLE_REG);
165 void __init config_q40(void)
167 mach_sched_init = q40_sched_init;
169 mach_init_IRQ = q40_init_IRQ;
170 mach_hwclk = q40_hwclk;
171 mach_get_rtc_pll = q40_get_rtc_pll;
172 mach_set_rtc_pll = q40_set_rtc_pll;
174 mach_reset = q40_reset;
175 mach_get_model = q40_get_model;
177 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
178 mach_beep = q40_mksound;
180 #ifdef CONFIG_HEARTBEAT
181 mach_heartbeat = q40_heartbeat;
183 mach_halt = q40_halt;
185 /* disable a few things that SMSQ might have left enabled */
190 int __init q40_parse_bootinfo(const struct bi_record *rec)
196 * Looks like op is non-zero for setting the clock, and zero for
199 * struct hwclk_time {
200 * unsigned sec; 0..59
201 * unsigned min; 0..59
202 * unsigned hour; 0..23
203 * unsigned day; 1..31
204 * unsigned mon; 0..11
205 * unsigned year; 00...
206 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
210 static int q40_hwclk(int op, struct rtc_time *t)
214 Q40_RTC_CTRL |= Q40_RTC_WRITE;
216 Q40_RTC_SECS = bin2bcd(t->tm_sec);
217 Q40_RTC_MINS = bin2bcd(t->tm_min);
218 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
219 Q40_RTC_DATE = bin2bcd(t->tm_mday);
220 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
221 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
223 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
225 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
228 Q40_RTC_CTRL |= Q40_RTC_READ;
230 t->tm_year = bcd2bin (Q40_RTC_YEAR);
231 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
232 t->tm_mday = bcd2bin (Q40_RTC_DATE);
233 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
234 t->tm_min = bcd2bin (Q40_RTC_MINS);
235 t->tm_sec = bcd2bin (Q40_RTC_SECS);
237 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
241 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
247 /* get and set PLL calibration of RTC clock */
248 #define Q40_RTC_PLL_MASK ((1<<5)-1)
249 #define Q40_RTC_PLL_SIGN (1<<5)
251 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
253 int tmp = Q40_RTC_CTRL;
256 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
257 if (tmp & Q40_RTC_PLL_SIGN)
258 pll->pll_value = -pll->pll_value;
261 pll->pll_posmult = 512;
262 pll->pll_negmult = 256;
263 pll->pll_clock = 125829120;
268 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
270 if (!pll->pll_ctrl) {
271 /* the docs are a bit unclear so I am doublesetting */
272 /* RTC_WRITE here ... */
273 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
275 Q40_RTC_CTRL |= Q40_RTC_WRITE;
277 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
283 #define PCIDE_BASE1 0x1f0
284 #define PCIDE_BASE2 0x170
285 #define PCIDE_CTL 0x206
287 static const struct resource q40_pata_rsrc_0[] __initconst = {
288 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38),
289 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2),
290 DEFINE_RES_IO(PCIDE_BASE1, 8),
291 DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1),
295 static const struct resource q40_pata_rsrc_1[] __initconst = {
296 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38),
297 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2),
298 DEFINE_RES_IO(PCIDE_BASE2, 8),
299 DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1),
303 static __init int q40_platform_init(void)
308 platform_device_register_simple("q40kbd", -1, NULL, 0);
310 platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0,
311 ARRAY_SIZE(q40_pata_rsrc_0));
313 platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1,
314 ARRAY_SIZE(q40_pata_rsrc_1));
318 arch_initcall(q40_platform_init);