1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/m68k/mm/cache.c
5 * Instruction cache handling
7 * Copyright (C) 1995 Hamish Macdonald
10 #include <linux/module.h>
11 #include <asm/pgalloc.h>
12 #include <asm/traps.h>
15 static unsigned long virt_to_phys_slow(unsigned long vaddr)
20 /* The PLPAR instruction causes an access error if the translation
21 * is not possible. To catch this we use the same exception mechanism
22 * as for user space accesses in <asm/uaccess.h>. */
23 asm volatile (".chip 68060\n"
27 ".section .fixup,\"ax\"\n"
32 ".section __ex_table,\"a\"\n"
39 } else if (CPU_IS_040) {
42 asm volatile (".chip 68040\n\t"
44 "movec %%mmusr, %0\n\t"
49 if (mmusr & MMU_R_040)
50 return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
53 unsigned long *descaddr;
55 asm volatile ("ptestr %3,%2@,#7,%0\n\t"
57 : "=a&" (descaddr), "=m" (mmusr)
58 : "a" (vaddr), "d" (get_fs().seg));
59 if (mmusr & (MMU_I|MMU_B|MMU_L))
61 descaddr = phys_to_virt((unsigned long)descaddr);
62 switch (mmusr & MMU_NUM) {
64 return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff);
66 return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff);
68 return (*descaddr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
74 /* Push n pages at kernel virtual address and clear the icache */
75 /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
76 void flush_icache_range(unsigned long address, unsigned long endaddr)
78 if (CPU_IS_COLDFIRE) {
79 unsigned long start, end;
80 start = address & ICACHE_SET_MASK;
81 end = endaddr & ICACHE_SET_MASK;
83 flush_cf_icache(0, end);
84 end = ICACHE_MAX_ADDR;
86 flush_cf_icache(start, end);
87 } else if (CPU_IS_040_OR_060) {
91 asm volatile ("nop\n\t"
93 "cpushp %%bc,(%0)\n\t"
95 : : "a" (virt_to_phys_slow(address)));
97 } while (address < endaddr);
100 asm volatile ("movec %%cacr,%0\n\t"
107 EXPORT_SYMBOL(flush_icache_range);
109 void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
110 unsigned long addr, int len)
112 if (CPU_IS_COLDFIRE) {
113 unsigned long start, end;
114 start = addr & ICACHE_SET_MASK;
115 end = (addr + len) & ICACHE_SET_MASK;
117 flush_cf_icache(0, end);
118 end = ICACHE_MAX_ADDR;
120 flush_cf_icache(start, end);
122 } else if (CPU_IS_040_OR_060) {
123 asm volatile ("nop\n\t"
125 "cpushp %%bc,(%0)\n\t"
127 : : "a" (page_to_phys(page)));
130 asm volatile ("movec %%cacr,%0\n\t"