arch/loongarch/kernel/head.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  */
   5 #include <linux/init.h>
   6 #include <linux/threads.h>
   7
   8 #include <asm/addrspace.h>
   9 #include <asm/asm.h>
  10 #include <asm/asmmacro.h>
  11 #include <asm/bug.h>
  12 #include <asm/regdef.h>
  13 #include <asm/loongarch.h>
  14 #include <asm/stackframe.h>
  15
  16 #ifdef CONFIG_EFI_STUB
  17
  18 #include "efi-header.S"
  19
  20         __HEAD
  21
  22 _head:
  23         .word   MZ_MAGIC                /* "MZ", MS-DOS header */
  24         .org    0x8
  25         .dword  kernel_entry            /* Kernel entry point */
  26         .dword  _end - _text            /* Kernel image effective size */
  27         .quad   0                       /* Kernel image load offset from start of RAM */
  28         .org    0x3c                    /* 0x20 ~ 0x3b reserved */
  29         .long   pe_header - _head       /* Offset to the PE header */
  30
  31 pe_header:
  32         __EFI_PE_HEADER
  33
  34 SYM_DATA(kernel_asize, .long _end - _text);
  35 SYM_DATA(kernel_fsize, .long _edata - _text);
  36 SYM_DATA(kernel_offset, .long kernel_offset - _text);
  37
  38 #endif
  39
  40         __REF
  41
  42         .align 12
  43
  44 SYM_CODE_START(kernel_entry)                    # kernel entry point
  45
  46         /* Config direct window and set PG */
  47         li.d            t0, CSR_DMW0_INIT       # UC, PLV0, 0x8000 xxxx xxxx xxxx
  48         csrwr           t0, LOONGARCH_CSR_DMWIN0
  49         li.d            t0, CSR_DMW1_INIT       # CA, PLV0, 0x9000 xxxx xxxx xxxx
  50         csrwr           t0, LOONGARCH_CSR_DMWIN1
  51
  52         /* We might not get launched at the address the kernel is linked to,
  53            so we jump there.  */
  54         la.abs          t0, 0f
  55         jr              t0
  56 0:
  57         /* Enable PG */
  58         li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
  59         csrwr           t0, LOONGARCH_CSR_CRMD
  60         li.w            t0, 0x04                # PLV=0, PIE=1, PWE=0
  61         csrwr           t0, LOONGARCH_CSR_PRMD
  62         li.w            t0, 0x00                # FPE=0, SXE=0, ASXE=0, BTE=0
  63         csrwr           t0, LOONGARCH_CSR_EUEN
  64
  65         la.pcrel        t0, __bss_start         # clear .bss
  66         st.d            zero, t0, 0
  67         la.pcrel        t1, __bss_stop - LONGSIZE
  68 1:
  69         addi.d          t0, t0, LONGSIZE
  70         st.d            zero, t0, 0
  71         bne             t0, t1, 1b
  72
  73         la.pcrel        t0, fw_arg0
  74         st.d            a0, t0, 0               # firmware arguments
  75         la.pcrel        t0, fw_arg1
  76         st.d            a1, t0, 0
  77         la.pcrel        t0, fw_arg2
  78         st.d            a2, t0, 0
  79
  80         /* KSave3 used for percpu base, initialized as 0 */
  81         csrwr           zero, PERCPU_BASE_KS
  82         /* GPR21 used for percpu base (runtime), initialized as 0 */
  83         move            u0, zero
  84
  85         la.pcrel        tp, init_thread_union
  86         /* Set the SP after an empty pt_regs.  */
  87         PTR_LI          sp, (_THREAD_SIZE - PT_SIZE)
  88         PTR_ADD         sp, sp, tp
  89         set_saved_sp    sp, t0, t1
  90
  91         bl              start_kernel
  92         ASM_BUG()
  93
  94 SYM_CODE_END(kernel_entry)
  95
  96 #ifdef CONFIG_SMP
  97
  98 /*
  99  * SMP slave cpus entry point.  Board specific code for bootstrap calls this
 100  * function after setting up the stack and tp registers.
 101  */
 102 SYM_CODE_START(smpboot_entry)
 103         li.d            t0, CSR_DMW0_INIT       # UC, PLV0
 104         csrwr           t0, LOONGARCH_CSR_DMWIN0
 105         li.d            t0, CSR_DMW1_INIT       # CA, PLV0
 106         csrwr           t0, LOONGARCH_CSR_DMWIN1
 107
 108         la.abs          t0, 0f
 109         jr              t0
 110 0:
 111         /* Enable PG */
 112         li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
 113         csrwr           t0, LOONGARCH_CSR_CRMD
 114         li.w            t0, 0x04                # PLV=0, PIE=1, PWE=0
 115         csrwr           t0, LOONGARCH_CSR_PRMD
 116         li.w            t0, 0x00                # FPE=0, SXE=0, ASXE=0, BTE=0
 117         csrwr           t0, LOONGARCH_CSR_EUEN
 118
 119         la.abs          t0, cpuboot_data
 120         ld.d            sp, t0, CPU_BOOT_STACK
 121         ld.d            tp, t0, CPU_BOOT_TINFO
 122
 123         bl              start_secondary
 124         ASM_BUG()
 125
 126 SYM_CODE_END(smpboot_entry)
 127
 128 #endif /* CONFIG_SMP */
 129
 130 SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)