arch/loongarch/kernel/head.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  */
   5 #include <linux/init.h>
   6 #include <linux/threads.h>
   7
   8 #include <asm/addrspace.h>
   9 #include <asm/asm.h>
  10 #include <asm/asmmacro.h>
  11 #include <asm/bug.h>
  12 #include <asm/regdef.h>
  13 #include <asm/loongarch.h>
  14 #include <asm/stackframe.h>
  15
  16 #ifdef CONFIG_EFI_STUB
  17
  18 #include "efi-header.S"
  19
  20         __HEAD
  21
  22 _head:
  23         .word   MZ_MAGIC                /* "MZ", MS-DOS header */
  24         .org    0x8
  25         .dword  kernel_entry            /* Kernel entry point */
  26         .dword  _kernel_asize           /* Kernel image effective size */
  27         .quad   PHYS_LINK_KADDR         /* Kernel image load offset from start of RAM */
  28         .org    0x38                    /* 0x20 ~ 0x37 reserved */
  29         .long   LINUX_PE_MAGIC
  30         .long   pe_header - _head       /* Offset to the PE header */
  31
  32 pe_header:
  33         __EFI_PE_HEADER
  34
  35 SYM_DATA(kernel_asize, .long _kernel_asize);
  36 SYM_DATA(kernel_fsize, .long _kernel_fsize);
  37 SYM_DATA(kernel_offset, .long _kernel_offset);
  38
  39 #endif
  40
  41         __REF
  42
  43         .align 12
  44
  45 SYM_CODE_START(kernel_entry)                    # kernel entry point
  46
  47         /* Config direct window and set PG */
  48         li.d            t0, CSR_DMW0_INIT       # UC, PLV0, 0x8000 xxxx xxxx xxxx
  49         csrwr           t0, LOONGARCH_CSR_DMWIN0
  50         li.d            t0, CSR_DMW1_INIT       # CA, PLV0, 0x9000 xxxx xxxx xxxx
  51         csrwr           t0, LOONGARCH_CSR_DMWIN1
  52
  53         JUMP_VIRT_ADDR  t0, t1
  54
  55         /* Enable PG */
  56         li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
  57         csrwr           t0, LOONGARCH_CSR_CRMD
  58         li.w            t0, 0x04                # PLV=0, PIE=1, PWE=0
  59         csrwr           t0, LOONGARCH_CSR_PRMD
  60         li.w            t0, 0x00                # FPE=0, SXE=0, ASXE=0, BTE=0
  61         csrwr           t0, LOONGARCH_CSR_EUEN
  62
  63         la.pcrel        t0, __bss_start         # clear .bss
  64         st.d            zero, t0, 0
  65         la.pcrel        t1, __bss_stop - LONGSIZE
  66 1:
  67         addi.d          t0, t0, LONGSIZE
  68         st.d            zero, t0, 0
  69         bne             t0, t1, 1b
  70
  71         la.pcrel        t0, fw_arg0
  72         st.d            a0, t0, 0               # firmware arguments
  73         la.pcrel        t0, fw_arg1
  74         st.d            a1, t0, 0
  75         la.pcrel        t0, fw_arg2
  76         st.d            a2, t0, 0
  77
  78         /* KSave3 used for percpu base, initialized as 0 */
  79         csrwr           zero, PERCPU_BASE_KS
  80         /* GPR21 used for percpu base (runtime), initialized as 0 */
  81         move            u0, zero
  82
  83         la.pcrel        tp, init_thread_union
  84         /* Set the SP after an empty pt_regs.  */
  85         PTR_LI          sp, (_THREAD_SIZE - PT_SIZE)
  86         PTR_ADD         sp, sp, tp
  87         set_saved_sp    sp, t0, t1
  88
  89 #ifdef CONFIG_RELOCATABLE
  90
  91         bl              relocate_kernel
  92
  93 #ifdef CONFIG_RANDOMIZE_BASE
  94         /* Repoint the sp into the new kernel */
  95         PTR_LI          sp, (_THREAD_SIZE - PT_SIZE)
  96         PTR_ADD         sp, sp, tp
  97         set_saved_sp    sp, t0, t1
  98
  99         /* Jump to the new kernel: new_pc = current_pc + random_offset */
 100         pcaddi          t0, 0
 101         add.d           t0, t0, a0
 102         jirl            zero, t0, 0xc
 103 #endif /* CONFIG_RANDOMIZE_BASE */
 104
 105 #endif /* CONFIG_RELOCATABLE */
 106
 107 #ifdef CONFIG_KASAN
 108         bl              kasan_early_init
 109 #endif
 110
 111         bl              start_kernel
 112         ASM_BUG()
 113
 114 SYM_CODE_END(kernel_entry)
 115
 116 #ifdef CONFIG_SMP
 117
 118 /*
 119  * SMP slave cpus entry point.  Board specific code for bootstrap calls this
 120  * function after setting up the stack and tp registers.
 121  */
 122 SYM_CODE_START(smpboot_entry)
 123         li.d            t0, CSR_DMW0_INIT       # UC, PLV0
 124         csrwr           t0, LOONGARCH_CSR_DMWIN0
 125         li.d            t0, CSR_DMW1_INIT       # CA, PLV0
 126         csrwr           t0, LOONGARCH_CSR_DMWIN1
 127
 128         JUMP_VIRT_ADDR  t0, t1
 129
 130         /* Enable PG */
 131         li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
 132         csrwr           t0, LOONGARCH_CSR_CRMD
 133         li.w            t0, 0x04                # PLV=0, PIE=1, PWE=0
 134         csrwr           t0, LOONGARCH_CSR_PRMD
 135         li.w            t0, 0x00                # FPE=0, SXE=0, ASXE=0, BTE=0
 136         csrwr           t0, LOONGARCH_CSR_EUEN
 137
 138         la.pcrel        t0, cpuboot_data
 139         ld.d            sp, t0, CPU_BOOT_STACK
 140         ld.d            tp, t0, CPU_BOOT_TINFO
 141
 142         bl              start_secondary
 143         ASM_BUG()
 144
 145 SYM_CODE_END(smpboot_entry)
 146
 147 #endif /* CONFIG_SMP */
 148
 149 SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)