1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
5 #include <linux/init.h>
6 #include <linux/threads.h>
8 #include <asm/addrspace.h>
10 #include <asm/asmmacro.h>
12 #include <asm/regdef.h>
13 #include <asm/loongarch.h>
14 #include <asm/stackframe.h>
16 #ifdef CONFIG_EFI_STUB
18 #include "efi-header.S"
23 .word MZ_MAGIC /* "MZ", MS-DOS header */
25 .dword kernel_entry /* Kernel entry point */
26 .dword _kernel_asize /* Kernel image effective size */
27 .quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */
28 .org 0x38 /* 0x20 ~ 0x37 reserved */
30 .long pe_header - _head /* Offset to the PE header */
35 SYM_DATA(kernel_asize, .long _kernel_asize);
36 SYM_DATA(kernel_fsize, .long _kernel_fsize);
37 SYM_DATA(kernel_offset, .long _kernel_offset);
45 SYM_CODE_START(kernel_entry) # kernel entry point
47 /* Config direct window and set PG */
48 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx
49 csrwr t0, LOONGARCH_CSR_DMWIN0
50 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx
51 csrwr t0, LOONGARCH_CSR_DMWIN1
56 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
57 csrwr t0, LOONGARCH_CSR_CRMD
58 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
59 csrwr t0, LOONGARCH_CSR_PRMD
60 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
61 csrwr t0, LOONGARCH_CSR_EUEN
63 la.pcrel t0, __bss_start # clear .bss
65 la.pcrel t1, __bss_stop - LONGSIZE
67 addi.d t0, t0, LONGSIZE
72 st.d a0, t0, 0 # firmware arguments
78 /* KSave3 used for percpu base, initialized as 0 */
79 csrwr zero, PERCPU_BASE_KS
80 /* GPR21 used for percpu base (runtime), initialized as 0 */
83 la.pcrel tp, init_thread_union
84 /* Set the SP after an empty pt_regs. */
85 PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
87 set_saved_sp sp, t0, t1
89 #ifdef CONFIG_RELOCATABLE
93 #ifdef CONFIG_RANDOMIZE_BASE
94 /* Repoint the sp into the new kernel */
95 PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
97 set_saved_sp sp, t0, t1
99 /* Jump to the new kernel: new_pc = current_pc + random_offset */
103 #endif /* CONFIG_RANDOMIZE_BASE */
105 #endif /* CONFIG_RELOCATABLE */
114 SYM_CODE_END(kernel_entry)
119 * SMP slave cpus entry point. Board specific code for bootstrap calls this
120 * function after setting up the stack and tp registers.
122 SYM_CODE_START(smpboot_entry)
123 li.d t0, CSR_DMW0_INIT # UC, PLV0
124 csrwr t0, LOONGARCH_CSR_DMWIN0
125 li.d t0, CSR_DMW1_INIT # CA, PLV0
126 csrwr t0, LOONGARCH_CSR_DMWIN1
128 JUMP_VIRT_ADDR t0, t1
131 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
132 csrwr t0, LOONGARCH_CSR_CRMD
133 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
134 csrwr t0, LOONGARCH_CSR_PRMD
135 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
136 csrwr t0, LOONGARCH_CSR_EUEN
138 la.pcrel t0, cpuboot_data
139 ld.d sp, t0, CPU_BOOT_STACK
140 ld.d tp, t0, CPU_BOOT_TINFO
145 SYM_CODE_END(smpboot_entry)
147 #endif /* CONFIG_SMP */
149 SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)