1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
8 #include <linux/bitops.h>
9 #include <linux/types.h>
11 #include <asm/ptrace.h>
13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
16 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
17 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
18 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
19 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
20 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
22 #define ADDR_IMMSHIFT_LU52ID 52
23 #define ADDR_IMMSBIDX_LU52ID 11
24 #define ADDR_IMMSHIFT_LU32ID 32
25 #define ADDR_IMMSBIDX_LU32ID 19
26 #define ADDR_IMMSHIFT_LU12IW 12
27 #define ADDR_IMMSBIDX_LU12IW 19
28 #define ADDR_IMMSHIFT_ORI 0
29 #define ADDR_IMMSBIDX_ORI 63
30 #define ADDR_IMMSHIFT_ADDU16ID 16
31 #define ADDR_IMMSBIDX_ADDU16ID 15
33 #define ADDR_IMM(addr, INSN) \
34 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN))
57 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
58 bcnez_op = 0x12, /* bits[9:8] = 0x01 */
70 iocsrrdb_op = 0x19200,
71 iocsrrdh_op = 0x19201,
72 iocsrrdw_op = 0x19202,
73 iocsrrdd_op = 0x19203,
74 iocsrwrb_op = 0x19204,
75 iocsrwrh_op = 0x19205,
76 iocsrwrw_op = 0x19206,
77 iocsrwrd_op = 0x19207,
208 amswapdbw_op = 0x70d2,
209 amswapdbd_op = 0x70d3,
210 amadddbw_op = 0x70d4,
211 amadddbd_op = 0x70d5,
212 amanddbw_op = 0x70d6,
213 amanddbd_op = 0x70d7,
216 amxordbw_op = 0x70da,
217 amxordbd_op = 0x70db,
218 ammaxdbw_op = 0x70dc,
219 ammaxdbd_op = 0x70dd,
220 ammindbw_op = 0x70de,
221 ammindbd_op = 0x70df,
222 ammaxdbwu_op = 0x70e0,
223 ammaxdbdu_op = 0x70e1,
224 ammindbwu_op = 0x70e2,
225 ammindbdu_op = 0x70e3,
258 struct reg0i15_format {
259 unsigned int immediate : 15;
260 unsigned int opcode : 17;
263 struct reg0i26_format {
264 unsigned int immediate_h : 10;
265 unsigned int immediate_l : 16;
266 unsigned int opcode : 6;
269 struct reg1i20_format {
271 unsigned int immediate : 20;
272 unsigned int opcode : 7;
275 struct reg1i21_format {
276 unsigned int immediate_h : 5;
278 unsigned int immediate_l : 16;
279 unsigned int opcode : 6;
285 unsigned int opcode : 22;
288 struct reg2i5_format {
291 unsigned int immediate : 5;
292 unsigned int opcode : 17;
295 struct reg2i6_format {
298 unsigned int immediate : 6;
299 unsigned int opcode : 16;
302 struct reg2i12_format {
305 unsigned int immediate : 12;
306 unsigned int opcode : 10;
309 struct reg2i14_format {
312 unsigned int immediate : 14;
313 unsigned int opcode : 8;
316 struct reg2i16_format {
319 unsigned int immediate : 16;
320 unsigned int opcode : 6;
323 struct reg2bstrd_format {
326 unsigned int lsbd : 6;
327 unsigned int msbd : 6;
328 unsigned int opcode : 10;
331 struct reg2csr_format {
334 unsigned int csr : 14;
335 unsigned int opcode : 8;
342 unsigned int opcode : 17;
345 struct reg3sa2_format {
349 unsigned int immediate : 2;
350 unsigned int opcode : 15;
353 union loongarch_instruction {
355 struct reg0i15_format reg0i15_format;
356 struct reg0i26_format reg0i26_format;
357 struct reg1i20_format reg1i20_format;
358 struct reg1i21_format reg1i21_format;
359 struct reg2_format reg2_format;
360 struct reg2i5_format reg2i5_format;
361 struct reg2i6_format reg2i6_format;
362 struct reg2i12_format reg2i12_format;
363 struct reg2i14_format reg2i14_format;
364 struct reg2i16_format reg2i16_format;
365 struct reg2bstrd_format reg2bstrd_format;
366 struct reg2csr_format reg2csr_format;
367 struct reg3_format reg3_format;
368 struct reg3sa2_format reg3sa2_format;
371 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
374 LOONGARCH_GPR_ZERO = 0,
375 LOONGARCH_GPR_RA = 1,
376 LOONGARCH_GPR_TP = 2,
377 LOONGARCH_GPR_SP = 3,
378 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
379 LOONGARCH_GPR_A1, /* Reused as V1 for return value */
386 LOONGARCH_GPR_T0 = 12,
395 LOONGARCH_GPR_FP = 22,
396 LOONGARCH_GPR_S0 = 23,
408 #define is_imm12_negative(val) is_imm_negative(val, 12)
410 static inline bool is_imm_negative(unsigned long val, unsigned int bit)
412 return val & (1UL << (bit - 1));
415 static inline bool is_break_ins(union loongarch_instruction *ip)
417 return ip->reg0i15_format.opcode == break_op;
420 static inline bool is_pc_ins(union loongarch_instruction *ip)
422 return ip->reg1i20_format.opcode >= pcaddi_op &&
423 ip->reg1i20_format.opcode <= pcaddu18i_op;
426 static inline bool is_branch_ins(union loongarch_instruction *ip)
428 return ip->reg1i21_format.opcode >= beqz_op &&
429 ip->reg1i21_format.opcode <= bgeu_op;
432 static inline bool is_ra_save_ins(union loongarch_instruction *ip)
434 /* st.d $ra, $sp, offset */
435 return ip->reg2i12_format.opcode == std_op &&
436 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
437 ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
438 !is_imm12_negative(ip->reg2i12_format.immediate);
441 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
443 /* addi.d $sp, $sp, -imm */
444 return ip->reg2i12_format.opcode == addid_op &&
445 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
446 ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
447 is_imm12_negative(ip->reg2i12_format.immediate);
450 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs)
452 switch (ip->reg0i26_format.opcode) {
455 if (ip->reg0i26_format.immediate_l == 0
456 && ip->reg0i26_format.immediate_h == 0)
460 switch (ip->reg1i21_format.opcode) {
464 if (ip->reg1i21_format.immediate_l == 0
465 && ip->reg1i21_format.immediate_h == 0)
469 switch (ip->reg2i16_format.opcode) {
476 if (ip->reg2i16_format.immediate == 0)
480 if (regs->regs[ip->reg2i16_format.rj] +
481 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip)
488 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn);
489 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn);
491 bool insns_not_supported(union loongarch_instruction insn);
492 bool insns_need_simulation(union loongarch_instruction insn);
493 void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs);
495 int larch_insn_read(void *addr, u32 *insnp);
496 int larch_insn_write(void *addr, u32 insn);
497 int larch_insn_patch_text(void *addr, u32 insn);
499 u32 larch_insn_gen_nop(void);
500 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
501 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);
503 u32 larch_insn_gen_break(int imm);
505 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
506 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
508 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
509 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
510 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
511 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
513 static inline bool signed_imm_check(long val, unsigned int bit)
515 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));
518 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
520 return val < (1UL << bit);
523 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \
524 static inline void emit_##NAME(union loongarch_instruction *insn, \
527 insn->reg0i15_format.opcode = OP; \
528 insn->reg0i15_format.immediate = imm; \
531 DEF_EMIT_REG0I15_FORMAT(break, break_op)
533 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
534 static inline void emit_##NAME(union loongarch_instruction *insn, \
537 unsigned int immediate_l, immediate_h; \
539 immediate_l = offset & 0xffff; \
541 immediate_h = offset & 0x3ff; \
543 insn->reg0i26_format.opcode = OP; \
544 insn->reg0i26_format.immediate_l = immediate_l; \
545 insn->reg0i26_format.immediate_h = immediate_h; \
548 DEF_EMIT_REG0I26_FORMAT(b, b_op)
549 DEF_EMIT_REG0I26_FORMAT(bl, bl_op)
551 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \
552 static inline void emit_##NAME(union loongarch_instruction *insn, \
553 enum loongarch_gpr rd, int imm) \
555 insn->reg1i20_format.opcode = OP; \
556 insn->reg1i20_format.immediate = imm; \
557 insn->reg1i20_format.rd = rd; \
560 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
561 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
562 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
564 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \
565 static inline void emit_##NAME(union loongarch_instruction *insn, \
566 enum loongarch_gpr rd, \
567 enum loongarch_gpr rj) \
569 insn->reg2_format.opcode = OP; \
570 insn->reg2_format.rd = rd; \
571 insn->reg2_format.rj = rj; \
574 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
575 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
576 DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
577 DEF_EMIT_REG2_FORMAT(extwh, extwh_op)
578 DEF_EMIT_REG2_FORMAT(extwb, extwb_op)
580 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
581 static inline void emit_##NAME(union loongarch_instruction *insn, \
582 enum loongarch_gpr rd, \
583 enum loongarch_gpr rj, \
586 insn->reg2i5_format.opcode = OP; \
587 insn->reg2i5_format.immediate = imm; \
588 insn->reg2i5_format.rd = rd; \
589 insn->reg2i5_format.rj = rj; \
592 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
593 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
594 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
596 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \
597 static inline void emit_##NAME(union loongarch_instruction *insn, \
598 enum loongarch_gpr rd, \
599 enum loongarch_gpr rj, \
602 insn->reg2i6_format.opcode = OP; \
603 insn->reg2i6_format.immediate = imm; \
604 insn->reg2i6_format.rd = rd; \
605 insn->reg2i6_format.rj = rj; \
608 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
609 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
610 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
612 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \
613 static inline void emit_##NAME(union loongarch_instruction *insn, \
614 enum loongarch_gpr rd, \
615 enum loongarch_gpr rj, \
618 insn->reg2i12_format.opcode = OP; \
619 insn->reg2i12_format.immediate = imm; \
620 insn->reg2i12_format.rd = rd; \
621 insn->reg2i12_format.rj = rj; \
624 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
625 DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
626 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
627 DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
628 DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
629 DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
630 DEF_EMIT_REG2I12_FORMAT(ldb, ldb_op)
631 DEF_EMIT_REG2I12_FORMAT(ldh, ldh_op)
632 DEF_EMIT_REG2I12_FORMAT(ldw, ldw_op)
633 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
634 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
635 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
636 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
637 DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
638 DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
639 DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
640 DEF_EMIT_REG2I12_FORMAT(std, std_op)
642 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \
643 static inline void emit_##NAME(union loongarch_instruction *insn, \
644 enum loongarch_gpr rd, \
645 enum loongarch_gpr rj, \
648 insn->reg2i14_format.opcode = OP; \
649 insn->reg2i14_format.immediate = imm; \
650 insn->reg2i14_format.rd = rd; \
651 insn->reg2i14_format.rj = rj; \
654 DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
655 DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
656 DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
657 DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
658 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
659 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
660 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
661 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
663 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
664 static inline void emit_##NAME(union loongarch_instruction *insn, \
665 enum loongarch_gpr rj, \
666 enum loongarch_gpr rd, \
669 insn->reg2i16_format.opcode = OP; \
670 insn->reg2i16_format.immediate = offset; \
671 insn->reg2i16_format.rj = rj; \
672 insn->reg2i16_format.rd = rd; \
675 DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
676 DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
677 DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
678 DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
679 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
680 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
681 DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
683 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \
684 static inline void emit_##NAME(union loongarch_instruction *insn, \
685 enum loongarch_gpr rd, \
686 enum loongarch_gpr rj, \
690 insn->reg2bstrd_format.opcode = OP; \
691 insn->reg2bstrd_format.msbd = msbd; \
692 insn->reg2bstrd_format.lsbd = lsbd; \
693 insn->reg2bstrd_format.rj = rj; \
694 insn->reg2bstrd_format.rd = rd; \
697 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
699 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \
700 static inline void emit_##NAME(union loongarch_instruction *insn, \
701 enum loongarch_gpr rd, \
702 enum loongarch_gpr rj, \
703 enum loongarch_gpr rk) \
705 insn->reg3_format.opcode = OP; \
706 insn->reg3_format.rd = rd; \
707 insn->reg3_format.rj = rj; \
708 insn->reg3_format.rk = rk; \
711 DEF_EMIT_REG3_FORMAT(addw, addw_op)
712 DEF_EMIT_REG3_FORMAT(addd, addd_op)
713 DEF_EMIT_REG3_FORMAT(subd, subd_op)
714 DEF_EMIT_REG3_FORMAT(muld, muld_op)
715 DEF_EMIT_REG3_FORMAT(divd, divd_op)
716 DEF_EMIT_REG3_FORMAT(modd, modd_op)
717 DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
718 DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
719 DEF_EMIT_REG3_FORMAT(and, and_op)
720 DEF_EMIT_REG3_FORMAT(or, or_op)
721 DEF_EMIT_REG3_FORMAT(xor, xor_op)
722 DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
723 DEF_EMIT_REG3_FORMAT(slld, slld_op)
724 DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
725 DEF_EMIT_REG3_FORMAT(srld, srld_op)
726 DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
727 DEF_EMIT_REG3_FORMAT(srad, srad_op)
728 DEF_EMIT_REG3_FORMAT(ldxb, ldxb_op)
729 DEF_EMIT_REG3_FORMAT(ldxh, ldxh_op)
730 DEF_EMIT_REG3_FORMAT(ldxw, ldxw_op)
731 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
732 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
733 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
734 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
735 DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
736 DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
737 DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
738 DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
739 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
740 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
741 DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
742 DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
743 DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
744 DEF_EMIT_REG3_FORMAT(amord, amord_op)
745 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
746 DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
747 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
748 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
750 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
751 static inline void emit_##NAME(union loongarch_instruction *insn, \
752 enum loongarch_gpr rd, \
753 enum loongarch_gpr rj, \
754 enum loongarch_gpr rk, \
757 insn->reg3sa2_format.opcode = OP; \
758 insn->reg3sa2_format.immediate = imm; \
759 insn->reg3sa2_format.rd = rd; \
760 insn->reg3sa2_format.rj = rj; \
761 insn->reg3sa2_format.rk = rk; \
764 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
768 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
769 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
770 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
772 #endif /* _ASM_INST_H */