1 // SPDX-License-Identifier: GPL-2.0-only
3 * SMP boot-related support
5 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 2001, 2004-2005 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Ashok Raj <ashok.raj@intel.com>
13 * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
14 * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
15 * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
16 * smp_boot_cpus()/smp_commence() is replaced by
17 * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
18 * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
19 * 04/12/26 Jin Gordon <gordon.jin@intel.com>
20 * 04/12/26 Rohit Seth <rohit.seth@intel.com>
21 * Add multi-threading and multi-core detection
22 * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
23 * Setup cpu_sibling_map and cpu_core_map
26 #include <linux/module.h>
27 #include <linux/acpi.h>
28 #include <linux/memblock.h>
29 #include <linux/cpu.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/kernel.h>
35 #include <linux/kernel_stat.h>
37 #include <linux/notifier.h>
38 #include <linux/smp.h>
39 #include <linux/spinlock.h>
40 #include <linux/efi.h>
41 #include <linux/percpu.h>
42 #include <linux/bitops.h>
44 #include <linux/atomic.h>
45 #include <asm/cache.h>
46 #include <asm/current.h>
47 #include <asm/delay.h>
52 #include <asm/processor.h>
53 #include <asm/ptrace.h>
55 #include <asm/tlbflush.h>
56 #include <asm/unistd.h>
61 #define Dprintk(x...) printk(x)
66 #ifdef CONFIG_HOTPLUG_CPU
67 #ifdef CONFIG_PERMIT_BSP_REMOVE
68 #define bsp_remove_ok 1
70 #define bsp_remove_ok 0
74 * Global array allocated for NR_CPUS at boot time
76 struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
79 * start_ap in head.S uses this to store current booting cpu
82 struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
84 #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
87 #define set_brendez_area(x)
92 * ITC synchronization related stuff:
95 #define SLAVE (SMP_CACHE_BYTES/8)
97 #define NUM_ROUNDS 64 /* magic value */
98 #define NUM_ITERS 5 /* likewise */
100 static DEFINE_SPINLOCK(itc_sync_lock);
101 static volatile unsigned long go[SLAVE + 1];
103 #define DEBUG_ITC_SYNC 0
105 extern void start_ap (void);
106 extern unsigned long ia64_iobase;
108 struct task_struct *task_for_booting_cpu;
113 DEFINE_PER_CPU(int, cpu_state);
115 cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
116 EXPORT_SYMBOL(cpu_core_map);
117 DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
118 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
120 int smp_num_siblings = 1;
122 /* which logical CPU number maps to which CPU (physical APIC ID) */
123 volatile int ia64_cpu_to_sapicid[NR_CPUS];
124 EXPORT_SYMBOL(ia64_cpu_to_sapicid);
126 static cpumask_t cpu_callin_map;
128 struct smp_boot_data smp_boot_data __initdata;
130 unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
132 char __initdata no_int_routing;
134 unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
136 #ifdef CONFIG_FORCE_CPEI_RETARGET
137 #define CPEI_OVERRIDE_DEFAULT (1)
139 #define CPEI_OVERRIDE_DEFAULT (0)
142 unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
145 cmdl_force_cpei(char *str)
149 get_option (&str, &value);
150 force_cpei_retarget = value;
155 __setup("force_cpei=", cmdl_force_cpei);
158 nointroute (char *str)
161 printk ("no_int_routing on\n");
165 __setup("nointroute", nointroute);
167 static void fix_b0_for_bsp(void)
169 #ifdef CONFIG_HOTPLUG_CPU
171 static int fix_bsp_b0 = 1;
173 cpuid = smp_processor_id();
176 * Cache the b0 value on the first AP that comes up
178 if (!(fix_bsp_b0 && cpuid))
181 sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
182 printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
189 sync_master (void *arg)
191 unsigned long flags, i;
195 local_irq_save(flags);
197 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
201 go[SLAVE] = ia64_get_itc();
204 local_irq_restore(flags);
208 * Return the number of cycles by which our itc differs from the itc on the master
209 * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
210 * negative that it is behind.
213 get_delta (long *rt, long *master)
215 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
216 unsigned long tcenter, t0, t1, tm;
219 for (i = 0; i < NUM_ITERS; ++i) {
222 while (!(tm = go[SLAVE]))
227 if (t1 - t0 < best_t1 - best_t0)
228 best_t0 = t0, best_t1 = t1, best_tm = tm;
231 *rt = best_t1 - best_t0;
232 *master = best_tm - best_t0;
234 /* average best_t0 and best_t1 without overflow: */
235 tcenter = (best_t0/2 + best_t1/2);
236 if (best_t0 % 2 + best_t1 % 2 == 2)
238 return tcenter - best_tm;
242 * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
243 * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
244 * unaccounted-for errors (such as getting a machine check in the middle of a calibration
245 * step). The basic idea is for the slave to ask the master what itc value it has and to
246 * read its own itc before and after the master responds. Each iteration gives us three
260 * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
261 * and t1. If we achieve this, the clocks are synchronized provided the interconnect
262 * between the slave and the master is symmetric. Even if the interconnect were
263 * asymmetric, we would still know that the synchronization error is smaller than the
264 * roundtrip latency (t0 - t1).
266 * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
267 * within one or two cycles. However, we can only *guarantee* that the synchronization is
268 * accurate to within a round-trip time, which is typically in the range of several
269 * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
270 * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
271 * than half a micro second or so.
274 ia64_sync_itc (unsigned int master)
276 long i, delta, adj, adjust_latency = 0, done = 0;
277 unsigned long flags, rt, master_time_stamp, bound;
280 long rt; /* roundtrip time */
281 long master; /* master's timestamp */
282 long diff; /* difference between midpoint and master's timestamp */
283 long lat; /* estimate of itc adjustment latency */
288 * Make sure local timer ticks are disabled while we sync. If
289 * they were enabled, we'd have to worry about nasty issues
290 * like setting the ITC ahead of (or a long time before) the
291 * next scheduled tick.
293 BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
297 if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
298 printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
303 cpu_relax(); /* wait for master to be ready */
305 spin_lock_irqsave(&itc_sync_lock, flags);
307 for (i = 0; i < NUM_ROUNDS; ++i) {
308 delta = get_delta(&rt, &master_time_stamp);
310 done = 1; /* let's lock on to this... */
316 adjust_latency += -delta;
317 adj = -delta + adjust_latency/4;
321 ia64_set_itc(ia64_get_itc() + adj);
325 t[i].master = master_time_stamp;
327 t[i].lat = adjust_latency/4;
331 spin_unlock_irqrestore(&itc_sync_lock, flags);
334 for (i = 0; i < NUM_ROUNDS; ++i)
335 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
336 t[i].rt, t[i].master, t[i].diff, t[i].lat);
339 printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
340 "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
344 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
346 static inline void smp_setup_percpu_timer(void)
353 int cpuid, phys_id, itc_master;
354 struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
355 extern void ia64_init_itm(void);
356 extern volatile int time_keeper_id;
358 cpuid = smp_processor_id();
359 phys_id = hard_smp_processor_id();
360 itc_master = time_keeper_id;
362 if (cpu_online(cpuid)) {
363 printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
371 * numa_node_id() works after this.
373 set_numa_node(cpu_to_node_map[cpuid]);
374 set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
376 spin_lock(&vector_lock);
377 /* Setup the per cpu irq handling data structures */
378 __setup_vector_irq(cpuid);
379 notify_cpu_starting(cpuid);
380 set_cpu_online(cpuid, true);
381 per_cpu(cpu_state, cpuid) = CPU_ONLINE;
382 spin_unlock(&vector_lock);
384 smp_setup_percpu_timer();
386 ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
390 if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
392 * Synchronize the ITC with the BP. Need to do this after irqs are
393 * enabled because ia64_sync_itc() calls smp_call_function_single(), which
394 * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
395 * local_bh_enable(), which bugs out if irqs are not enabled...
397 Dprintk("Going to syncup ITC with ITC Master.\n");
398 ia64_sync_itc(itc_master);
407 * Delay calibration can be skipped if new processor is identical to the
408 * previous processor.
410 last_cpuinfo = cpu_data(cpuid - 1);
411 this_cpuinfo = local_cpu_data;
412 if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
413 last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
414 last_cpuinfo->features != this_cpuinfo->features ||
415 last_cpuinfo->revision != this_cpuinfo->revision ||
416 last_cpuinfo->family != this_cpuinfo->family ||
417 last_cpuinfo->archrev != this_cpuinfo->archrev ||
418 last_cpuinfo->model != this_cpuinfo->model)
420 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
423 * Allow the master to continue.
425 cpumask_set_cpu(cpuid, &cpu_callin_map);
426 Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
431 * Activate a secondary processor. head.S calls this.
434 start_secondary (void *unused)
436 /* Early console may use I/O ports */
437 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
438 #ifndef CONFIG_PRINTK_TIME
439 Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
445 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
450 do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
454 task_for_booting_cpu = idle;
455 Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
457 set_brendez_area(cpu);
458 ia64_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
461 * Wait 10s total for the AP to start
463 Dprintk("Waiting on callin_map ...");
464 for (timeout = 0; timeout < 100000; timeout++) {
465 if (cpumask_test_cpu(cpu, &cpu_callin_map))
466 break; /* It has booted */
467 barrier(); /* Make sure we re-read cpu_callin_map */
472 if (!cpumask_test_cpu(cpu, &cpu_callin_map)) {
473 printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
474 ia64_cpu_to_sapicid[cpu] = -1;
475 set_cpu_online(cpu, false); /* was set in smp_callin() */
485 get_option (&str, &ticks);
489 __setup("decay=", decay);
492 * Initialize the logical CPU number to SAPICID mapping
495 smp_build_cpu_map (void)
498 int boot_cpu_id = hard_smp_processor_id();
500 for (cpu = 0; cpu < NR_CPUS; cpu++) {
501 ia64_cpu_to_sapicid[cpu] = -1;
504 ia64_cpu_to_sapicid[0] = boot_cpu_id;
505 init_cpu_present(cpumask_of(0));
506 set_cpu_possible(0, true);
507 for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
508 sapicid = smp_boot_data.cpu_phys_id[i];
509 if (sapicid == boot_cpu_id)
511 set_cpu_present(cpu, true);
512 set_cpu_possible(cpu, true);
513 ia64_cpu_to_sapicid[cpu] = sapicid;
519 * Cycle through the APs sending Wakeup IPIs to boot each.
522 smp_prepare_cpus (unsigned int max_cpus)
524 int boot_cpu_id = hard_smp_processor_id();
527 * Initialize the per-CPU profiling counter/multiplier
530 smp_setup_percpu_timer();
532 cpumask_set_cpu(0, &cpu_callin_map);
534 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
535 ia64_cpu_to_sapicid[0] = boot_cpu_id;
537 printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
539 current_thread_info()->cpu = 0;
542 * If SMP should be disabled, then really disable it!
545 printk(KERN_INFO "SMP mode deactivated.\n");
546 init_cpu_online(cpumask_of(0));
547 init_cpu_present(cpumask_of(0));
548 init_cpu_possible(cpumask_of(0));
553 void smp_prepare_boot_cpu(void)
555 set_cpu_online(smp_processor_id(), true);
556 cpumask_set_cpu(smp_processor_id(), &cpu_callin_map);
557 set_numa_node(cpu_to_node_map[smp_processor_id()]);
558 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
561 #ifdef CONFIG_HOTPLUG_CPU
563 clear_cpu_sibling_map(int cpu)
567 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
568 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
569 for_each_cpu(i, &cpu_core_map[cpu])
570 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
572 per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
576 remove_siblinginfo(int cpu)
580 if (cpu_data(cpu)->threads_per_core == 1 &&
581 cpu_data(cpu)->cores_per_socket == 1) {
582 cpumask_clear_cpu(cpu, &cpu_core_map[cpu]);
583 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, cpu));
587 last = (cpumask_weight(&cpu_core_map[cpu]) == 1 ? 1 : 0);
589 /* remove it from all sibling map's */
590 clear_cpu_sibling_map(cpu);
593 extern void fixup_irqs(void);
595 int migrate_platform_irqs(unsigned int cpu)
598 struct irq_data *data = NULL;
599 const struct cpumask *mask;
603 * dont permit CPEI target to removed.
605 if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
606 printk ("CPU (%d) is CPEI Target\n", cpu);
607 if (can_cpei_retarget()) {
609 * Now re-target the CPEI to a different processor
611 new_cpei_cpu = cpumask_any(cpu_online_mask);
612 mask = cpumask_of(new_cpei_cpu);
613 set_cpei_target_cpu(new_cpei_cpu);
614 data = irq_get_irq_data(ia64_cpe_irq);
616 * Switch for now, immediately, we need to do fake intr
617 * as other interrupts, but need to study CPEI behaviour with
618 * polling before making changes.
620 if (data && data->chip) {
621 data->chip->irq_disable(data);
622 data->chip->irq_set_affinity(data, mask, false);
623 data->chip->irq_enable(data);
624 printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
628 printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
635 /* must be called with cpucontrol mutex held */
636 int __cpu_disable(void)
638 int cpu = smp_processor_id();
641 * dont permit boot processor for now
643 if (cpu == 0 && !bsp_remove_ok) {
644 printk ("Your platform does not support removal of BSP\n");
648 set_cpu_online(cpu, false);
650 if (migrate_platform_irqs(cpu)) {
651 set_cpu_online(cpu, true);
655 remove_siblinginfo(cpu);
657 local_flush_tlb_all();
658 cpumask_clear_cpu(cpu, &cpu_callin_map);
662 void __cpu_die(unsigned int cpu)
666 for (i = 0; i < 100; i++) {
667 /* They ack this in play_dead by setting CPU_DEAD */
668 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
670 printk ("CPU %d is now offline\n", cpu);
675 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
677 #endif /* CONFIG_HOTPLUG_CPU */
680 smp_cpus_done (unsigned int dummy)
683 unsigned long bogosum = 0;
686 * Allow the user to impress friends.
689 for_each_online_cpu(cpu) {
690 bogosum += cpu_data(cpu)->loops_per_jiffy;
693 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
694 (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
697 static inline void set_cpu_sibling_map(int cpu)
701 for_each_online_cpu(i) {
702 if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
703 cpumask_set_cpu(i, &cpu_core_map[cpu]);
704 cpumask_set_cpu(cpu, &cpu_core_map[i]);
705 if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
707 &per_cpu(cpu_sibling_map, cpu));
709 &per_cpu(cpu_sibling_map, i));
716 __cpu_up(unsigned int cpu, struct task_struct *tidle)
721 sapicid = ia64_cpu_to_sapicid[cpu];
726 * Already booted cpu? not valid anymore since we dont
727 * do idle loop tightspin anymore.
729 if (cpumask_test_cpu(cpu, &cpu_callin_map))
732 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
733 /* Processor goes to start_secondary(), sets online flag */
734 ret = do_boot_cpu(sapicid, cpu, tidle);
738 if (cpu_data(cpu)->threads_per_core == 1 &&
739 cpu_data(cpu)->cores_per_socket == 1) {
740 cpumask_set_cpu(cpu, &per_cpu(cpu_sibling_map, cpu));
741 cpumask_set_cpu(cpu, &cpu_core_map[cpu]);
745 set_cpu_sibling_map(cpu);
751 * Assume that CPUs have been discovered by some platform-dependent interface. For
752 * SoftSDV/Lion, that would be ACPI.
754 * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
757 init_smp_config(void)
765 /* Tell SAL where to drop the APs. */
766 ap_startup = (struct fptr *) start_ap;
767 sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
768 ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
770 printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
771 ia64_sal_strerror(sal_ret));
775 * identify_siblings(cpu) gets called from identify_cpu. This populates the
776 * information related to logical execution units in per_cpu_data structure.
778 void identify_siblings(struct cpuinfo_ia64 *c)
782 pal_logical_to_physical_t info;
784 status = ia64_pal_logical_to_phys(-1, &info);
785 if (status != PAL_STATUS_SUCCESS) {
786 if (status != PAL_STATUS_UNIMPLEMENTED) {
788 "ia64_pal_logical_to_phys failed with %ld\n",
793 info.overview_ppid = 0;
794 info.overview_cpp = 1;
795 info.overview_tpc = 1;
798 status = ia64_sal_physical_id_info(&pltid);
799 if (status != PAL_STATUS_SUCCESS) {
800 if (status != PAL_STATUS_UNIMPLEMENTED)
802 "ia64_sal_pltid failed with %ld\n",
807 c->socket_id = (pltid << 8) | info.overview_ppid;
809 if (info.overview_cpp == 1 && info.overview_tpc == 1)
812 c->cores_per_socket = info.overview_cpp;
813 c->threads_per_core = info.overview_tpc;
814 c->num_log = info.overview_num_log;
816 c->core_id = info.log1_cid;
817 c->thread_id = info.log1_tid;
821 * returns non zero, if multi-threading is enabled
822 * on at least one physical package. Due to hotplug cpu
823 * and (maxcpus=), all threads may not necessarily be enabled
824 * even though the processor supports multi-threading.
826 int is_multithreading_enabled(void)
830 for_each_present_cpu(i) {
831 for_each_present_cpu(j) {
834 if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
835 if (cpu_data(j)->core_id == cpu_data(i)->core_id)
842 EXPORT_SYMBOL_GPL(is_multithreading_enabled);