arch/ia64/include/asm/pal.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_IA64_PAL_H
   3 #define _ASM_IA64_PAL_H
   4
   5 /*
   6  * Processor Abstraction Layer definitions.
   7  *
   8  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
   9  * chapter 11 IA-64 Processor Abstraction Layer
  10  *
  11  * Copyright (C) 1998-2001 Hewlett-Packard Co
  12  *      David Mosberger-Tang <davidm@hpl.hp.com>
  13  *      Stephane Eranian <eranian@hpl.hp.com>
  14  * Copyright (C) 1999 VA Linux Systems
  15  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  16  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  17  * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
  18  *
  19  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
  20  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
  21  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  22  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  23  * 00/05/25     eranian Support for stack calls, and static physical calls
  24  * 00/06/18     eranian Support for stacked physical calls
  25  * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
  26  *                      Manual Rev 2.2 (Jan 2006)
  27  */
  28
  29 /*
  30  * Note that some of these calls use a static-register only calling
  31  * convention which has nothing to do with the regular calling
  32  * convention.
  33  */
  34 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
  35 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
  36 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
  37 #define PAL_CACHE_SUMMARY       4       /* get summary of cache hierarchy */
  38 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
  39 #define PAL_PTCE_INFO           6       /* purge TLB info */
  40 #define PAL_VM_INFO             7       /* return supported virtual memory features */
  41 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
  42 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
  43 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
  44 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
  45 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
  46 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
  47 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
  48 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
  49 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
  50 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
  51 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
  52 #define PAL_RSE_INFO            19      /* return rse information */
  53 #define PAL_VERSION             20      /* return version of PAL code */
  54 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
  55 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
  56 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
  57 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
  58 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
  59 #define PAL_MC_RESUME           26      /* Return to interrupted process */
  60 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
  61 #define PAL_HALT                28      /* enter the low power HALT state */
  62 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
  63 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
  64 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
  65 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
  66 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
  67 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
  68
  69 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
  70 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
  71 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
  72 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
  73 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
  74 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
  75 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
  76 #define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
  77 #define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
  78 #define PAL_VP_INFO             50      /* Information about virtual processor features */
  79 #define PAL_MC_HW_TRACKING      51      /* Hardware tracking status */
  80
  81 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
  82 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
  83 #define PAL_TEST_PROC           258     /* perform late processor self-test */
  84 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
  85 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
  86 #define PAL_VM_TR_READ          261     /* read contents of translation register */
  87 #define PAL_GET_PSTATE          262     /* get the current P-state */
  88 #define PAL_SET_PSTATE          263     /* set the P-state */
  89 #define PAL_BRAND_INFO          274     /* Processor branding information */
  90
  91 #define PAL_GET_PSTATE_TYPE_LASTSET     0
  92 #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
  93 #define PAL_GET_PSTATE_TYPE_AVGNORESET  2
  94 #define PAL_GET_PSTATE_TYPE_INSTANT     3
  95
  96 #define PAL_MC_ERROR_INJECT     276     /* Injects processor error or returns injection capabilities */
  97
  98 #ifndef __ASSEMBLY__
  99
 100 #include <linux/types.h>
 101 #include <asm/fpu.h>
 102 #include <asm/intrinsics.h>
 103
 104 /*
 105  * Data types needed to pass information into PAL procedures and
 106  * interpret information returned by them.
 107  */
 108
 109 /* Return status from the PAL procedure */
 110 typedef s64                             pal_status_t;
 111
 112 #define PAL_STATUS_SUCCESS              0       /* No error */
 113 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
 114 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
 115 #define PAL_STATUS_ERROR                (-3)    /* Error */
 116 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
 117                                                  * specified level and type of
 118                                                  * cache without sideeffects
 119                                                  * and "restrict" was 1
 120                                                  */
 121 #define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
 122
 123 /* Processor cache level in the hierarchy */
 124 typedef u64                             pal_cache_level_t;
 125 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 126 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 127 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 128
 129
 130 /* Processor cache type at a particular level in the hierarchy */
 131
 132 typedef u64                             pal_cache_type_t;
 133 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
 134 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
 135 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
 136
 137
 138 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
 139 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
 140
 141 /* Processor cache line size in bytes  */
 142 typedef int                             pal_cache_line_size_t;
 143
 144 /* Processor cache line state */
 145 typedef u64                             pal_cache_line_state_t;
 146 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
 147 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
 148 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
 149 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
 150
 151 typedef struct pal_freq_ratio {
 152         u32 den, num;           /* numerator & denominator */
 153 } itc_ratio, proc_ratio;
 154
 155 typedef union  pal_cache_config_info_1_s {
 156         struct {
 157                 u64             u               : 1,    /* 0 Unified cache ? */
 158                                 at              : 2,    /* 2-1 Cache mem attr*/
 159                                 reserved        : 5,    /* 7-3 Reserved */
 160                                 associativity   : 8,    /* 16-8 Associativity*/
 161                                 line_size       : 8,    /* 23-17 Line size */
 162                                 stride          : 8,    /* 31-24 Stride */
 163                                 store_latency   : 8,    /*39-32 Store latency*/
 164                                 load_latency    : 8,    /* 47-40 Load latency*/
 165                                 store_hints     : 8,    /* 55-48 Store hints*/
 166                                 load_hints      : 8;    /* 63-56 Load hints */
 167         } pcci1_bits;
 168         u64                     pcci1_data;
 169 } pal_cache_config_info_1_t;
 170
 171 typedef union  pal_cache_config_info_2_s {
 172         struct {
 173                 u32             cache_size;             /*cache size in bytes*/
 174
 175
 176                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
 177                                                          * separation for max
 178                                                          * performance.
 179                                                          */
 180                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
 181                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
 182                                 reserved        : 8;    /* 63-56 Reserved */
 183         } pcci2_bits;
 184         u64                     pcci2_data;
 185 } pal_cache_config_info_2_t;
 186
 187
 188 typedef struct pal_cache_config_info_s {
 189         pal_status_t                    pcci_status;
 190         pal_cache_config_info_1_t       pcci_info_1;
 191         pal_cache_config_info_2_t       pcci_info_2;
 192         u64                             pcci_reserved;
 193 } pal_cache_config_info_t;
 194
 195 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
 196 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
 197 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
 198 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
 199 #define pcci_stride             pcci_info_1.pcci1_bits.stride
 200 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
 201 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
 202 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
 203 #define pcci_unified            pcci_info_1.pcci1_bits.u
 204 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
 205 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
 206 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
 207 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
 208
 209
 210
 211 /* Possible values for cache attributes */
 212
 213 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
 214 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
 215 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
 216                                                  * back depending on TLB
 217                                                  * memory attributes
 218                                                  */
 219
 220
 221 /* Possible values for cache hints */
 222
 223 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
 224 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
 225 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
 226
 227 /* Processor cache protection  information */
 228 typedef union pal_cache_protection_element_u {
 229         u32                     pcpi_data;
 230         struct {
 231                 u32             data_bits       : 8, /* # data bits covered by
 232                                                       * each unit of protection
 233                                                       */
 234
 235                                 tagprot_lsb     : 6, /* Least -do- */
 236                                 tagprot_msb     : 6, /* Most Sig. tag address
 237                                                       * bit that this
 238                                                       * protection covers.
 239                                                       */
 240                                 prot_bits       : 6, /* # of protection bits */
 241                                 method          : 4, /* Protection method */
 242                                 t_d             : 2; /* Indicates which part
 243                                                       * of the cache this
 244                                                       * protection encoding
 245                                                       * applies.
 246                                                       */
 247         } pcp_info;
 248 } pal_cache_protection_element_t;
 249
 250 #define pcpi_cache_prot_part    pcp_info.t_d
 251 #define pcpi_prot_method        pcp_info.method
 252 #define pcpi_prot_bits          pcp_info.prot_bits
 253 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
 254 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
 255 #define pcpi_data_bits          pcp_info.data_bits
 256
 257 /* Processor cache part encodings */
 258 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
 259 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
 260 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
 261                                                  * more significant )
 262                                                  */
 263 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
 264                                                  * more significant )
 265                                                  */
 266 #define PAL_CACHE_PROT_PART_MAX         6
 267
 268
 269 typedef struct pal_cache_protection_info_s {
 270         pal_status_t                    pcpi_status;
 271         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
 272 } pal_cache_protection_info_t;
 273
 274
 275 /* Processor cache protection method encodings */
 276 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
 277 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
 278 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
 279 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 280
 281
 282 /* Processor cache line identification in the hierarchy */
 283 typedef union pal_cache_line_id_u {
 284         u64                     pclid_data;
 285         struct {
 286                 u64             cache_type      : 8,    /* 7-0 cache type */
 287                                 level           : 8,    /* 15-8 level of the
 288                                                          * cache in the
 289                                                          * hierarchy.
 290                                                          */
 291                                 way             : 8,    /* 23-16 way in the set
 292                                                          */
 293                                 part            : 8,    /* 31-24 part of the
 294                                                          * cache
 295                                                          */
 296                                 reserved        : 32;   /* 63-32 is reserved*/
 297         } pclid_info_read;
 298         struct {
 299                 u64             cache_type      : 8,    /* 7-0 cache type */
 300                                 level           : 8,    /* 15-8 level of the
 301                                                          * cache in the
 302                                                          * hierarchy.
 303                                                          */
 304                                 way             : 8,    /* 23-16 way in the set
 305                                                          */
 306                                 part            : 8,    /* 31-24 part of the
 307                                                          * cache
 308                                                          */
 309                                 mesi            : 8,    /* 39-32 cache line
 310                                                          * state
 311                                                          */
 312                                 start           : 8,    /* 47-40 lsb of data to
 313                                                          * invert
 314                                                          */
 315                                 length          : 8,    /* 55-48 #bits to
 316                                                          * invert
 317                                                          */
 318                                 trigger         : 8;    /* 63-56 Trigger error
 319                                                          * by doing a load
 320                                                          * after the write
 321                                                          */
 322
 323         } pclid_info_write;
 324 } pal_cache_line_id_u_t;
 325
 326 #define pclid_read_part         pclid_info_read.part
 327 #define pclid_read_way          pclid_info_read.way
 328 #define pclid_read_level        pclid_info_read.level
 329 #define pclid_read_cache_type   pclid_info_read.cache_type
 330
 331 #define pclid_write_trigger     pclid_info_write.trigger
 332 #define pclid_write_length      pclid_info_write.length
 333 #define pclid_write_start       pclid_info_write.start
 334 #define pclid_write_mesi        pclid_info_write.mesi
 335 #define pclid_write_part        pclid_info_write.part
 336 #define pclid_write_way         pclid_info_write.way
 337 #define pclid_write_level       pclid_info_write.level
 338 #define pclid_write_cache_type  pclid_info_write.cache_type
 339
 340 /* Processor cache line part encodings */
 341 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
 342 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
 343 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
 344 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
 345 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
 346                                                          * protection
 347                                                          */
 348 typedef struct pal_cache_line_info_s {
 349         pal_status_t            pcli_status;            /* Return status of the read cache line
 350                                                          * info call.
 351                                                          */
 352         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
 353         u64                     pcli_data_len;          /* data length in bits */
 354         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
 355
 356 } pal_cache_line_info_t;
 357
 358
 359 /* Machine Check related crap */
 360
 361 /* Pending event status bits  */
 362 typedef u64                                     pal_mc_pending_events_t;
 363
 364 #define PAL_MC_PENDING_MCA                      (1 << 0)
 365 #define PAL_MC_PENDING_INIT                     (1 << 1)
 366
 367 /* Error information type */
 368 typedef u64                                     pal_mc_info_index_t;
 369
 370 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
 371 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
 372 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
 373 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
 374 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
 375 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
 376 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
 377 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
 378                                                          * dependent
 379                                                          */
 380
 381 #define PAL_TLB_CHECK_OP_PURGE                  8
 382
 383 typedef struct pal_process_state_info_s {
 384         u64             reserved1       : 2,
 385                         rz              : 1,    /* PAL_CHECK processor
 386                                                  * rendezvous
 387                                                  * successful.
 388                                                  */
 389
 390                         ra              : 1,    /* PAL_CHECK attempted
 391                                                  * a rendezvous.
 392                                                  */
 393                         me              : 1,    /* Distinct multiple
 394                                                  * errors occurred
 395                                                  */
 396
 397                         mn              : 1,    /* Min. state save
 398                                                  * area has been
 399                                                  * registered with PAL
 400                                                  */
 401
 402                         sy              : 1,    /* Storage integrity
 403                                                  * synched
 404                                                  */
 405
 406
 407                         co              : 1,    /* Continuable */
 408                         ci              : 1,    /* MC isolated */
 409                         us              : 1,    /* Uncontained storage
 410                                                  * damage.
 411                                                  */
 412
 413
 414                         hd              : 1,    /* Non-essential hw
 415                                                  * lost (no loss of
 416                                                  * functionality)
 417                                                  * causing the
 418                                                  * processor to run in
 419                                                  * degraded mode.
 420                                                  */
 421
 422                         tl              : 1,    /* 1 => MC occurred
 423                                                  * after an instr was
 424                                                  * executed but before
 425                                                  * the trap that
 426                                                  * resulted from instr
 427                                                  * execution was
 428                                                  * generated.
 429                                                  * (Trap Lost )
 430                                                  */
 431                         mi              : 1,    /* More information available
 432                                                  * call PAL_MC_ERROR_INFO
 433                                                  */
 434                         pi              : 1,    /* Precise instruction pointer */
 435                         pm              : 1,    /* Precise min-state save area */
 436
 437                         dy              : 1,    /* Processor dynamic
 438                                                  * state valid
 439                                                  */
 440
 441
 442                         in              : 1,    /* 0 = MC, 1 = INIT */
 443                         rs              : 1,    /* RSE valid */
 444                         cm              : 1,    /* MC corrected */
 445                         ex              : 1,    /* MC is expected */
 446                         cr              : 1,    /* Control regs valid*/
 447                         pc              : 1,    /* Perf cntrs valid */
 448                         dr              : 1,    /* Debug regs valid */
 449                         tr              : 1,    /* Translation regs
 450                                                  * valid
 451                                                  */
 452                         rr              : 1,    /* Region regs valid */
 453                         ar              : 1,    /* App regs valid */
 454                         br              : 1,    /* Branch regs valid */
 455                         pr              : 1,    /* Predicate registers
 456                                                  * valid
 457                                                  */
 458
 459                         fp              : 1,    /* fp registers valid*/
 460                         b1              : 1,    /* Preserved bank one
 461                                                  * general registers
 462                                                  * are valid
 463                                                  */
 464                         b0              : 1,    /* Preserved bank zero
 465                                                  * general registers
 466                                                  * are valid
 467                                                  */
 468                         gr              : 1,    /* General registers
 469                                                  * are valid
 470                                                  * (excl. banked regs)
 471                                                  */
 472                         dsize           : 16,   /* size of dynamic
 473                                                  * state returned
 474                                                  * by the processor
 475                                                  */
 476
 477                         se              : 1,    /* Shared error.  MCA in a
 478                                                    shared structure */
 479                         reserved2       : 10,
 480                         cc              : 1,    /* Cache check */
 481                         tc              : 1,    /* TLB check */
 482                         bc              : 1,    /* Bus check */
 483                         rc              : 1,    /* Register file check */
 484                         uc              : 1;    /* Uarch check */
 485
 486 } pal_processor_state_info_t;
 487
 488 typedef struct pal_cache_check_info_s {
 489         u64             op              : 4,    /* Type of cache
 490                                                  * operation that
 491                                                  * caused the machine
 492                                                  * check.
 493                                                  */
 494                         level           : 2,    /* Cache level */
 495                         reserved1       : 2,
 496                         dl              : 1,    /* Failure in data part
 497                                                  * of cache line
 498                                                  */
 499                         tl              : 1,    /* Failure in tag part
 500                                                  * of cache line
 501                                                  */
 502                         dc              : 1,    /* Failure in dcache */
 503                         ic              : 1,    /* Failure in icache */
 504                         mesi            : 3,    /* Cache line state */
 505                         mv              : 1,    /* mesi valid */
 506                         way             : 5,    /* Way in which the
 507                                                  * error occurred
 508                                                  */
 509                         wiv             : 1,    /* Way field valid */
 510                         reserved2       : 1,
 511                         dp              : 1,    /* Data poisoned on MBE */
 512                         reserved3       : 6,
 513                         hlth            : 2,    /* Health indicator */
 514
 515                         index           : 20,   /* Cache line index */
 516                         reserved4       : 2,
 517
 518                         is              : 1,    /* instruction set (1 == ia32) */
 519                         iv              : 1,    /* instruction set field valid */
 520                         pl              : 2,    /* privilege level */
 521                         pv              : 1,    /* privilege level field valid */
 522                         mcc             : 1,    /* Machine check corrected */
 523                         tv              : 1,    /* Target address
 524                                                  * structure is valid
 525                                                  */
 526                         rq              : 1,    /* Requester identifier
 527                                                  * structure is valid
 528                                                  */
 529                         rp              : 1,    /* Responder identifier
 530                                                  * structure is valid
 531                                                  */
 532                         pi              : 1;    /* Precise instruction pointer
 533                                                  * structure is valid
 534                                                  */
 535 } pal_cache_check_info_t;
 536
 537 typedef struct pal_tlb_check_info_s {
 538
 539         u64             tr_slot         : 8,    /* Slot# of TR where
 540                                                  * error occurred
 541                                                  */
 542                         trv             : 1,    /* tr_slot field is valid */
 543                         reserved1       : 1,
 544                         level           : 2,    /* TLB level where failure occurred */
 545                         reserved2       : 4,
 546                         dtr             : 1,    /* Fail in data TR */
 547                         itr             : 1,    /* Fail in inst TR */
 548                         dtc             : 1,    /* Fail in data TC */
 549                         itc             : 1,    /* Fail in inst. TC */
 550                         op              : 4,    /* Cache operation */
 551                         reserved3       : 6,
 552                         hlth            : 2,    /* Health indicator */
 553                         reserved4       : 22,
 554
 555                         is              : 1,    /* instruction set (1 == ia32) */
 556                         iv              : 1,    /* instruction set field valid */
 557                         pl              : 2,    /* privilege level */
 558                         pv              : 1,    /* privilege level field valid */
 559                         mcc             : 1,    /* Machine check corrected */
 560                         tv              : 1,    /* Target address
 561                                                  * structure is valid
 562                                                  */
 563                         rq              : 1,    /* Requester identifier
 564                                                  * structure is valid
 565                                                  */
 566                         rp              : 1,    /* Responder identifier
 567                                                  * structure is valid
 568                                                  */
 569                         pi              : 1;    /* Precise instruction pointer
 570                                                  * structure is valid
 571                                                  */
 572 } pal_tlb_check_info_t;
 573
 574 typedef struct pal_bus_check_info_s {
 575         u64             size            : 5,    /* Xaction size */
 576                         ib              : 1,    /* Internal bus error */
 577                         eb              : 1,    /* External bus error */
 578                         cc              : 1,    /* Error occurred
 579                                                  * during cache-cache
 580                                                  * transfer.
 581                                                  */
 582                         type            : 8,    /* Bus xaction type*/
 583                         sev             : 5,    /* Bus error severity*/
 584                         hier            : 2,    /* Bus hierarchy level */
 585                         dp              : 1,    /* Data poisoned on MBE */
 586                         bsi             : 8,    /* Bus error status
 587                                                  * info
 588                                                  */
 589                         reserved2       : 22,
 590
 591                         is              : 1,    /* instruction set (1 == ia32) */
 592                         iv              : 1,    /* instruction set field valid */
 593                         pl              : 2,    /* privilege level */
 594                         pv              : 1,    /* privilege level field valid */
 595                         mcc             : 1,    /* Machine check corrected */
 596                         tv              : 1,    /* Target address
 597                                                  * structure is valid
 598                                                  */
 599                         rq              : 1,    /* Requester identifier
 600                                                  * structure is valid
 601                                                  */
 602                         rp              : 1,    /* Responder identifier
 603                                                  * structure is valid
 604                                                  */
 605                         pi              : 1;    /* Precise instruction pointer
 606                                                  * structure is valid
 607                                                  */
 608 } pal_bus_check_info_t;
 609
 610 typedef struct pal_reg_file_check_info_s {
 611         u64             id              : 4,    /* Register file identifier */
 612                         op              : 4,    /* Type of register
 613                                                  * operation that
 614                                                  * caused the machine
 615                                                  * check.
 616                                                  */
 617                         reg_num         : 7,    /* Register number */
 618                         rnv             : 1,    /* reg_num valid */
 619                         reserved2       : 38,
 620
 621                         is              : 1,    /* instruction set (1 == ia32) */
 622                         iv              : 1,    /* instruction set field valid */
 623                         pl              : 2,    /* privilege level */
 624                         pv              : 1,    /* privilege level field valid */
 625                         mcc             : 1,    /* Machine check corrected */
 626                         reserved3       : 3,
 627                         pi              : 1;    /* Precise instruction pointer
 628                                                  * structure is valid
 629                                                  */
 630 } pal_reg_file_check_info_t;
 631
 632 typedef struct pal_uarch_check_info_s {
 633         u64             sid             : 5,    /* Structure identification */
 634                         level           : 3,    /* Level of failure */
 635                         array_id        : 4,    /* Array identification */
 636                         op              : 4,    /* Type of
 637                                                  * operation that
 638                                                  * caused the machine
 639                                                  * check.
 640                                                  */
 641                         way             : 6,    /* Way of structure */
 642                         wv              : 1,    /* way valid */
 643                         xv              : 1,    /* index valid */
 644                         reserved1       : 6,
 645                         hlth            : 2,    /* Health indicator */
 646                         index           : 8,    /* Index or set of the uarch
 647                                                  * structure that failed.
 648                                                  */
 649                         reserved2       : 24,
 650
 651                         is              : 1,    /* instruction set (1 == ia32) */
 652                         iv              : 1,    /* instruction set field valid */
 653                         pl              : 2,    /* privilege level */
 654                         pv              : 1,    /* privilege level field valid */
 655                         mcc             : 1,    /* Machine check corrected */
 656                         tv              : 1,    /* Target address
 657                                                  * structure is valid
 658                                                  */
 659                         rq              : 1,    /* Requester identifier
 660                                                  * structure is valid
 661                                                  */
 662                         rp              : 1,    /* Responder identifier
 663                                                  * structure is valid
 664                                                  */
 665                         pi              : 1;    /* Precise instruction pointer
 666                                                  * structure is valid
 667                                                  */
 668 } pal_uarch_check_info_t;
 669
 670 typedef union pal_mc_error_info_u {
 671         u64                             pmei_data;
 672         pal_processor_state_info_t      pme_processor;
 673         pal_cache_check_info_t          pme_cache;
 674         pal_tlb_check_info_t            pme_tlb;
 675         pal_bus_check_info_t            pme_bus;
 676         pal_reg_file_check_info_t       pme_reg_file;
 677         pal_uarch_check_info_t          pme_uarch;
 678 } pal_mc_error_info_t;
 679
 680 #define pmci_proc_unknown_check                 pme_processor.uc
 681 #define pmci_proc_bus_check                     pme_processor.bc
 682 #define pmci_proc_tlb_check                     pme_processor.tc
 683 #define pmci_proc_cache_check                   pme_processor.cc
 684 #define pmci_proc_dynamic_state_size            pme_processor.dsize
 685 #define pmci_proc_gpr_valid                     pme_processor.gr
 686 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
 687 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
 688 #define pmci_proc_fp_valid                      pme_processor.fp
 689 #define pmci_proc_predicate_regs_valid          pme_processor.pr
 690 #define pmci_proc_branch_regs_valid             pme_processor.br
 691 #define pmci_proc_app_regs_valid                pme_processor.ar
 692 #define pmci_proc_region_regs_valid             pme_processor.rr
 693 #define pmci_proc_translation_regs_valid        pme_processor.tr
 694 #define pmci_proc_debug_regs_valid              pme_processor.dr
 695 #define pmci_proc_perf_counters_valid           pme_processor.pc
 696 #define pmci_proc_control_regs_valid            pme_processor.cr
 697 #define pmci_proc_machine_check_expected        pme_processor.ex
 698 #define pmci_proc_machine_check_corrected       pme_processor.cm
 699 #define pmci_proc_rse_valid                     pme_processor.rs
 700 #define pmci_proc_machine_check_or_init         pme_processor.in
 701 #define pmci_proc_dynamic_state_valid           pme_processor.dy
 702 #define pmci_proc_operation                     pme_processor.op
 703 #define pmci_proc_trap_lost                     pme_processor.tl
 704 #define pmci_proc_hardware_damage               pme_processor.hd
 705 #define pmci_proc_uncontained_storage_damage    pme_processor.us
 706 #define pmci_proc_machine_check_isolated        pme_processor.ci
 707 #define pmci_proc_continuable                   pme_processor.co
 708 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
 709 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
 710 #define pmci_proc_distinct_multiple_errors      pme_processor.me
 711 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
 712 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
 713
 714
 715 #define pmci_cache_level                        pme_cache.level
 716 #define pmci_cache_line_state                   pme_cache.mesi
 717 #define pmci_cache_line_state_valid             pme_cache.mv
 718 #define pmci_cache_line_index                   pme_cache.index
 719 #define pmci_cache_instr_cache_fail             pme_cache.ic
 720 #define pmci_cache_data_cache_fail              pme_cache.dc
 721 #define pmci_cache_line_tag_fail                pme_cache.tl
 722 #define pmci_cache_line_data_fail               pme_cache.dl
 723 #define pmci_cache_operation                    pme_cache.op
 724 #define pmci_cache_way_valid                    pme_cache.wv
 725 #define pmci_cache_target_address_valid         pme_cache.tv
 726 #define pmci_cache_way                          pme_cache.way
 727 #define pmci_cache_mc                           pme_cache.mc
 728
 729 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
 730 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
 731 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
 732 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
 733 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
 734 #define pmci_tlb_mc                             pme_tlb.mc
 735
 736 #define pmci_bus_status_info                    pme_bus.bsi
 737 #define pmci_bus_req_address_valid              pme_bus.rq
 738 #define pmci_bus_resp_address_valid             pme_bus.rp
 739 #define pmci_bus_target_address_valid           pme_bus.tv
 740 #define pmci_bus_error_severity                 pme_bus.sev
 741 #define pmci_bus_transaction_type               pme_bus.type
 742 #define pmci_bus_cache_cache_transfer           pme_bus.cc
 743 #define pmci_bus_transaction_size               pme_bus.size
 744 #define pmci_bus_internal_error                 pme_bus.ib
 745 #define pmci_bus_external_error                 pme_bus.eb
 746 #define pmci_bus_mc                             pme_bus.mc
 747
 748 /*
 749  * NOTE: this min_state_save area struct only includes the 1KB
 750  * architectural state save area.  The other 3 KB is scratch space
 751  * for PAL.
 752  */
 753
 754 struct pal_min_state_area {
 755         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
 756         u64     pmsa_gr[15];            /* GR1  - GR15             */
 757         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
 758         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
 759         u64     pmsa_pr;                /* predicate registers     */
 760         u64     pmsa_br0;               /* branch register 0       */
 761         u64     pmsa_rsc;               /* ar.rsc                  */
 762         u64     pmsa_iip;               /* cr.iip                  */
 763         u64     pmsa_ipsr;              /* cr.ipsr                 */
 764         u64     pmsa_ifs;               /* cr.ifs                  */
 765         u64     pmsa_xip;               /* previous iip            */
 766         u64     pmsa_xpsr;              /* previous psr            */
 767         u64     pmsa_xfs;               /* previous ifs            */
 768         u64     pmsa_br1;               /* branch register 1       */
 769         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
 770 };
 771
 772
 773 struct ia64_pal_retval {
 774         /*
 775          * A zero status value indicates call completed without error.
 776          * A negative status value indicates reason of call failure.
 777          * A positive status value indicates success but an
 778          * informational value should be printed (e.g., "reboot for
 779          * change to take effect").
 780          */
 781         s64 status;
 782         u64 v0;
 783         u64 v1;
 784         u64 v2;
 785 };
 786
 787 /*
 788  * Note: Currently unused PAL arguments are generally labeled
 789  * "reserved" so the value specified in the PAL documentation
 790  * (generally 0) MUST be passed.  Reserved parameters are not optional
 791  * parameters.
 792  */
 793 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
 794 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 795 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 796 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
 797 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
 798 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 799
 800 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
 801         struct ia64_fpreg fr[6];                        \
 802         ia64_save_scratch_fpregs(fr);                   \
 803         iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
 804         ia64_load_scratch_fpregs(fr);                   \
 805 } while (0)
 806
 807 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
 808         struct ia64_fpreg fr[6];                        \
 809         ia64_save_scratch_fpregs(fr);                   \
 810         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
 811         ia64_load_scratch_fpregs(fr);                   \
 812 } while (0)
 813
 814 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
 815         struct ia64_fpreg fr[6];                                \
 816         ia64_save_scratch_fpregs(fr);                           \
 817         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
 818         ia64_load_scratch_fpregs(fr);                           \
 819 } while (0)
 820
 821 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
 822         struct ia64_fpreg fr[6];                                \
 823         ia64_save_scratch_fpregs(fr);                           \
 824         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
 825         ia64_load_scratch_fpregs(fr);                           \
 826 } while (0)
 827
 828 typedef int (*ia64_pal_handler) (u64, ...);
 829 extern ia64_pal_handler ia64_pal;
 830 extern void ia64_pal_handler_init (void *);
 831
 832 extern ia64_pal_handler ia64_pal;
 833
 834 extern pal_cache_config_info_t          l0d_cache_config_info;
 835 extern pal_cache_config_info_t          l0i_cache_config_info;
 836 extern pal_cache_config_info_t          l1_cache_config_info;
 837 extern pal_cache_config_info_t          l2_cache_config_info;
 838
 839 extern pal_cache_protection_info_t      l0d_cache_protection_info;
 840 extern pal_cache_protection_info_t      l0i_cache_protection_info;
 841 extern pal_cache_protection_info_t      l1_cache_protection_info;
 842 extern pal_cache_protection_info_t      l2_cache_protection_info;
 843
 844 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
 845                                                                   pal_cache_type_t);
 846
 847 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
 848                                                                       pal_cache_type_t);
 849
 850
 851 extern void                             pal_error(int);
 852
 853
 854 /* Useful wrappers for the current list of pal procedures */
 855
 856 typedef union pal_bus_features_u {
 857         u64     pal_bus_features_val;
 858         struct {
 859                 u64     pbf_reserved1                           :       29;
 860                 u64     pbf_req_bus_parking                     :       1;
 861                 u64     pbf_bus_lock_mask                       :       1;
 862                 u64     pbf_enable_half_xfer_rate               :       1;
 863                 u64     pbf_reserved2                           :       20;
 864                 u64     pbf_enable_shared_line_replace          :       1;
 865                 u64     pbf_enable_exclusive_line_replace       :       1;
 866                 u64     pbf_disable_xaction_queueing            :       1;
 867                 u64     pbf_disable_resp_err_check              :       1;
 868                 u64     pbf_disable_berr_check                  :       1;
 869                 u64     pbf_disable_bus_req_internal_err_signal :       1;
 870                 u64     pbf_disable_bus_req_berr_signal         :       1;
 871                 u64     pbf_disable_bus_init_event_check        :       1;
 872                 u64     pbf_disable_bus_init_event_signal       :       1;
 873                 u64     pbf_disable_bus_addr_err_check          :       1;
 874                 u64     pbf_disable_bus_addr_err_signal         :       1;
 875                 u64     pbf_disable_bus_data_err_check          :       1;
 876         } pal_bus_features_s;
 877 } pal_bus_features_u_t;
 878
 879 extern void pal_bus_features_print (u64);
 880
 881 /* Provide information about configurable processor bus features */
 882 static inline s64
 883 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
 884                            pal_bus_features_u_t *features_status,
 885                            pal_bus_features_u_t *features_control)
 886 {
 887         struct ia64_pal_retval iprv;
 888         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
 889         if (features_avail)
 890                 features_avail->pal_bus_features_val = iprv.v0;
 891         if (features_status)
 892                 features_status->pal_bus_features_val = iprv.v1;
 893         if (features_control)
 894                 features_control->pal_bus_features_val = iprv.v2;
 895         return iprv.status;
 896 }
 897
 898 /* Enables/disables specific processor bus features */
 899 static inline s64
 900 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
 901 {
 902         struct ia64_pal_retval iprv;
 903         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
 904         return iprv.status;
 905 }
 906
 907 /* Get detailed cache information */
 908 static inline s64
 909 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
 910 {
 911         struct ia64_pal_retval iprv;
 912
 913         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
 914
 915         if (iprv.status == 0) {
 916                 conf->pcci_status                 = iprv.status;
 917                 conf->pcci_info_1.pcci1_data      = iprv.v0;
 918                 conf->pcci_info_2.pcci2_data      = iprv.v1;
 919                 conf->pcci_reserved               = iprv.v2;
 920         }
 921         return iprv.status;
 922
 923 }
 924
 925 /* Get detailed cche protection information */
 926 static inline s64
 927 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
 928 {
 929         struct ia64_pal_retval iprv;
 930
 931         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
 932
 933         if (iprv.status == 0) {
 934                 prot->pcpi_status           = iprv.status;
 935                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
 936                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
 937                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
 938                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
 939                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
 940                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
 941         }
 942         return iprv.status;
 943 }
 944
 945 /*
 946  * Flush the processor instruction or data caches.  *PROGRESS must be
 947  * initialized to zero before calling this for the first time..
 948  */
 949 static inline s64
 950 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 951 {
 952         struct ia64_pal_retval iprv;
 953         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 954         if (vector)
 955                 *vector = iprv.v0;
 956         *progress = iprv.v1;
 957         return iprv.status;
 958 }
 959
 960
 961 /* Initialize the processor controlled caches */
 962 static inline s64
 963 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
 964 {
 965         struct ia64_pal_retval iprv;
 966         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
 967         return iprv.status;
 968 }
 969
 970 /* Initialize the tags and data of a data or unified cache line of
 971  * processor controlled cache to known values without the availability
 972  * of backing memory.
 973  */
 974 static inline s64
 975 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
 976 {
 977         struct ia64_pal_retval iprv;
 978         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
 979         return iprv.status;
 980 }
 981
 982
 983 /* Read the data and tag of a processor controlled cache line for diags */
 984 static inline s64
 985 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 986 {
 987         struct ia64_pal_retval iprv;
 988         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
 989                                 physical_addr, 0);
 990         return iprv.status;
 991 }
 992
 993 /* Return summary information about the hierarchy of caches controlled by the processor */
 994 static inline long ia64_pal_cache_summary(unsigned long *cache_levels,
 995                                                 unsigned long *unique_caches)
 996 {
 997         struct ia64_pal_retval iprv;
 998         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
 999         if (cache_levels)
1000                 *cache_levels = iprv.v0;
1001         if (unique_caches)
1002                 *unique_caches = iprv.v1;
1003         return iprv.status;
1004 }
1005
1006 /* Write the data and tag of a processor-controlled cache line for diags */
1007 static inline s64
1008 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
1009 {
1010         struct ia64_pal_retval iprv;
1011         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1012                                 physical_addr, data);
1013         return iprv.status;
1014 }
1015
1016
1017 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1018 static inline s64
1019 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1020                     u64 *buffer_size, u64 *buffer_align)
1021 {
1022         struct ia64_pal_retval iprv;
1023         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1024         if (buffer_size)
1025                 *buffer_size = iprv.v0;
1026         if (buffer_align)
1027                 *buffer_align = iprv.v1;
1028         return iprv.status;
1029 }
1030
1031 /* Copy relocatable PAL procedures from ROM to memory */
1032 static inline s64
1033 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1034 {
1035         struct ia64_pal_retval iprv;
1036         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1037         if (pal_proc_offset)
1038                 *pal_proc_offset = iprv.v0;
1039         return iprv.status;
1040 }
1041
1042 /* Return the number of instruction and data debug register pairs */
1043 static inline long ia64_pal_debug_info(unsigned long *inst_regs,
1044                                                 unsigned long *data_regs)
1045 {
1046         struct ia64_pal_retval iprv;
1047         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1048         if (inst_regs)
1049                 *inst_regs = iprv.v0;
1050         if (data_regs)
1051                 *data_regs = iprv.v1;
1052
1053         return iprv.status;
1054 }
1055
1056 #ifdef TBD
1057 /* Switch from IA64-system environment to IA-32 system environment */
1058 static inline s64
1059 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1060 {
1061         struct ia64_pal_retval iprv;
1062         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1063         return iprv.status;
1064 }
1065 #endif
1066
1067 /* Get unique geographical address of this processor on its bus */
1068 static inline s64
1069 ia64_pal_fixed_addr (u64 *global_unique_addr)
1070 {
1071         struct ia64_pal_retval iprv;
1072         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1073         if (global_unique_addr)
1074                 *global_unique_addr = iprv.v0;
1075         return iprv.status;
1076 }
1077
1078 /* Get base frequency of the platform if generated by the processor */
1079 static inline long ia64_pal_freq_base(unsigned long *platform_base_freq)
1080 {
1081         struct ia64_pal_retval iprv;
1082         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1083         if (platform_base_freq)
1084                 *platform_base_freq = iprv.v0;
1085         return iprv.status;
1086 }
1087
1088 /*
1089  * Get the ratios for processor frequency, bus frequency and interval timer to
1090  * the base frequency of the platform
1091  */
1092 static inline s64
1093 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1094                       struct pal_freq_ratio *itc_ratio)
1095 {
1096         struct ia64_pal_retval iprv;
1097         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1098         if (proc_ratio)
1099                 *(u64 *)proc_ratio = iprv.v0;
1100         if (bus_ratio)
1101                 *(u64 *)bus_ratio = iprv.v1;
1102         if (itc_ratio)
1103                 *(u64 *)itc_ratio = iprv.v2;
1104         return iprv.status;
1105 }
1106
1107 /*
1108  * Get the current hardware resource sharing policy of the processor
1109  */
1110 static inline s64
1111 ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1112                         u64 *la)
1113 {
1114         struct ia64_pal_retval iprv;
1115         PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1116         if (cur_policy)
1117                 *cur_policy = iprv.v0;
1118         if (num_impacted)
1119                 *num_impacted = iprv.v1;
1120         if (la)
1121                 *la = iprv.v2;
1122         return iprv.status;
1123 }
1124
1125 /* Make the processor enter HALT or one of the implementation dependent low
1126  * power states where prefetching and execution are suspended and cache and
1127  * TLB coherency is not maintained.
1128  */
1129 static inline s64
1130 ia64_pal_halt (u64 halt_state)
1131 {
1132         struct ia64_pal_retval iprv;
1133         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1134         return iprv.status;
1135 }
1136
1137 typedef union pal_power_mgmt_info_u {
1138         u64                     ppmi_data;
1139         struct {
1140                u64              exit_latency            : 16,
1141                                 entry_latency           : 16,
1142                                 power_consumption       : 28,
1143                                 im                      : 1,
1144                                 co                      : 1,
1145                                 reserved                : 2;
1146         } pal_power_mgmt_info_s;
1147 } pal_power_mgmt_info_u_t;
1148
1149 /* Return information about processor's optional power management capabilities. */
1150 static inline s64
1151 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1152 {
1153         struct ia64_pal_retval iprv;
1154         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1155         return iprv.status;
1156 }
1157
1158 /* Get the current P-state information */
1159 static inline s64
1160 ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1161 {
1162         struct ia64_pal_retval iprv;
1163         PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1164         *pstate_index = iprv.v0;
1165         return iprv.status;
1166 }
1167
1168 /* Set the P-state */
1169 static inline s64
1170 ia64_pal_set_pstate (u64 pstate_index)
1171 {
1172         struct ia64_pal_retval iprv;
1173         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1174         return iprv.status;
1175 }
1176
1177 /* Processor branding information*/
1178 static inline s64
1179 ia64_pal_get_brand_info (char *brand_info)
1180 {
1181         struct ia64_pal_retval iprv;
1182         PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1183         return iprv.status;
1184 }
1185
1186 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1187  * suspended, but cache and TLB coherency is maintained.
1188  */
1189 static inline s64
1190 ia64_pal_halt_light (void)
1191 {
1192         struct ia64_pal_retval iprv;
1193         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1194         return iprv.status;
1195 }
1196
1197 /* Clear all the processor error logging   registers and reset the indicator that allows
1198  * the error logging registers to be written. This procedure also checks the pending
1199  * machine check bit and pending INIT bit and reports their states.
1200  */
1201 static inline s64
1202 ia64_pal_mc_clear_log (u64 *pending_vector)
1203 {
1204         struct ia64_pal_retval iprv;
1205         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1206         if (pending_vector)
1207                 *pending_vector = iprv.v0;
1208         return iprv.status;
1209 }
1210
1211 /* Ensure that all outstanding transactions in a processor are completed or that any
1212  * MCA due to thes outstanding transaction is taken.
1213  */
1214 static inline s64
1215 ia64_pal_mc_drain (void)
1216 {
1217         struct ia64_pal_retval iprv;
1218         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1219         return iprv.status;
1220 }
1221
1222 /* Return the machine check dynamic processor state */
1223 static inline s64
1224 ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
1225 {
1226         struct ia64_pal_retval iprv;
1227         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
1228         if (size)
1229                 *size = iprv.v0;
1230         return iprv.status;
1231 }
1232
1233 /* Return processor machine check information */
1234 static inline s64
1235 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1236 {
1237         struct ia64_pal_retval iprv;
1238         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1239         if (size)
1240                 *size = iprv.v0;
1241         if (error_info)
1242                 *error_info = iprv.v1;
1243         return iprv.status;
1244 }
1245
1246 /* Injects the requested processor error or returns info on
1247  * supported injection capabilities for current processor implementation
1248  */
1249 static inline s64
1250 ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
1251                         u64 err_data_buffer, u64 *capabilities, u64 *resources)
1252 {
1253         struct ia64_pal_retval iprv;
1254         PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1255                           err_struct_info, err_data_buffer);
1256         if (capabilities)
1257                 *capabilities= iprv.v0;
1258         if (resources)
1259                 *resources= iprv.v1;
1260         return iprv.status;
1261 }
1262
1263 static inline s64
1264 ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
1265                         u64 err_data_buffer, u64 *capabilities, u64 *resources)
1266 {
1267         struct ia64_pal_retval iprv;
1268         PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1269                           err_struct_info, err_data_buffer);
1270         if (capabilities)
1271                 *capabilities= iprv.v0;
1272         if (resources)
1273                 *resources= iprv.v1;
1274         return iprv.status;
1275 }
1276
1277 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1278  * attempt to correct any expected machine checks.
1279  */
1280 static inline s64
1281 ia64_pal_mc_expected (u64 expected, u64 *previous)
1282 {
1283         struct ia64_pal_retval iprv;
1284         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1285         if (previous)
1286                 *previous = iprv.v0;
1287         return iprv.status;
1288 }
1289
1290 typedef union pal_hw_tracking_u {
1291         u64                     pht_data;
1292         struct {
1293                 u64             itc     :4,     /* Instruction cache tracking */
1294                                 dct     :4,     /* Date cache tracking */
1295                                 itt     :4,     /* Instruction TLB tracking */
1296                                 ddt     :4,     /* Data TLB tracking */
1297                                 reserved:48;
1298         } pal_hw_tracking_s;
1299 } pal_hw_tracking_u_t;
1300
1301 /*
1302  * Hardware tracking status.
1303  */
1304 static inline s64
1305 ia64_pal_mc_hw_tracking (u64 *status)
1306 {
1307         struct ia64_pal_retval iprv;
1308         PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
1309         if (status)
1310                 *status = iprv.v0;
1311         return iprv.status;
1312 }
1313
1314 /* Register a platform dependent location with PAL to which it can save
1315  * minimal processor state in the event of a machine check or initialization
1316  * event.
1317  */
1318 static inline s64
1319 ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
1320 {
1321         struct ia64_pal_retval iprv;
1322         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
1323         if (req_size)
1324                 *req_size = iprv.v0;
1325         return iprv.status;
1326 }
1327
1328 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1329  * and resume execution
1330  */
1331 static inline s64
1332 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1333 {
1334         struct ia64_pal_retval iprv;
1335         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1336         return iprv.status;
1337 }
1338
1339 /* Return the memory attributes implemented by the processor */
1340 static inline s64
1341 ia64_pal_mem_attrib (u64 *mem_attrib)
1342 {
1343         struct ia64_pal_retval iprv;
1344         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1345         if (mem_attrib)
1346                 *mem_attrib = iprv.v0 & 0xff;
1347         return iprv.status;
1348 }
1349
1350 /* Return the amount of memory needed for second phase of processor
1351  * self-test and the required alignment of memory.
1352  */
1353 static inline s64
1354 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1355 {
1356         struct ia64_pal_retval iprv;
1357         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1358         if (bytes_needed)
1359                 *bytes_needed = iprv.v0;
1360         if (alignment)
1361                 *alignment = iprv.v1;
1362         return iprv.status;
1363 }
1364
1365 typedef union pal_perf_mon_info_u {
1366         u64                       ppmi_data;
1367         struct {
1368                u64              generic         : 8,
1369                                 width           : 8,
1370                                 cycles          : 8,
1371                                 retired         : 8,
1372                                 reserved        : 32;
1373         } pal_perf_mon_info_s;
1374 } pal_perf_mon_info_u_t;
1375
1376 /* Return the performance monitor information about what can be counted
1377  * and how to configure the monitors to count the desired events.
1378  */
1379 static inline s64
1380 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1381 {
1382         struct ia64_pal_retval iprv;
1383         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1384         if (pm_info)
1385                 pm_info->ppmi_data = iprv.v0;
1386         return iprv.status;
1387 }
1388
1389 /* Specifies the physical address of the processor interrupt block
1390  * and I/O port space.
1391  */
1392 static inline s64
1393 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1394 {
1395         struct ia64_pal_retval iprv;
1396         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1397         return iprv.status;
1398 }
1399
1400 /* Set the SAL PMI entrypoint in memory */
1401 static inline s64
1402 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1403 {
1404         struct ia64_pal_retval iprv;
1405         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1406         return iprv.status;
1407 }
1408
1409 struct pal_features_s;
1410 /* Provide information about configurable processor features */
1411 static inline s64
1412 ia64_pal_proc_get_features (u64 *features_avail,
1413                             u64 *features_status,
1414                             u64 *features_control,
1415                             u64 features_set)
1416 {
1417         struct ia64_pal_retval iprv;
1418         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0);
1419         if (iprv.status == 0) {
1420                 *features_avail   = iprv.v0;
1421                 *features_status  = iprv.v1;
1422                 *features_control = iprv.v2;
1423         }
1424         return iprv.status;
1425 }
1426
1427 /* Enable/disable processor dependent features */
1428 static inline s64
1429 ia64_pal_proc_set_features (u64 feature_select)
1430 {
1431         struct ia64_pal_retval iprv;
1432         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1433         return iprv.status;
1434 }
1435
1436 /*
1437  * Put everything in a struct so we avoid the global offset table whenever
1438  * possible.
1439  */
1440 typedef struct ia64_ptce_info_s {
1441         unsigned long   base;
1442         u32             count[2];
1443         u32             stride[2];
1444 } ia64_ptce_info_t;
1445
1446 /* Return the information required for the architected loop used to purge
1447  * (initialize) the entire TC
1448  */
1449 static inline s64
1450 ia64_get_ptce (ia64_ptce_info_t *ptce)
1451 {
1452         struct ia64_pal_retval iprv;
1453
1454         if (!ptce)
1455                 return -1;
1456
1457         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1458         if (iprv.status == 0) {
1459                 ptce->base = iprv.v0;
1460                 ptce->count[0] = iprv.v1 >> 32;
1461                 ptce->count[1] = iprv.v1 & 0xffffffff;
1462                 ptce->stride[0] = iprv.v2 >> 32;
1463                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1464         }
1465         return iprv.status;
1466 }
1467
1468 /* Return info about implemented application and control registers. */
1469 static inline s64
1470 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1471 {
1472         struct ia64_pal_retval iprv;
1473         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1474         if (reg_info_1)
1475                 *reg_info_1 = iprv.v0;
1476         if (reg_info_2)
1477                 *reg_info_2 = iprv.v1;
1478         return iprv.status;
1479 }
1480
1481 typedef union pal_hints_u {
1482         unsigned long           ph_data;
1483         struct {
1484                unsigned long    si              : 1,
1485                                 li              : 1,
1486                                 reserved        : 62;
1487         } pal_hints_s;
1488 } pal_hints_u_t;
1489
1490 /* Return information about the register stack and RSE for this processor
1491  * implementation.
1492  */
1493 static inline long ia64_pal_rse_info(unsigned long *num_phys_stacked,
1494                                                         pal_hints_u_t *hints)
1495 {
1496         struct ia64_pal_retval iprv;
1497         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1498         if (num_phys_stacked)
1499                 *num_phys_stacked = iprv.v0;
1500         if (hints)
1501                 hints->ph_data = iprv.v1;
1502         return iprv.status;
1503 }
1504
1505 /*
1506  * Set the current hardware resource sharing policy of the processor
1507  */
1508 static inline s64
1509 ia64_pal_set_hw_policy (u64 policy)
1510 {
1511         struct ia64_pal_retval iprv;
1512         PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1513         return iprv.status;
1514 }
1515
1516 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1517  * suspended, but cause cache and TLB coherency to be maintained.
1518  * This is usually called in IA-32 mode.
1519  */
1520 static inline s64
1521 ia64_pal_shutdown (void)
1522 {
1523         struct ia64_pal_retval iprv;
1524         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1525         return iprv.status;
1526 }
1527
1528 /* Perform the second phase of processor self-test. */
1529 static inline s64
1530 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1531 {
1532         struct ia64_pal_retval iprv;
1533         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1534         if (self_test_state)
1535                 *self_test_state = iprv.v0;
1536         return iprv.status;
1537 }
1538
1539 typedef union  pal_version_u {
1540         u64     pal_version_val;
1541         struct {
1542                 u64     pv_pal_b_rev            :       8;
1543                 u64     pv_pal_b_model          :       8;
1544                 u64     pv_reserved1            :       8;
1545                 u64     pv_pal_vendor           :       8;
1546                 u64     pv_pal_a_rev            :       8;
1547                 u64     pv_pal_a_model          :       8;
1548                 u64     pv_reserved2            :       16;
1549         } pal_version_s;
1550 } pal_version_u_t;
1551
1552
1553 /*
1554  * Return PAL version information.  While the documentation states that
1555  * PAL_VERSION can be called in either physical or virtual mode, some
1556  * implementations only allow physical calls.  We don't call it very often,
1557  * so the overhead isn't worth eliminating.
1558  */
1559 static inline s64
1560 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1561 {
1562         struct ia64_pal_retval iprv;
1563         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1564         if (pal_min_version)
1565                 pal_min_version->pal_version_val = iprv.v0;
1566
1567         if (pal_cur_version)
1568                 pal_cur_version->pal_version_val = iprv.v1;
1569
1570         return iprv.status;
1571 }
1572
1573 typedef union pal_tc_info_u {
1574         u64                     pti_val;
1575         struct {
1576                u64              num_sets        :       8,
1577                                 associativity   :       8,
1578                                 num_entries     :       16,
1579                                 pf              :       1,
1580                                 unified         :       1,
1581                                 reduce_tr       :       1,
1582                                 reserved        :       29;
1583         } pal_tc_info_s;
1584 } pal_tc_info_u_t;
1585
1586 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1587 #define tc_unified              pal_tc_info_s.unified
1588 #define tc_pf                   pal_tc_info_s.pf
1589 #define tc_num_entries          pal_tc_info_s.num_entries
1590 #define tc_associativity        pal_tc_info_s.associativity
1591 #define tc_num_sets             pal_tc_info_s.num_sets
1592
1593
1594 /* Return information about the virtual memory characteristics of the processor
1595  * implementation.
1596  */
1597 static inline s64
1598 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1599 {
1600         struct ia64_pal_retval iprv;
1601         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1602         if (tc_info)
1603                 tc_info->pti_val = iprv.v0;
1604         if (tc_pages)
1605                 *tc_pages = iprv.v1;
1606         return iprv.status;
1607 }
1608
1609 /* Get page size information about the virtual memory characteristics of the processor
1610  * implementation.
1611  */
1612 static inline s64 ia64_pal_vm_page_size(u64 *tr_pages, u64 *vw_pages)
1613 {
1614         struct ia64_pal_retval iprv;
1615         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1616         if (tr_pages)
1617                 *tr_pages = iprv.v0;
1618         if (vw_pages)
1619                 *vw_pages = iprv.v1;
1620         return iprv.status;
1621 }
1622
1623 typedef union pal_vm_info_1_u {
1624         u64                     pvi1_val;
1625         struct {
1626                 u64             vw              : 1,
1627                                 phys_add_size   : 7,
1628                                 key_size        : 8,
1629                                 max_pkr         : 8,
1630                                 hash_tag_id     : 8,
1631                                 max_dtr_entry   : 8,
1632                                 max_itr_entry   : 8,
1633                                 max_unique_tcs  : 8,
1634                                 num_tc_levels   : 8;
1635         } pal_vm_info_1_s;
1636 } pal_vm_info_1_u_t;
1637
1638 #define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
1639
1640 typedef union pal_vm_info_2_u {
1641         u64                     pvi2_val;
1642         struct {
1643                 u64             impl_va_msb     : 8,
1644                                 rid_size        : 8,
1645                                 max_purges      : 16,
1646                                 reserved        : 32;
1647         } pal_vm_info_2_s;
1648 } pal_vm_info_2_u_t;
1649
1650 /* Get summary information about the virtual memory characteristics of the processor
1651  * implementation.
1652  */
1653 static inline s64
1654 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1655 {
1656         struct ia64_pal_retval iprv;
1657         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1658         if (vm_info_1)
1659                 vm_info_1->pvi1_val = iprv.v0;
1660         if (vm_info_2)
1661                 vm_info_2->pvi2_val = iprv.v1;
1662         return iprv.status;
1663 }
1664
1665 typedef union pal_vp_info_u {
1666         u64                     pvi_val;
1667         struct {
1668                 u64             index:          48,     /* virtual feature set info */
1669                                 vmm_id:         16;     /* feature set id */
1670         } pal_vp_info_s;
1671 } pal_vp_info_u_t;
1672
1673 /*
1674  * Returns information about virtual processor features
1675  */
1676 static inline s64
1677 ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
1678 {
1679         struct ia64_pal_retval iprv;
1680         PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
1681         if (vp_info)
1682                 *vp_info = iprv.v0;
1683         if (vmm_id)
1684                 *vmm_id = iprv.v1;
1685         return iprv.status;
1686 }
1687
1688 typedef union pal_itr_valid_u {
1689         u64                     piv_val;
1690         struct {
1691                u64              access_rights_valid     : 1,
1692                                 priv_level_valid        : 1,
1693                                 dirty_bit_valid         : 1,
1694                                 mem_attr_valid          : 1,
1695                                 reserved                : 60;
1696         } pal_tr_valid_s;
1697 } pal_tr_valid_u_t;
1698
1699 /* Read a translation register */
1700 static inline s64
1701 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1702 {
1703         struct ia64_pal_retval iprv;
1704         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1705         if (tr_valid)
1706                 tr_valid->piv_val = iprv.v0;
1707         return iprv.status;
1708 }
1709
1710 /*
1711  * PAL_PREFETCH_VISIBILITY transaction types
1712  */
1713 #define PAL_VISIBILITY_VIRTUAL          0
1714 #define PAL_VISIBILITY_PHYSICAL         1
1715
1716 /*
1717  * PAL_PREFETCH_VISIBILITY return codes
1718  */
1719 #define PAL_VISIBILITY_OK               1
1720 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1721 #define PAL_VISIBILITY_INVAL_ARG        -2
1722 #define PAL_VISIBILITY_ERROR            -3
1723
1724 static inline s64
1725 ia64_pal_prefetch_visibility (s64 trans_type)
1726 {
1727         struct ia64_pal_retval iprv;
1728         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1729         return iprv.status;
1730 }
1731
1732 /* data structure for getting information on logical to physical mappings */
1733 typedef union pal_log_overview_u {
1734         struct {
1735                 u64     num_log         :16,    /* Total number of logical
1736                                                  * processors on this die
1737                                                  */
1738                         tpc             :8,     /* Threads per core */
1739                         reserved3       :8,     /* Reserved */
1740                         cpp             :8,     /* Cores per processor */
1741                         reserved2       :8,     /* Reserved */
1742                         ppid            :8,     /* Physical processor ID */
1743                         reserved1       :8;     /* Reserved */
1744         } overview_bits;
1745         u64 overview_data;
1746 } pal_log_overview_t;
1747
1748 typedef union pal_proc_n_log_info1_u{
1749         struct {
1750                 u64     tid             :16,    /* Thread id */
1751                         reserved2       :16,    /* Reserved */
1752                         cid             :16,    /* Core id */
1753                         reserved1       :16;    /* Reserved */
1754         } ppli1_bits;
1755         u64     ppli1_data;
1756 } pal_proc_n_log_info1_t;
1757
1758 typedef union pal_proc_n_log_info2_u {
1759         struct {
1760                 u64     la              :16,    /* Logical address */
1761                         reserved        :48;    /* Reserved */
1762         } ppli2_bits;
1763         u64     ppli2_data;
1764 } pal_proc_n_log_info2_t;
1765
1766 typedef struct pal_logical_to_physical_s
1767 {
1768         pal_log_overview_t overview;
1769         pal_proc_n_log_info1_t ppli1;
1770         pal_proc_n_log_info2_t ppli2;
1771 } pal_logical_to_physical_t;
1772
1773 #define overview_num_log        overview.overview_bits.num_log
1774 #define overview_tpc            overview.overview_bits.tpc
1775 #define overview_cpp            overview.overview_bits.cpp
1776 #define overview_ppid           overview.overview_bits.ppid
1777 #define log1_tid                ppli1.ppli1_bits.tid
1778 #define log1_cid                ppli1.ppli1_bits.cid
1779 #define log2_la                 ppli2.ppli2_bits.la
1780
1781 /* Get information on logical to physical processor mappings. */
1782 static inline s64
1783 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1784 {
1785         struct ia64_pal_retval iprv;
1786
1787         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1788
1789         if (iprv.status == PAL_STATUS_SUCCESS)
1790         {
1791                 mapping->overview.overview_data = iprv.v0;
1792                 mapping->ppli1.ppli1_data = iprv.v1;
1793                 mapping->ppli2.ppli2_data = iprv.v2;
1794         }
1795
1796         return iprv.status;
1797 }
1798
1799 typedef struct pal_cache_shared_info_s
1800 {
1801         u64 num_shared;
1802         pal_proc_n_log_info1_t ppli1;
1803         pal_proc_n_log_info2_t ppli2;
1804 } pal_cache_shared_info_t;
1805
1806 /* Get information on logical to physical processor mappings. */
1807 static inline s64
1808 ia64_pal_cache_shared_info(u64 level,
1809                 u64 type,
1810                 u64 proc_number,
1811                 pal_cache_shared_info_t *info)
1812 {
1813         struct ia64_pal_retval iprv;
1814
1815         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1816
1817         if (iprv.status == PAL_STATUS_SUCCESS) {
1818                 info->num_shared = iprv.v0;
1819                 info->ppli1.ppli1_data = iprv.v1;
1820                 info->ppli2.ppli2_data = iprv.v2;
1821         }
1822
1823         return iprv.status;
1824 }
1825 #endif /* __ASSEMBLY__ */
1826
1827 #endif /* _ASM_IA64_PAL_H */