1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #include <linux/spinlock.h>
8 #include <asm/barrier.h>
11 #define INS_CACHE (1 << 0)
12 #define DATA_CACHE (1 << 1)
13 #define CACHE_INV (1 << 4)
14 #define CACHE_CLR (1 << 5)
15 #define CACHE_OMS (1 << 6)
17 void local_icache_inv_all(void *priv)
19 mtcr("cr17", INS_CACHE|CACHE_INV);
23 #ifdef CONFIG_CPU_HAS_ICACHE_INS
24 void icache_inv_range(unsigned long start, unsigned long end)
26 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
28 for (; i < end; i += L1_CACHE_BYTES)
29 asm volatile("icache.iva %0\n"::"r"(i):"memory");
38 static DEFINE_SPINLOCK(cache_lock);
40 static inline void cache_op_line(unsigned long i, unsigned int val)
46 void local_icache_inv_range(void *priv)
48 struct cache_range *param = priv;
49 unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
52 spin_lock_irqsave(&cache_lock, flags);
54 for (; i < param->end; i += L1_CACHE_BYTES)
55 cache_op_line(i, INS_CACHE | CACHE_INV | CACHE_OMS);
57 spin_unlock_irqrestore(&cache_lock, flags);
62 void icache_inv_range(unsigned long start, unsigned long end)
64 struct cache_range param = { start, end };
67 local_icache_inv_range(¶m);
69 on_each_cpu(local_icache_inv_range, ¶m, 1);
73 inline void dcache_wb_line(unsigned long start)
75 asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
79 void dcache_wb_range(unsigned long start, unsigned long end)
81 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
83 for (; i < end; i += L1_CACHE_BYTES)
84 asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
88 void cache_wbinv_range(unsigned long start, unsigned long end)
90 dcache_wb_range(start, end);
91 icache_inv_range(start, end);
93 EXPORT_SYMBOL(cache_wbinv_range);
95 void dma_wbinv_range(unsigned long start, unsigned long end)
97 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
99 for (; i < end; i += L1_CACHE_BYTES)
100 asm volatile("dcache.civa %0\n"::"r"(i):"memory");
104 void dma_inv_range(unsigned long start, unsigned long end)
106 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
108 for (; i < end; i += L1_CACHE_BYTES)
109 asm volatile("dcache.iva %0\n"::"r"(i):"memory");
113 void dma_wb_range(unsigned long start, unsigned long end)
115 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
117 for (; i < end; i += L1_CACHE_BYTES)
118 asm volatile("dcache.cva %0\n"::"r"(i):"memory");