1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #ifndef __ASM_CSKY_ENTRY_H
5 #define __ASM_CSKY_ENTRY_H
8 #include <abi/regdef.h>
24 .macro SAVE_ALL epc_inc
56 #ifdef CONFIG_CPU_HAS_HILO
80 #ifdef CONFIG_CPU_HAS_HILO
105 .macro SAVE_SWITCH_STACK
116 #ifdef CONFIG_CPU_HAS_HILO
127 .macro RESTORE_SWITCH_STACK
128 #ifdef CONFIG_CPU_HAS_HILO
149 /* MMU registers operators. */
179 /* Init psr and enable ee */
180 lrw r6, DEFAULT_PSR_VALUE
184 /* Invalid I/Dcache BTB BHT */
190 /* Invalid all TLB */
192 mtcr r6, cr<8, 15> /* Set MCIR */
194 /* Check MMU on/off */
199 /* MMU off: setup mapping tlb entry */
201 mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
203 grs r6, 1f /* Get current pa by PC */
204 bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
206 mtcr r6, cr<4, 15> /* Set MEH */
211 mtcr r8, cr<2, 15> /* Set MEL0 */
214 mtcr r8, cr<3, 15> /* Set MEL1 */
217 mtcr r8, cr<8, 15> /* Set MCIR to write TLB */
222 * MMU on: use origin MSA value from bootloader
224 * cr<30/31, 15> MSA register format:
225 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
226 * BA Reserved SH WA B SO SEC C D V
228 mfcr r6, cr<30, 15> /* Get MSA0 */
233 mtcr r6, cr<30, 15> /* Set MSA0 */
236 mtcr r6, cr<31, 15> /* Clr MSA1 */
243 jmpi 3f /* jump to va */
247 .macro ANDI_R3 rx, imm
249 andi \rx, (\imm >> 3)
251 #endif /* __ASM_CSKY_ENTRY_H */