1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __ASM_CSKY_PGTABLE_BITS_H
4 #define __ASM_CSKY_PGTABLE_BITS_H
6 /* implemented in software */
7 #define _PAGE_PRESENT (1<<0)
8 #define _PAGE_READ (1<<1)
9 #define _PAGE_WRITE (1<<2)
10 #define _PAGE_ACCESSED (1<<3)
11 #define _PAGE_MODIFIED (1<<4)
13 /* implemented in hardware */
14 #define _PAGE_GLOBAL (1<<6)
15 #define _PAGE_VALID (1<<7)
16 #define _PAGE_DIRTY (1<<8)
18 #define _PAGE_CACHE (3<<9)
19 #define _PAGE_UNCACHE (2<<9)
20 #define _PAGE_SO _PAGE_UNCACHE
21 #define _CACHE_MASK (7<<9)
23 #define _CACHE_CACHED _PAGE_CACHE
24 #define _CACHE_UNCACHED _PAGE_UNCACHE
26 #define _PAGE_PROT_NONE _PAGE_READ
29 * Encode and decode a swap entry
32 * bit 0: _PAGE_PRESENT (zero)
33 * bit 1: _PAGE_READ (zero)
34 * bit 2 - 5: swap type[0 - 3]
35 * bit 6: _PAGE_GLOBAL (zero)
36 * bit 7: _PAGE_VALID (zero)
38 * bit 9 - 31: swap offset
40 #define __swp_type(x) ((((x).val >> 2) & 0xf) | \
41 (((x).val >> 4) & 0x10))
42 #define __swp_offset(x) ((x).val >> 9)
43 #define __swp_entry(type, offset) ((swp_entry_t) { \
44 ((type & 0xf) << 2) | \
45 ((type & 0x10) << 4) | \
48 #define HAVE_ARCH_UNMAPPED_AREA
50 #endif /* __ASM_CSKY_PGTABLE_BITS_H */