1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __l2cache_defs_h
3 #define __l2cache_defs_h
6 * This file is autogenerated from
9 * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
10 * Any changes here will be lost.
12 * -*- buffer-read-only: t -*-
14 /* Main access macros */
16 #define REG_RD( scope, inst, reg ) \
17 REG_READ( reg_##scope##_##reg, \
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \
23 REG_WRITE( reg_##scope##_##reg, \
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \
29 REG_READ( reg_##scope##_##reg, \
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
31 (index) * STRIDE_##scope##_##reg )
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 REG_WRITE( reg_##scope##_##reg, \
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
38 (index) * STRIDE_##scope##_##reg, (val) )
42 #define REG_RD_INT( scope, inst, reg ) \
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
47 #define REG_WR_INT( scope, inst, reg, val ) \
48 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #ifndef REG_RD_INT_VECT
52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
53 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
54 (index) * STRIDE_##scope##_##reg )
57 #ifndef REG_WR_INT_VECT
58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
59 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
60 (index) * STRIDE_##scope##_##reg, (val) )
64 #define REG_TYPE_CONV( type, orgtype, val ) \
65 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69 #define reg_page_size 8192
73 #define REG_ADDR( scope, inst, reg ) \
74 ( (inst) + REG_RD_ADDR_##scope##_##reg )
78 #define REG_ADDR_VECT( scope, inst, reg, index ) \
79 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
80 (index) * STRIDE_##scope##_##reg )
83 /* C-code for register scope l2cache */
85 /* Register rw_cfg, scope l2cache, type rw */
88 unsigned int dummy1 : 31;
90 #define REG_RD_ADDR_l2cache_rw_cfg 0
91 #define REG_WR_ADDR_l2cache_rw_cfg 0
93 /* Register rw_ctrl, scope l2cache, type rw */
95 unsigned int dummy1 : 7;
96 unsigned int cbase : 9;
97 unsigned int dummy2 : 4;
98 unsigned int csize : 10;
99 unsigned int dummy3 : 2;
100 } reg_l2cache_rw_ctrl;
101 #define REG_RD_ADDR_l2cache_rw_ctrl 4
102 #define REG_WR_ADDR_l2cache_rw_ctrl 4
104 /* Register rw_idxop, scope l2cache, type rw */
106 unsigned int idx : 10;
107 unsigned int dummy1 : 14;
108 unsigned int way : 3;
109 unsigned int dummy2 : 2;
110 unsigned int cmd : 3;
111 } reg_l2cache_rw_idxop;
112 #define REG_RD_ADDR_l2cache_rw_idxop 8
113 #define REG_WR_ADDR_l2cache_rw_idxop 8
115 /* Register rw_addrop_addr, scope l2cache, type rw */
117 unsigned int addr : 32;
118 } reg_l2cache_rw_addrop_addr;
119 #define REG_RD_ADDR_l2cache_rw_addrop_addr 12
120 #define REG_WR_ADDR_l2cache_rw_addrop_addr 12
122 /* Register rw_addrop_ctrl, scope l2cache, type rw */
124 unsigned int size : 16;
125 unsigned int dummy1 : 13;
126 unsigned int cmd : 3;
127 } reg_l2cache_rw_addrop_ctrl;
128 #define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
129 #define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
134 regk_l2cache_flush = 0x00000001,
135 regk_l2cache_no = 0x00000000,
136 regk_l2cache_rw_addrop_addr_default = 0x00000000,
137 regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
138 regk_l2cache_rw_cfg_default = 0x00000000,
139 regk_l2cache_rw_ctrl_default = 0x00000000,
140 regk_l2cache_rw_idxop_default = 0x00000000,
141 regk_l2cache_yes = 0x00000001
143 #endif /* __l2cache_defs_h */