1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_sw_mpu_defs_h
3 #define __iop_sw_mpu_defs_h
6 * This file is autogenerated from
9 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
10 * Any changes here will be lost.
12 * -*- buffer-read-only: t -*-
14 /* Main access macros */
16 #define REG_RD( scope, inst, reg ) \
17 REG_READ( reg_##scope##_##reg, \
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \
23 REG_WRITE( reg_##scope##_##reg, \
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \
29 REG_READ( reg_##scope##_##reg, \
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
31 (index) * STRIDE_##scope##_##reg )
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 REG_WRITE( reg_##scope##_##reg, \
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
38 (index) * STRIDE_##scope##_##reg, (val) )
42 #define REG_RD_INT( scope, inst, reg ) \
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
47 #define REG_WR_INT( scope, inst, reg, val ) \
48 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #ifndef REG_RD_INT_VECT
52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
53 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
54 (index) * STRIDE_##scope##_##reg )
57 #ifndef REG_WR_INT_VECT
58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
59 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
60 (index) * STRIDE_##scope##_##reg, (val) )
64 #define REG_TYPE_CONV( type, orgtype, val ) \
65 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69 #define reg_page_size 8192
73 #define REG_ADDR( scope, inst, reg ) \
74 ( (inst) + REG_RD_ADDR_##scope##_##reg )
78 #define REG_ADDR_VECT( scope, inst, reg, index ) \
79 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
80 (index) * STRIDE_##scope##_##reg )
83 /* C-code for register scope iop_sw_mpu */
85 /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
88 unsigned int dummy1 : 30;
89 } reg_iop_sw_mpu_rw_sw_cfg_owner;
90 #define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
91 #define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
93 /* Register r_spu_trace, scope iop_sw_mpu, type r */
94 typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
95 #define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
97 /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
98 typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
99 #define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
101 /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
103 unsigned int keep_owner : 1;
104 unsigned int cmd : 2;
105 unsigned int size : 3;
106 unsigned int wr_spu_mem : 1;
107 unsigned int dummy1 : 25;
108 } reg_iop_sw_mpu_rw_mc_ctrl;
109 #define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
110 #define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
112 /* Register rw_mc_data, scope iop_sw_mpu, type rw */
114 unsigned int val : 32;
115 } reg_iop_sw_mpu_rw_mc_data;
116 #define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
117 #define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
119 /* Register rw_mc_addr, scope iop_sw_mpu, type rw */
120 typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
121 #define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
122 #define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
124 /* Register rs_mc_data, scope iop_sw_mpu, type rs */
125 typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
126 #define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
128 /* Register r_mc_data, scope iop_sw_mpu, type r */
129 typedef unsigned int reg_iop_sw_mpu_r_mc_data;
130 #define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
132 /* Register r_mc_stat, scope iop_sw_mpu, type r */
134 unsigned int busy_cpu : 1;
135 unsigned int busy_mpu : 1;
136 unsigned int busy_spu : 1;
137 unsigned int owned_by_cpu : 1;
138 unsigned int owned_by_mpu : 1;
139 unsigned int owned_by_spu : 1;
140 unsigned int dummy1 : 26;
141 } reg_iop_sw_mpu_r_mc_stat;
142 #define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
144 /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
146 unsigned int byte0 : 8;
147 unsigned int byte1 : 8;
148 unsigned int byte2 : 8;
149 unsigned int byte3 : 8;
150 } reg_iop_sw_mpu_rw_bus_clr_mask;
151 #define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
152 #define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
154 /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
156 unsigned int byte0 : 8;
157 unsigned int byte1 : 8;
158 unsigned int byte2 : 8;
159 unsigned int byte3 : 8;
160 } reg_iop_sw_mpu_rw_bus_set_mask;
161 #define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
162 #define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
164 /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
166 unsigned int byte0 : 1;
167 unsigned int byte1 : 1;
168 unsigned int byte2 : 1;
169 unsigned int byte3 : 1;
170 unsigned int dummy1 : 28;
171 } reg_iop_sw_mpu_rw_bus_oe_clr_mask;
172 #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
173 #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
175 /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
177 unsigned int byte0 : 1;
178 unsigned int byte1 : 1;
179 unsigned int byte2 : 1;
180 unsigned int byte3 : 1;
181 unsigned int dummy1 : 28;
182 } reg_iop_sw_mpu_rw_bus_oe_set_mask;
183 #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
184 #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
186 /* Register r_bus_in, scope iop_sw_mpu, type r */
187 typedef unsigned int reg_iop_sw_mpu_r_bus_in;
188 #define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
190 /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
192 unsigned int val : 32;
193 } reg_iop_sw_mpu_rw_gio_clr_mask;
194 #define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
195 #define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
197 /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
199 unsigned int val : 32;
200 } reg_iop_sw_mpu_rw_gio_set_mask;
201 #define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
202 #define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
204 /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
206 unsigned int val : 32;
207 } reg_iop_sw_mpu_rw_gio_oe_clr_mask;
208 #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
209 #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
211 /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
213 unsigned int val : 32;
214 } reg_iop_sw_mpu_rw_gio_oe_set_mask;
215 #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
216 #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
218 /* Register r_gio_in, scope iop_sw_mpu, type r */
219 typedef unsigned int reg_iop_sw_mpu_r_gio_in;
220 #define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
222 /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
224 unsigned int intr0 : 1;
225 unsigned int intr1 : 1;
226 unsigned int intr2 : 1;
227 unsigned int intr3 : 1;
228 unsigned int intr4 : 1;
229 unsigned int intr5 : 1;
230 unsigned int intr6 : 1;
231 unsigned int intr7 : 1;
232 unsigned int intr8 : 1;
233 unsigned int intr9 : 1;
234 unsigned int intr10 : 1;
235 unsigned int intr11 : 1;
236 unsigned int intr12 : 1;
237 unsigned int intr13 : 1;
238 unsigned int intr14 : 1;
239 unsigned int intr15 : 1;
240 unsigned int intr16 : 1;
241 unsigned int intr17 : 1;
242 unsigned int intr18 : 1;
243 unsigned int intr19 : 1;
244 unsigned int intr20 : 1;
245 unsigned int intr21 : 1;
246 unsigned int intr22 : 1;
247 unsigned int intr23 : 1;
248 unsigned int intr24 : 1;
249 unsigned int intr25 : 1;
250 unsigned int intr26 : 1;
251 unsigned int intr27 : 1;
252 unsigned int intr28 : 1;
253 unsigned int intr29 : 1;
254 unsigned int intr30 : 1;
255 unsigned int intr31 : 1;
256 } reg_iop_sw_mpu_rw_cpu_intr;
257 #define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
258 #define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
260 /* Register r_cpu_intr, scope iop_sw_mpu, type r */
262 unsigned int intr0 : 1;
263 unsigned int intr1 : 1;
264 unsigned int intr2 : 1;
265 unsigned int intr3 : 1;
266 unsigned int intr4 : 1;
267 unsigned int intr5 : 1;
268 unsigned int intr6 : 1;
269 unsigned int intr7 : 1;
270 unsigned int intr8 : 1;
271 unsigned int intr9 : 1;
272 unsigned int intr10 : 1;
273 unsigned int intr11 : 1;
274 unsigned int intr12 : 1;
275 unsigned int intr13 : 1;
276 unsigned int intr14 : 1;
277 unsigned int intr15 : 1;
278 unsigned int intr16 : 1;
279 unsigned int intr17 : 1;
280 unsigned int intr18 : 1;
281 unsigned int intr19 : 1;
282 unsigned int intr20 : 1;
283 unsigned int intr21 : 1;
284 unsigned int intr22 : 1;
285 unsigned int intr23 : 1;
286 unsigned int intr24 : 1;
287 unsigned int intr25 : 1;
288 unsigned int intr26 : 1;
289 unsigned int intr27 : 1;
290 unsigned int intr28 : 1;
291 unsigned int intr29 : 1;
292 unsigned int intr30 : 1;
293 unsigned int intr31 : 1;
294 } reg_iop_sw_mpu_r_cpu_intr;
295 #define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
297 /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
299 unsigned int spu_intr0 : 1;
300 unsigned int trigger_grp0 : 1;
301 unsigned int timer_grp0 : 1;
302 unsigned int fifo_out : 1;
303 unsigned int spu_intr1 : 1;
304 unsigned int trigger_grp1 : 1;
305 unsigned int timer_grp1 : 1;
306 unsigned int fifo_in : 1;
307 unsigned int spu_intr2 : 1;
308 unsigned int trigger_grp2 : 1;
309 unsigned int fifo_out_extra : 1;
310 unsigned int dmc_out : 1;
311 unsigned int spu_intr3 : 1;
312 unsigned int trigger_grp3 : 1;
313 unsigned int fifo_in_extra : 1;
314 unsigned int dmc_in : 1;
315 unsigned int dummy1 : 16;
316 } reg_iop_sw_mpu_rw_intr_grp0_mask;
317 #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
318 #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
320 /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
322 unsigned int spu_intr0 : 1;
323 unsigned int dummy1 : 3;
324 unsigned int spu_intr1 : 1;
325 unsigned int dummy2 : 3;
326 unsigned int spu_intr2 : 1;
327 unsigned int dummy3 : 3;
328 unsigned int spu_intr3 : 1;
329 unsigned int dummy4 : 19;
330 } reg_iop_sw_mpu_rw_ack_intr_grp0;
331 #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
332 #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
334 /* Register r_intr_grp0, scope iop_sw_mpu, type r */
336 unsigned int spu_intr0 : 1;
337 unsigned int trigger_grp0 : 1;
338 unsigned int timer_grp0 : 1;
339 unsigned int fifo_out : 1;
340 unsigned int spu_intr1 : 1;
341 unsigned int trigger_grp1 : 1;
342 unsigned int timer_grp1 : 1;
343 unsigned int fifo_in : 1;
344 unsigned int spu_intr2 : 1;
345 unsigned int trigger_grp2 : 1;
346 unsigned int fifo_out_extra : 1;
347 unsigned int dmc_out : 1;
348 unsigned int spu_intr3 : 1;
349 unsigned int trigger_grp3 : 1;
350 unsigned int fifo_in_extra : 1;
351 unsigned int dmc_in : 1;
352 unsigned int dummy1 : 16;
353 } reg_iop_sw_mpu_r_intr_grp0;
354 #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
356 /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
358 unsigned int spu_intr0 : 1;
359 unsigned int trigger_grp0 : 1;
360 unsigned int timer_grp0 : 1;
361 unsigned int fifo_out : 1;
362 unsigned int spu_intr1 : 1;
363 unsigned int trigger_grp1 : 1;
364 unsigned int timer_grp1 : 1;
365 unsigned int fifo_in : 1;
366 unsigned int spu_intr2 : 1;
367 unsigned int trigger_grp2 : 1;
368 unsigned int fifo_out_extra : 1;
369 unsigned int dmc_out : 1;
370 unsigned int spu_intr3 : 1;
371 unsigned int trigger_grp3 : 1;
372 unsigned int fifo_in_extra : 1;
373 unsigned int dmc_in : 1;
374 unsigned int dummy1 : 16;
375 } reg_iop_sw_mpu_r_masked_intr_grp0;
376 #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
378 /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
380 unsigned int spu_intr4 : 1;
381 unsigned int trigger_grp4 : 1;
382 unsigned int fifo_out_extra : 1;
383 unsigned int dmc_out : 1;
384 unsigned int spu_intr5 : 1;
385 unsigned int trigger_grp5 : 1;
386 unsigned int fifo_in_extra : 1;
387 unsigned int dmc_in : 1;
388 unsigned int spu_intr6 : 1;
389 unsigned int trigger_grp6 : 1;
390 unsigned int timer_grp0 : 1;
391 unsigned int fifo_out : 1;
392 unsigned int spu_intr7 : 1;
393 unsigned int trigger_grp7 : 1;
394 unsigned int timer_grp1 : 1;
395 unsigned int fifo_in : 1;
396 unsigned int dummy1 : 16;
397 } reg_iop_sw_mpu_rw_intr_grp1_mask;
398 #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
399 #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
401 /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
403 unsigned int spu_intr4 : 1;
404 unsigned int dummy1 : 3;
405 unsigned int spu_intr5 : 1;
406 unsigned int dummy2 : 3;
407 unsigned int spu_intr6 : 1;
408 unsigned int dummy3 : 3;
409 unsigned int spu_intr7 : 1;
410 unsigned int dummy4 : 19;
411 } reg_iop_sw_mpu_rw_ack_intr_grp1;
412 #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
413 #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
415 /* Register r_intr_grp1, scope iop_sw_mpu, type r */
417 unsigned int spu_intr4 : 1;
418 unsigned int trigger_grp4 : 1;
419 unsigned int fifo_out_extra : 1;
420 unsigned int dmc_out : 1;
421 unsigned int spu_intr5 : 1;
422 unsigned int trigger_grp5 : 1;
423 unsigned int fifo_in_extra : 1;
424 unsigned int dmc_in : 1;
425 unsigned int spu_intr6 : 1;
426 unsigned int trigger_grp6 : 1;
427 unsigned int timer_grp0 : 1;
428 unsigned int fifo_out : 1;
429 unsigned int spu_intr7 : 1;
430 unsigned int trigger_grp7 : 1;
431 unsigned int timer_grp1 : 1;
432 unsigned int fifo_in : 1;
433 unsigned int dummy1 : 16;
434 } reg_iop_sw_mpu_r_intr_grp1;
435 #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
437 /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
439 unsigned int spu_intr4 : 1;
440 unsigned int trigger_grp4 : 1;
441 unsigned int fifo_out_extra : 1;
442 unsigned int dmc_out : 1;
443 unsigned int spu_intr5 : 1;
444 unsigned int trigger_grp5 : 1;
445 unsigned int fifo_in_extra : 1;
446 unsigned int dmc_in : 1;
447 unsigned int spu_intr6 : 1;
448 unsigned int trigger_grp6 : 1;
449 unsigned int timer_grp0 : 1;
450 unsigned int fifo_out : 1;
451 unsigned int spu_intr7 : 1;
452 unsigned int trigger_grp7 : 1;
453 unsigned int timer_grp1 : 1;
454 unsigned int fifo_in : 1;
455 unsigned int dummy1 : 16;
456 } reg_iop_sw_mpu_r_masked_intr_grp1;
457 #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
459 /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
461 unsigned int spu_intr8 : 1;
462 unsigned int trigger_grp0 : 1;
463 unsigned int timer_grp0 : 1;
464 unsigned int fifo_out : 1;
465 unsigned int spu_intr9 : 1;
466 unsigned int trigger_grp1 : 1;
467 unsigned int timer_grp1 : 1;
468 unsigned int fifo_in : 1;
469 unsigned int spu_intr10 : 1;
470 unsigned int trigger_grp2 : 1;
471 unsigned int fifo_out_extra : 1;
472 unsigned int dmc_out : 1;
473 unsigned int spu_intr11 : 1;
474 unsigned int trigger_grp3 : 1;
475 unsigned int fifo_in_extra : 1;
476 unsigned int dmc_in : 1;
477 unsigned int dummy1 : 16;
478 } reg_iop_sw_mpu_rw_intr_grp2_mask;
479 #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
480 #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
482 /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
484 unsigned int spu_intr8 : 1;
485 unsigned int dummy1 : 3;
486 unsigned int spu_intr9 : 1;
487 unsigned int dummy2 : 3;
488 unsigned int spu_intr10 : 1;
489 unsigned int dummy3 : 3;
490 unsigned int spu_intr11 : 1;
491 unsigned int dummy4 : 19;
492 } reg_iop_sw_mpu_rw_ack_intr_grp2;
493 #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
494 #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
496 /* Register r_intr_grp2, scope iop_sw_mpu, type r */
498 unsigned int spu_intr8 : 1;
499 unsigned int trigger_grp0 : 1;
500 unsigned int timer_grp0 : 1;
501 unsigned int fifo_out : 1;
502 unsigned int spu_intr9 : 1;
503 unsigned int trigger_grp1 : 1;
504 unsigned int timer_grp1 : 1;
505 unsigned int fifo_in : 1;
506 unsigned int spu_intr10 : 1;
507 unsigned int trigger_grp2 : 1;
508 unsigned int fifo_out_extra : 1;
509 unsigned int dmc_out : 1;
510 unsigned int spu_intr11 : 1;
511 unsigned int trigger_grp3 : 1;
512 unsigned int fifo_in_extra : 1;
513 unsigned int dmc_in : 1;
514 unsigned int dummy1 : 16;
515 } reg_iop_sw_mpu_r_intr_grp2;
516 #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
518 /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
520 unsigned int spu_intr8 : 1;
521 unsigned int trigger_grp0 : 1;
522 unsigned int timer_grp0 : 1;
523 unsigned int fifo_out : 1;
524 unsigned int spu_intr9 : 1;
525 unsigned int trigger_grp1 : 1;
526 unsigned int timer_grp1 : 1;
527 unsigned int fifo_in : 1;
528 unsigned int spu_intr10 : 1;
529 unsigned int trigger_grp2 : 1;
530 unsigned int fifo_out_extra : 1;
531 unsigned int dmc_out : 1;
532 unsigned int spu_intr11 : 1;
533 unsigned int trigger_grp3 : 1;
534 unsigned int fifo_in_extra : 1;
535 unsigned int dmc_in : 1;
536 unsigned int dummy1 : 16;
537 } reg_iop_sw_mpu_r_masked_intr_grp2;
538 #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
540 /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
542 unsigned int spu_intr12 : 1;
543 unsigned int trigger_grp4 : 1;
544 unsigned int fifo_out_extra : 1;
545 unsigned int dmc_out : 1;
546 unsigned int spu_intr13 : 1;
547 unsigned int trigger_grp5 : 1;
548 unsigned int fifo_in_extra : 1;
549 unsigned int dmc_in : 1;
550 unsigned int spu_intr14 : 1;
551 unsigned int trigger_grp6 : 1;
552 unsigned int timer_grp0 : 1;
553 unsigned int fifo_out : 1;
554 unsigned int spu_intr15 : 1;
555 unsigned int trigger_grp7 : 1;
556 unsigned int timer_grp1 : 1;
557 unsigned int fifo_in : 1;
558 unsigned int dummy1 : 16;
559 } reg_iop_sw_mpu_rw_intr_grp3_mask;
560 #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
561 #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
563 /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
565 unsigned int spu_intr12 : 1;
566 unsigned int dummy1 : 3;
567 unsigned int spu_intr13 : 1;
568 unsigned int dummy2 : 3;
569 unsigned int spu_intr14 : 1;
570 unsigned int dummy3 : 3;
571 unsigned int spu_intr15 : 1;
572 unsigned int dummy4 : 19;
573 } reg_iop_sw_mpu_rw_ack_intr_grp3;
574 #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
575 #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
577 /* Register r_intr_grp3, scope iop_sw_mpu, type r */
579 unsigned int spu_intr12 : 1;
580 unsigned int trigger_grp4 : 1;
581 unsigned int fifo_out_extra : 1;
582 unsigned int dmc_out : 1;
583 unsigned int spu_intr13 : 1;
584 unsigned int trigger_grp5 : 1;
585 unsigned int fifo_in_extra : 1;
586 unsigned int dmc_in : 1;
587 unsigned int spu_intr14 : 1;
588 unsigned int trigger_grp6 : 1;
589 unsigned int timer_grp0 : 1;
590 unsigned int fifo_out : 1;
591 unsigned int spu_intr15 : 1;
592 unsigned int trigger_grp7 : 1;
593 unsigned int timer_grp1 : 1;
594 unsigned int fifo_in : 1;
595 unsigned int dummy1 : 16;
596 } reg_iop_sw_mpu_r_intr_grp3;
597 #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
599 /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
601 unsigned int spu_intr12 : 1;
602 unsigned int trigger_grp4 : 1;
603 unsigned int fifo_out_extra : 1;
604 unsigned int dmc_out : 1;
605 unsigned int spu_intr13 : 1;
606 unsigned int trigger_grp5 : 1;
607 unsigned int fifo_in_extra : 1;
608 unsigned int dmc_in : 1;
609 unsigned int spu_intr14 : 1;
610 unsigned int trigger_grp6 : 1;
611 unsigned int timer_grp0 : 1;
612 unsigned int fifo_out : 1;
613 unsigned int spu_intr15 : 1;
614 unsigned int trigger_grp7 : 1;
615 unsigned int timer_grp1 : 1;
616 unsigned int fifo_in : 1;
617 unsigned int dummy1 : 16;
618 } reg_iop_sw_mpu_r_masked_intr_grp3;
619 #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
624 regk_iop_sw_mpu_copy = 0x00000000,
625 regk_iop_sw_mpu_cpu = 0x00000000,
626 regk_iop_sw_mpu_mpu = 0x00000001,
627 regk_iop_sw_mpu_no = 0x00000000,
628 regk_iop_sw_mpu_nop = 0x00000000,
629 regk_iop_sw_mpu_rd = 0x00000002,
630 regk_iop_sw_mpu_reg_copy = 0x00000001,
631 regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,
632 regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
633 regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
634 regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000,
635 regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
636 regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
637 regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
638 regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
639 regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
640 regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
641 regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
642 regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
643 regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
644 regk_iop_sw_mpu_set = 0x00000001,
645 regk_iop_sw_mpu_spu = 0x00000002,
646 regk_iop_sw_mpu_wr = 0x00000003,
647 regk_iop_sw_mpu_yes = 0x00000001
649 #endif /* __iop_sw_mpu_defs_h */