arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __timer_defs_asm_h
   3 #define __timer_defs_asm_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           timer.r
   8  *
   9  *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
  10  * Any changes here will be lost.
  11  *
  12  * -*- buffer-read-only: t -*-
  13  */
  14
  15 #ifndef REG_FIELD
  16 #define REG_FIELD( scope, reg, field, value ) \
  17   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  18 #define REG_FIELD_X_( value, shift ) ((value) << shift)
  19 #endif
  20
  21 #ifndef REG_STATE
  22 #define REG_STATE( scope, reg, field, symbolic_value ) \
  23   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  24 #define REG_STATE_X_( k, shift ) (k << shift)
  25 #endif
  26
  27 #ifndef REG_MASK
  28 #define REG_MASK( scope, reg, field ) \
  29   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  30 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  31 #endif
  32
  33 #ifndef REG_LSB
  34 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  35 #endif
  36
  37 #ifndef REG_BIT
  38 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  39 #endif
  40
  41 #ifndef REG_ADDR
  42 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  43 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  44 #endif
  45
  46 #ifndef REG_ADDR_VECT
  47 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  48          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  49                          STRIDE_##scope##_##reg )
  50 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  51                           ((inst) + offs + (index) * stride)
  52 #endif
  53
  54 /* Register rw_tmr0_div, scope timer, type rw */
  55 #define reg_timer_rw_tmr0_div_offset 0
  56
  57 /* Register r_tmr0_data, scope timer, type r */
  58 #define reg_timer_r_tmr0_data_offset 4
  59
  60 /* Register rw_tmr0_ctrl, scope timer, type rw */
  61 #define reg_timer_rw_tmr0_ctrl___op___lsb 0
  62 #define reg_timer_rw_tmr0_ctrl___op___width 2
  63 #define reg_timer_rw_tmr0_ctrl___freq___lsb 2
  64 #define reg_timer_rw_tmr0_ctrl___freq___width 3
  65 #define reg_timer_rw_tmr0_ctrl_offset 8
  66
  67 /* Register rw_tmr1_div, scope timer, type rw */
  68 #define reg_timer_rw_tmr1_div_offset 16
  69
  70 /* Register r_tmr1_data, scope timer, type r */
  71 #define reg_timer_r_tmr1_data_offset 20
  72
  73 /* Register rw_tmr1_ctrl, scope timer, type rw */
  74 #define reg_timer_rw_tmr1_ctrl___op___lsb 0
  75 #define reg_timer_rw_tmr1_ctrl___op___width 2
  76 #define reg_timer_rw_tmr1_ctrl___freq___lsb 2
  77 #define reg_timer_rw_tmr1_ctrl___freq___width 3
  78 #define reg_timer_rw_tmr1_ctrl_offset 24
  79
  80 /* Register rs_cnt_data, scope timer, type rs */
  81 #define reg_timer_rs_cnt_data___tmr___lsb 0
  82 #define reg_timer_rs_cnt_data___tmr___width 24
  83 #define reg_timer_rs_cnt_data___cnt___lsb 24
  84 #define reg_timer_rs_cnt_data___cnt___width 8
  85 #define reg_timer_rs_cnt_data_offset 32
  86
  87 /* Register r_cnt_data, scope timer, type r */
  88 #define reg_timer_r_cnt_data___tmr___lsb 0
  89 #define reg_timer_r_cnt_data___tmr___width 24
  90 #define reg_timer_r_cnt_data___cnt___lsb 24
  91 #define reg_timer_r_cnt_data___cnt___width 8
  92 #define reg_timer_r_cnt_data_offset 36
  93
  94 /* Register rw_cnt_cfg, scope timer, type rw */
  95 #define reg_timer_rw_cnt_cfg___clk___lsb 0
  96 #define reg_timer_rw_cnt_cfg___clk___width 2
  97 #define reg_timer_rw_cnt_cfg_offset 40
  98
  99 /* Register rw_trig, scope timer, type rw */
 100 #define reg_timer_rw_trig_offset 48
 101
 102 /* Register rw_trig_cfg, scope timer, type rw */
 103 #define reg_timer_rw_trig_cfg___tmr___lsb 0
 104 #define reg_timer_rw_trig_cfg___tmr___width 2
 105 #define reg_timer_rw_trig_cfg_offset 52
 106
 107 /* Register r_time, scope timer, type r */
 108 #define reg_timer_r_time_offset 56
 109
 110 /* Register rw_out, scope timer, type rw */
 111 #define reg_timer_rw_out___tmr___lsb 0
 112 #define reg_timer_rw_out___tmr___width 2
 113 #define reg_timer_rw_out_offset 60
 114
 115 /* Register rw_wd_ctrl, scope timer, type rw */
 116 #define reg_timer_rw_wd_ctrl___cnt___lsb 0
 117 #define reg_timer_rw_wd_ctrl___cnt___width 8
 118 #define reg_timer_rw_wd_ctrl___cmd___lsb 8
 119 #define reg_timer_rw_wd_ctrl___cmd___width 1
 120 #define reg_timer_rw_wd_ctrl___cmd___bit 8
 121 #define reg_timer_rw_wd_ctrl___key___lsb 9
 122 #define reg_timer_rw_wd_ctrl___key___width 7
 123 #define reg_timer_rw_wd_ctrl_offset 64
 124
 125 /* Register r_wd_stat, scope timer, type r */
 126 #define reg_timer_r_wd_stat___cnt___lsb 0
 127 #define reg_timer_r_wd_stat___cnt___width 8
 128 #define reg_timer_r_wd_stat___cmd___lsb 8
 129 #define reg_timer_r_wd_stat___cmd___width 1
 130 #define reg_timer_r_wd_stat___cmd___bit 8
 131 #define reg_timer_r_wd_stat_offset 68
 132
 133 /* Register rw_intr_mask, scope timer, type rw */
 134 #define reg_timer_rw_intr_mask___tmr0___lsb 0
 135 #define reg_timer_rw_intr_mask___tmr0___width 1
 136 #define reg_timer_rw_intr_mask___tmr0___bit 0
 137 #define reg_timer_rw_intr_mask___tmr1___lsb 1
 138 #define reg_timer_rw_intr_mask___tmr1___width 1
 139 #define reg_timer_rw_intr_mask___tmr1___bit 1
 140 #define reg_timer_rw_intr_mask___cnt___lsb 2
 141 #define reg_timer_rw_intr_mask___cnt___width 1
 142 #define reg_timer_rw_intr_mask___cnt___bit 2
 143 #define reg_timer_rw_intr_mask___trig___lsb 3
 144 #define reg_timer_rw_intr_mask___trig___width 1
 145 #define reg_timer_rw_intr_mask___trig___bit 3
 146 #define reg_timer_rw_intr_mask_offset 72
 147
 148 /* Register rw_ack_intr, scope timer, type rw */
 149 #define reg_timer_rw_ack_intr___tmr0___lsb 0
 150 #define reg_timer_rw_ack_intr___tmr0___width 1
 151 #define reg_timer_rw_ack_intr___tmr0___bit 0
 152 #define reg_timer_rw_ack_intr___tmr1___lsb 1
 153 #define reg_timer_rw_ack_intr___tmr1___width 1
 154 #define reg_timer_rw_ack_intr___tmr1___bit 1
 155 #define reg_timer_rw_ack_intr___cnt___lsb 2
 156 #define reg_timer_rw_ack_intr___cnt___width 1
 157 #define reg_timer_rw_ack_intr___cnt___bit 2
 158 #define reg_timer_rw_ack_intr___trig___lsb 3
 159 #define reg_timer_rw_ack_intr___trig___width 1
 160 #define reg_timer_rw_ack_intr___trig___bit 3
 161 #define reg_timer_rw_ack_intr_offset 76
 162
 163 /* Register r_intr, scope timer, type r */
 164 #define reg_timer_r_intr___tmr0___lsb 0
 165 #define reg_timer_r_intr___tmr0___width 1
 166 #define reg_timer_r_intr___tmr0___bit 0
 167 #define reg_timer_r_intr___tmr1___lsb 1
 168 #define reg_timer_r_intr___tmr1___width 1
 169 #define reg_timer_r_intr___tmr1___bit 1
 170 #define reg_timer_r_intr___cnt___lsb 2
 171 #define reg_timer_r_intr___cnt___width 1
 172 #define reg_timer_r_intr___cnt___bit 2
 173 #define reg_timer_r_intr___trig___lsb 3
 174 #define reg_timer_r_intr___trig___width 1
 175 #define reg_timer_r_intr___trig___bit 3
 176 #define reg_timer_r_intr_offset 80
 177
 178 /* Register r_masked_intr, scope timer, type r */
 179 #define reg_timer_r_masked_intr___tmr0___lsb 0
 180 #define reg_timer_r_masked_intr___tmr0___width 1
 181 #define reg_timer_r_masked_intr___tmr0___bit 0
 182 #define reg_timer_r_masked_intr___tmr1___lsb 1
 183 #define reg_timer_r_masked_intr___tmr1___width 1
 184 #define reg_timer_r_masked_intr___tmr1___bit 1
 185 #define reg_timer_r_masked_intr___cnt___lsb 2
 186 #define reg_timer_r_masked_intr___cnt___width 1
 187 #define reg_timer_r_masked_intr___cnt___bit 2
 188 #define reg_timer_r_masked_intr___trig___lsb 3
 189 #define reg_timer_r_masked_intr___trig___width 1
 190 #define reg_timer_r_masked_intr___trig___bit 3
 191 #define reg_timer_r_masked_intr_offset 84
 192
 193 /* Register rw_test, scope timer, type rw */
 194 #define reg_timer_rw_test___dis___lsb 0
 195 #define reg_timer_rw_test___dis___width 1
 196 #define reg_timer_rw_test___dis___bit 0
 197 #define reg_timer_rw_test___en___lsb 1
 198 #define reg_timer_rw_test___en___width 1
 199 #define reg_timer_rw_test___en___bit 1
 200 #define reg_timer_rw_test_offset 88
 201
 202
 203 /* Constants */
 204 #define regk_timer_ext                            0x00000001
 205 #define regk_timer_f100                           0x00000007
 206 #define regk_timer_f29_493                        0x00000004
 207 #define regk_timer_f32                            0x00000005
 208 #define regk_timer_f32_768                        0x00000006
 209 #define regk_timer_f90                            0x00000003
 210 #define regk_timer_hold                           0x00000001
 211 #define regk_timer_ld                             0x00000000
 212 #define regk_timer_no                             0x00000000
 213 #define regk_timer_off                            0x00000000
 214 #define regk_timer_run                            0x00000002
 215 #define regk_timer_rw_cnt_cfg_default             0x00000000
 216 #define regk_timer_rw_intr_mask_default           0x00000000
 217 #define regk_timer_rw_out_default                 0x00000000
 218 #define regk_timer_rw_test_default                0x00000000
 219 #define regk_timer_rw_tmr0_ctrl_default           0x00000000
 220 #define regk_timer_rw_tmr1_ctrl_default           0x00000000
 221 #define regk_timer_rw_trig_cfg_default            0x00000000
 222 #define regk_timer_start                          0x00000001
 223 #define regk_timer_stop                           0x00000000
 224 #define regk_timer_time                           0x00000001
 225 #define regk_timer_tmr0                           0x00000002
 226 #define regk_timer_tmr1                           0x00000003
 227 #define regk_timer_vclk                           0x00000002
 228 #define regk_timer_yes                            0x00000001
 229 #endif /* __timer_defs_asm_h */