1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_sw_cfg_defs_h
3 #define __iop_sw_cfg_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
9 * last modfied: Mon Apr 11 16:10:19 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
12 * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_sw_cfg */
88 /* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
91 unsigned int dummy1 : 30;
92 } reg_iop_sw_cfg_rw_crc_par0_owner;
93 #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
94 #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
96 /* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
99 unsigned int dummy1 : 30;
100 } reg_iop_sw_cfg_rw_crc_par1_owner;
101 #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
102 #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
104 /* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
106 unsigned int cfg : 2;
107 unsigned int dummy1 : 30;
108 } reg_iop_sw_cfg_rw_dmc_in0_owner;
109 #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
110 #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
112 /* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
114 unsigned int cfg : 2;
115 unsigned int dummy1 : 30;
116 } reg_iop_sw_cfg_rw_dmc_in1_owner;
117 #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
118 #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
120 /* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
122 unsigned int cfg : 2;
123 unsigned int dummy1 : 30;
124 } reg_iop_sw_cfg_rw_dmc_out0_owner;
125 #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
126 #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
128 /* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
130 unsigned int cfg : 2;
131 unsigned int dummy1 : 30;
132 } reg_iop_sw_cfg_rw_dmc_out1_owner;
133 #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
134 #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
136 /* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
138 unsigned int cfg : 2;
139 unsigned int dummy1 : 30;
140 } reg_iop_sw_cfg_rw_fifo_in0_owner;
141 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
142 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
144 /* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
146 unsigned int cfg : 2;
147 unsigned int dummy1 : 30;
148 } reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
149 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
150 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
152 /* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
154 unsigned int cfg : 2;
155 unsigned int dummy1 : 30;
156 } reg_iop_sw_cfg_rw_fifo_in1_owner;
157 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
158 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
160 /* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
162 unsigned int cfg : 2;
163 unsigned int dummy1 : 30;
164 } reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
165 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
166 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
168 /* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
170 unsigned int cfg : 2;
171 unsigned int dummy1 : 30;
172 } reg_iop_sw_cfg_rw_fifo_out0_owner;
173 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
174 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
176 /* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
178 unsigned int cfg : 2;
179 unsigned int dummy1 : 30;
180 } reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
181 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
182 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
184 /* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
186 unsigned int cfg : 2;
187 unsigned int dummy1 : 30;
188 } reg_iop_sw_cfg_rw_fifo_out1_owner;
189 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
190 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
192 /* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
194 unsigned int cfg : 2;
195 unsigned int dummy1 : 30;
196 } reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
197 #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
198 #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
200 /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
202 unsigned int cfg : 2;
203 unsigned int dummy1 : 30;
204 } reg_iop_sw_cfg_rw_sap_in_owner;
205 #define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
206 #define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
208 /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
210 unsigned int cfg : 2;
211 unsigned int dummy1 : 30;
212 } reg_iop_sw_cfg_rw_sap_out_owner;
213 #define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
214 #define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
216 /* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
218 unsigned int cfg : 2;
219 unsigned int dummy1 : 30;
220 } reg_iop_sw_cfg_rw_scrc_in0_owner;
221 #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
222 #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
224 /* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
226 unsigned int cfg : 2;
227 unsigned int dummy1 : 30;
228 } reg_iop_sw_cfg_rw_scrc_in1_owner;
229 #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
230 #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
232 /* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
234 unsigned int cfg : 2;
235 unsigned int dummy1 : 30;
236 } reg_iop_sw_cfg_rw_scrc_out0_owner;
237 #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
238 #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
240 /* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
242 unsigned int cfg : 2;
243 unsigned int dummy1 : 30;
244 } reg_iop_sw_cfg_rw_scrc_out1_owner;
245 #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
246 #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
248 /* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
250 unsigned int cfg : 2;
251 unsigned int dummy1 : 30;
252 } reg_iop_sw_cfg_rw_spu0_owner;
253 #define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
254 #define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
256 /* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
258 unsigned int cfg : 2;
259 unsigned int dummy1 : 30;
260 } reg_iop_sw_cfg_rw_spu1_owner;
261 #define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
262 #define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
264 /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
266 unsigned int cfg : 2;
267 unsigned int dummy1 : 30;
268 } reg_iop_sw_cfg_rw_timer_grp0_owner;
269 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
270 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
272 /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
274 unsigned int cfg : 2;
275 unsigned int dummy1 : 30;
276 } reg_iop_sw_cfg_rw_timer_grp1_owner;
277 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
278 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
280 /* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
282 unsigned int cfg : 2;
283 unsigned int dummy1 : 30;
284 } reg_iop_sw_cfg_rw_timer_grp2_owner;
285 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
286 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
288 /* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
290 unsigned int cfg : 2;
291 unsigned int dummy1 : 30;
292 } reg_iop_sw_cfg_rw_timer_grp3_owner;
293 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
294 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
296 /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
298 unsigned int cfg : 2;
299 unsigned int dummy1 : 30;
300 } reg_iop_sw_cfg_rw_trigger_grp0_owner;
301 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
302 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
304 /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
306 unsigned int cfg : 2;
307 unsigned int dummy1 : 30;
308 } reg_iop_sw_cfg_rw_trigger_grp1_owner;
309 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
310 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
312 /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
314 unsigned int cfg : 2;
315 unsigned int dummy1 : 30;
316 } reg_iop_sw_cfg_rw_trigger_grp2_owner;
317 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
318 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
320 /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
322 unsigned int cfg : 2;
323 unsigned int dummy1 : 30;
324 } reg_iop_sw_cfg_rw_trigger_grp3_owner;
325 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
326 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
328 /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
330 unsigned int cfg : 2;
331 unsigned int dummy1 : 30;
332 } reg_iop_sw_cfg_rw_trigger_grp4_owner;
333 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
334 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
336 /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
338 unsigned int cfg : 2;
339 unsigned int dummy1 : 30;
340 } reg_iop_sw_cfg_rw_trigger_grp5_owner;
341 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
342 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
344 /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
346 unsigned int cfg : 2;
347 unsigned int dummy1 : 30;
348 } reg_iop_sw_cfg_rw_trigger_grp6_owner;
349 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
350 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
352 /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
354 unsigned int cfg : 2;
355 unsigned int dummy1 : 30;
356 } reg_iop_sw_cfg_rw_trigger_grp7_owner;
357 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
358 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
360 /* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
362 unsigned int byte0 : 8;
363 unsigned int byte1 : 8;
364 unsigned int byte2 : 8;
365 unsigned int byte3 : 8;
366 } reg_iop_sw_cfg_rw_bus0_mask;
367 #define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
368 #define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
370 /* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
372 unsigned int byte0 : 1;
373 unsigned int byte1 : 1;
374 unsigned int byte2 : 1;
375 unsigned int byte3 : 1;
376 unsigned int dummy1 : 28;
377 } reg_iop_sw_cfg_rw_bus0_oe_mask;
378 #define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
379 #define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
381 /* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
383 unsigned int byte0 : 8;
384 unsigned int byte1 : 8;
385 unsigned int byte2 : 8;
386 unsigned int byte3 : 8;
387 } reg_iop_sw_cfg_rw_bus1_mask;
388 #define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
389 #define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
391 /* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
393 unsigned int byte0 : 1;
394 unsigned int byte1 : 1;
395 unsigned int byte2 : 1;
396 unsigned int byte3 : 1;
397 unsigned int dummy1 : 28;
398 } reg_iop_sw_cfg_rw_bus1_oe_mask;
399 #define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
400 #define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
402 /* Register rw_gio_mask, scope iop_sw_cfg, type rw */
404 unsigned int val : 32;
405 } reg_iop_sw_cfg_rw_gio_mask;
406 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
407 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
409 /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
411 unsigned int val : 32;
412 } reg_iop_sw_cfg_rw_gio_oe_mask;
413 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
414 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
416 /* Register rw_pinmapping, scope iop_sw_cfg, type rw */
418 unsigned int bus0_byte0 : 2;
419 unsigned int bus0_byte1 : 2;
420 unsigned int bus0_byte2 : 2;
421 unsigned int bus0_byte3 : 2;
422 unsigned int bus1_byte0 : 2;
423 unsigned int bus1_byte1 : 2;
424 unsigned int bus1_byte2 : 2;
425 unsigned int bus1_byte3 : 2;
426 unsigned int gio3_0 : 2;
427 unsigned int gio7_4 : 2;
428 unsigned int gio11_8 : 2;
429 unsigned int gio15_12 : 2;
430 unsigned int gio19_16 : 2;
431 unsigned int gio23_20 : 2;
432 unsigned int gio27_24 : 2;
433 unsigned int gio31_28 : 2;
434 } reg_iop_sw_cfg_rw_pinmapping;
435 #define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
436 #define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
438 /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
440 unsigned int bus0_lo : 3;
441 unsigned int bus0_hi : 3;
442 unsigned int bus0_lo_oe : 3;
443 unsigned int bus0_hi_oe : 3;
444 unsigned int bus1_lo : 3;
445 unsigned int bus1_hi : 3;
446 unsigned int bus1_lo_oe : 3;
447 unsigned int bus1_hi_oe : 3;
448 unsigned int dummy1 : 8;
449 } reg_iop_sw_cfg_rw_bus_out_cfg;
450 #define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
451 #define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
453 /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
455 unsigned int gio0 : 4;
456 unsigned int gio0_oe : 2;
457 unsigned int gio1 : 4;
458 unsigned int gio1_oe : 2;
459 unsigned int gio2 : 4;
460 unsigned int gio2_oe : 2;
461 unsigned int gio3 : 4;
462 unsigned int gio3_oe : 2;
463 unsigned int dummy1 : 8;
464 } reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
465 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
466 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
468 /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
470 unsigned int gio4 : 4;
471 unsigned int gio4_oe : 2;
472 unsigned int gio5 : 4;
473 unsigned int gio5_oe : 2;
474 unsigned int gio6 : 4;
475 unsigned int gio6_oe : 2;
476 unsigned int gio7 : 4;
477 unsigned int gio7_oe : 2;
478 unsigned int dummy1 : 8;
479 } reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
480 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
481 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
483 /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
485 unsigned int gio8 : 4;
486 unsigned int gio8_oe : 2;
487 unsigned int gio9 : 4;
488 unsigned int gio9_oe : 2;
489 unsigned int gio10 : 4;
490 unsigned int gio10_oe : 2;
491 unsigned int gio11 : 4;
492 unsigned int gio11_oe : 2;
493 unsigned int dummy1 : 8;
494 } reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
495 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
496 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
498 /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
500 unsigned int gio12 : 4;
501 unsigned int gio12_oe : 2;
502 unsigned int gio13 : 4;
503 unsigned int gio13_oe : 2;
504 unsigned int gio14 : 4;
505 unsigned int gio14_oe : 2;
506 unsigned int gio15 : 4;
507 unsigned int gio15_oe : 2;
508 unsigned int dummy1 : 8;
509 } reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
510 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
511 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
513 /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
515 unsigned int gio16 : 4;
516 unsigned int gio16_oe : 2;
517 unsigned int gio17 : 4;
518 unsigned int gio17_oe : 2;
519 unsigned int gio18 : 4;
520 unsigned int gio18_oe : 2;
521 unsigned int gio19 : 4;
522 unsigned int gio19_oe : 2;
523 unsigned int dummy1 : 8;
524 } reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
525 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
526 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
528 /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
530 unsigned int gio20 : 4;
531 unsigned int gio20_oe : 2;
532 unsigned int gio21 : 4;
533 unsigned int gio21_oe : 2;
534 unsigned int gio22 : 4;
535 unsigned int gio22_oe : 2;
536 unsigned int gio23 : 4;
537 unsigned int gio23_oe : 2;
538 unsigned int dummy1 : 8;
539 } reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
540 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
541 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
543 /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
545 unsigned int gio24 : 4;
546 unsigned int gio24_oe : 2;
547 unsigned int gio25 : 4;
548 unsigned int gio25_oe : 2;
549 unsigned int gio26 : 4;
550 unsigned int gio26_oe : 2;
551 unsigned int gio27 : 4;
552 unsigned int gio27_oe : 2;
553 unsigned int dummy1 : 8;
554 } reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
555 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
556 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
558 /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
560 unsigned int gio28 : 4;
561 unsigned int gio28_oe : 2;
562 unsigned int gio29 : 4;
563 unsigned int gio29_oe : 2;
564 unsigned int gio30 : 4;
565 unsigned int gio30_oe : 2;
566 unsigned int gio31 : 4;
567 unsigned int gio31_oe : 2;
568 unsigned int dummy1 : 8;
569 } reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
570 #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
571 #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
573 /* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
575 unsigned int bus0_in : 2;
576 unsigned int bus1_in : 2;
577 unsigned int dummy1 : 28;
578 } reg_iop_sw_cfg_rw_spu0_cfg;
579 #define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
580 #define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
582 /* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
584 unsigned int bus0_in : 2;
585 unsigned int bus1_in : 2;
586 unsigned int dummy1 : 28;
587 } reg_iop_sw_cfg_rw_spu1_cfg;
588 #define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
589 #define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
591 /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
593 unsigned int ext_clk : 3;
594 unsigned int tmr0_en : 1;
595 unsigned int tmr1_en : 1;
596 unsigned int tmr2_en : 1;
597 unsigned int tmr3_en : 1;
598 unsigned int tmr0_dis : 1;
599 unsigned int tmr1_dis : 1;
600 unsigned int tmr2_dis : 1;
601 unsigned int tmr3_dis : 1;
602 unsigned int dummy1 : 21;
603 } reg_iop_sw_cfg_rw_timer_grp0_cfg;
604 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
605 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
607 /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
609 unsigned int ext_clk : 3;
610 unsigned int tmr0_en : 1;
611 unsigned int tmr1_en : 1;
612 unsigned int tmr2_en : 1;
613 unsigned int tmr3_en : 1;
614 unsigned int tmr0_dis : 1;
615 unsigned int tmr1_dis : 1;
616 unsigned int tmr2_dis : 1;
617 unsigned int tmr3_dis : 1;
618 unsigned int dummy1 : 21;
619 } reg_iop_sw_cfg_rw_timer_grp1_cfg;
620 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
621 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
623 /* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
625 unsigned int ext_clk : 3;
626 unsigned int tmr0_en : 1;
627 unsigned int tmr1_en : 1;
628 unsigned int tmr2_en : 1;
629 unsigned int tmr3_en : 1;
630 unsigned int tmr0_dis : 1;
631 unsigned int tmr1_dis : 1;
632 unsigned int tmr2_dis : 1;
633 unsigned int tmr3_dis : 1;
634 unsigned int dummy1 : 21;
635 } reg_iop_sw_cfg_rw_timer_grp2_cfg;
636 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
637 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
639 /* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
641 unsigned int ext_clk : 3;
642 unsigned int tmr0_en : 1;
643 unsigned int tmr1_en : 1;
644 unsigned int tmr2_en : 1;
645 unsigned int tmr3_en : 1;
646 unsigned int tmr0_dis : 1;
647 unsigned int tmr1_dis : 1;
648 unsigned int tmr2_dis : 1;
649 unsigned int tmr3_dis : 1;
650 unsigned int dummy1 : 21;
651 } reg_iop_sw_cfg_rw_timer_grp3_cfg;
652 #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
653 #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
655 /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
657 unsigned int grp0_dis : 1;
658 unsigned int grp0_en : 1;
659 unsigned int grp1_dis : 1;
660 unsigned int grp1_en : 1;
661 unsigned int grp2_dis : 1;
662 unsigned int grp2_en : 1;
663 unsigned int grp3_dis : 1;
664 unsigned int grp3_en : 1;
665 unsigned int grp4_dis : 1;
666 unsigned int grp4_en : 1;
667 unsigned int grp5_dis : 1;
668 unsigned int grp5_en : 1;
669 unsigned int grp6_dis : 1;
670 unsigned int grp6_en : 1;
671 unsigned int grp7_dis : 1;
672 unsigned int grp7_en : 1;
673 unsigned int dummy1 : 16;
674 } reg_iop_sw_cfg_rw_trigger_grps_cfg;
675 #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
676 #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
678 /* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
680 unsigned int dmc0_usr : 1;
681 unsigned int out_strb : 5;
682 unsigned int in_src : 3;
683 unsigned int in_size : 3;
684 unsigned int in_last : 2;
685 unsigned int in_strb : 4;
686 unsigned int out_src : 1;
687 unsigned int dummy1 : 13;
688 } reg_iop_sw_cfg_rw_pdp0_cfg;
689 #define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
690 #define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
692 /* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
694 unsigned int dmc1_usr : 1;
695 unsigned int out_strb : 5;
696 unsigned int in_src : 3;
697 unsigned int in_size : 3;
698 unsigned int in_last : 2;
699 unsigned int in_strb : 4;
700 unsigned int out_src : 1;
701 unsigned int dummy1 : 13;
702 } reg_iop_sw_cfg_rw_pdp1_cfg;
703 #define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
704 #define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
706 /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
708 unsigned int sdp_out0_strb : 3;
709 unsigned int sdp_out1_strb : 3;
710 unsigned int sdp_in0_data : 3;
711 unsigned int sdp_in0_last : 2;
712 unsigned int sdp_in0_strb : 3;
713 unsigned int sdp_in1_data : 3;
714 unsigned int sdp_in1_last : 2;
715 unsigned int sdp_in1_strb : 3;
716 unsigned int dummy1 : 10;
717 } reg_iop_sw_cfg_rw_sdp_cfg;
718 #define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
719 #define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
724 regk_iop_sw_cfg_a = 0x00000001,
725 regk_iop_sw_cfg_b = 0x00000002,
726 regk_iop_sw_cfg_bus0 = 0x00000000,
727 regk_iop_sw_cfg_bus0_rot16 = 0x00000004,
728 regk_iop_sw_cfg_bus0_rot24 = 0x00000006,
729 regk_iop_sw_cfg_bus0_rot8 = 0x00000002,
730 regk_iop_sw_cfg_bus1 = 0x00000001,
731 regk_iop_sw_cfg_bus1_rot16 = 0x00000005,
732 regk_iop_sw_cfg_bus1_rot24 = 0x00000007,
733 regk_iop_sw_cfg_bus1_rot8 = 0x00000003,
734 regk_iop_sw_cfg_clk12 = 0x00000000,
735 regk_iop_sw_cfg_cpu = 0x00000000,
736 regk_iop_sw_cfg_dmc0 = 0x00000000,
737 regk_iop_sw_cfg_dmc1 = 0x00000001,
738 regk_iop_sw_cfg_gated_clk0 = 0x00000010,
739 regk_iop_sw_cfg_gated_clk1 = 0x00000011,
740 regk_iop_sw_cfg_gated_clk2 = 0x00000012,
741 regk_iop_sw_cfg_gated_clk3 = 0x00000013,
742 regk_iop_sw_cfg_gio0 = 0x00000004,
743 regk_iop_sw_cfg_gio1 = 0x00000001,
744 regk_iop_sw_cfg_gio2 = 0x00000005,
745 regk_iop_sw_cfg_gio3 = 0x00000002,
746 regk_iop_sw_cfg_gio4 = 0x00000006,
747 regk_iop_sw_cfg_gio5 = 0x00000003,
748 regk_iop_sw_cfg_gio6 = 0x00000007,
749 regk_iop_sw_cfg_gio7 = 0x00000004,
750 regk_iop_sw_cfg_gio_in0 = 0x00000000,
751 regk_iop_sw_cfg_gio_in1 = 0x00000001,
752 regk_iop_sw_cfg_gio_in10 = 0x00000002,
753 regk_iop_sw_cfg_gio_in11 = 0x00000003,
754 regk_iop_sw_cfg_gio_in14 = 0x00000004,
755 regk_iop_sw_cfg_gio_in15 = 0x00000005,
756 regk_iop_sw_cfg_gio_in18 = 0x00000002,
757 regk_iop_sw_cfg_gio_in19 = 0x00000003,
758 regk_iop_sw_cfg_gio_in20 = 0x00000004,
759 regk_iop_sw_cfg_gio_in21 = 0x00000005,
760 regk_iop_sw_cfg_gio_in26 = 0x00000006,
761 regk_iop_sw_cfg_gio_in27 = 0x00000007,
762 regk_iop_sw_cfg_gio_in28 = 0x00000006,
763 regk_iop_sw_cfg_gio_in29 = 0x00000007,
764 regk_iop_sw_cfg_gio_in4 = 0x00000000,
765 regk_iop_sw_cfg_gio_in5 = 0x00000001,
766 regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
767 regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001,
768 regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002,
769 regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003,
770 regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002,
771 regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003,
772 regk_iop_sw_cfg_mpu = 0x00000001,
773 regk_iop_sw_cfg_none = 0x00000000,
774 regk_iop_sw_cfg_par0 = 0x00000000,
775 regk_iop_sw_cfg_par1 = 0x00000001,
776 regk_iop_sw_cfg_pdp_out0 = 0x00000002,
777 regk_iop_sw_cfg_pdp_out0_hi = 0x00000001,
778 regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005,
779 regk_iop_sw_cfg_pdp_out0_lo = 0x00000000,
780 regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004,
781 regk_iop_sw_cfg_pdp_out1 = 0x00000003,
782 regk_iop_sw_cfg_pdp_out1_hi = 0x00000003,
783 regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005,
784 regk_iop_sw_cfg_pdp_out1_lo = 0x00000002,
785 regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004,
786 regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000,
787 regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000,
788 regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000,
789 regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000,
790 regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
791 regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
792 regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
793 regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
794 regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
795 regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
796 regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
797 regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
798 regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
799 regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
800 regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
801 regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
802 regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
803 regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
804 regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
805 regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
806 regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
807 regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
808 regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
809 regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
810 regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
811 regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
812 regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
813 regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
814 regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
815 regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000,
816 regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000,
817 regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555,
818 regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
819 regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
820 regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
821 regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
822 regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
823 regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
824 regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
825 regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000,
826 regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000,
827 regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000,
828 regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000,
829 regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
830 regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
831 regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
832 regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
833 regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
834 regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
835 regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
836 regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
837 regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
838 regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
839 regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
840 regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
841 regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
842 regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
843 regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
844 regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
845 regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
846 regk_iop_sw_cfg_sdp_out0 = 0x00000008,
847 regk_iop_sw_cfg_sdp_out1 = 0x00000009,
848 regk_iop_sw_cfg_size16 = 0x00000002,
849 regk_iop_sw_cfg_size24 = 0x00000003,
850 regk_iop_sw_cfg_size32 = 0x00000004,
851 regk_iop_sw_cfg_size8 = 0x00000001,
852 regk_iop_sw_cfg_spu0 = 0x00000002,
853 regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006,
854 regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006,
855 regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007,
856 regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007,
857 regk_iop_sw_cfg_spu0_g0 = 0x0000000e,
858 regk_iop_sw_cfg_spu0_g1 = 0x0000000e,
859 regk_iop_sw_cfg_spu0_g2 = 0x0000000e,
860 regk_iop_sw_cfg_spu0_g3 = 0x0000000e,
861 regk_iop_sw_cfg_spu0_g4 = 0x0000000e,
862 regk_iop_sw_cfg_spu0_g5 = 0x0000000e,
863 regk_iop_sw_cfg_spu0_g6 = 0x0000000e,
864 regk_iop_sw_cfg_spu0_g7 = 0x0000000e,
865 regk_iop_sw_cfg_spu0_gio0 = 0x00000000,
866 regk_iop_sw_cfg_spu0_gio1 = 0x00000001,
867 regk_iop_sw_cfg_spu0_gio2 = 0x00000000,
868 regk_iop_sw_cfg_spu0_gio5 = 0x00000005,
869 regk_iop_sw_cfg_spu0_gio6 = 0x00000006,
870 regk_iop_sw_cfg_spu0_gio7 = 0x00000007,
871 regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008,
872 regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009,
873 regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a,
874 regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b,
875 regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c,
876 regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d,
877 regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e,
878 regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f,
879 regk_iop_sw_cfg_spu0_gioout0 = 0x00000000,
880 regk_iop_sw_cfg_spu0_gioout1 = 0x00000000,
881 regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e,
882 regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e,
883 regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e,
884 regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e,
885 regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e,
886 regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e,
887 regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e,
888 regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e,
889 regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e,
890 regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e,
891 regk_iop_sw_cfg_spu0_gioout2 = 0x00000002,
892 regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e,
893 regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e,
894 regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e,
895 regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e,
896 regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e,
897 regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e,
898 regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e,
899 regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e,
900 regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e,
901 regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e,
902 regk_iop_sw_cfg_spu0_gioout3 = 0x00000002,
903 regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e,
904 regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e,
905 regk_iop_sw_cfg_spu0_gioout4 = 0x00000004,
906 regk_iop_sw_cfg_spu0_gioout5 = 0x00000004,
907 regk_iop_sw_cfg_spu0_gioout6 = 0x00000006,
908 regk_iop_sw_cfg_spu0_gioout7 = 0x00000006,
909 regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e,
910 regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e,
911 regk_iop_sw_cfg_spu1 = 0x00000003,
912 regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006,
913 regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006,
914 regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007,
915 regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007,
916 regk_iop_sw_cfg_spu1_g0 = 0x0000000f,
917 regk_iop_sw_cfg_spu1_g1 = 0x0000000f,
918 regk_iop_sw_cfg_spu1_g2 = 0x0000000f,
919 regk_iop_sw_cfg_spu1_g3 = 0x0000000f,
920 regk_iop_sw_cfg_spu1_g4 = 0x0000000f,
921 regk_iop_sw_cfg_spu1_g5 = 0x0000000f,
922 regk_iop_sw_cfg_spu1_g6 = 0x0000000f,
923 regk_iop_sw_cfg_spu1_g7 = 0x0000000f,
924 regk_iop_sw_cfg_spu1_gio0 = 0x00000002,
925 regk_iop_sw_cfg_spu1_gio1 = 0x00000003,
926 regk_iop_sw_cfg_spu1_gio2 = 0x00000002,
927 regk_iop_sw_cfg_spu1_gio5 = 0x00000005,
928 regk_iop_sw_cfg_spu1_gio6 = 0x00000006,
929 regk_iop_sw_cfg_spu1_gio7 = 0x00000007,
930 regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008,
931 regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009,
932 regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a,
933 regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b,
934 regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c,
935 regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d,
936 regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e,
937 regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f,
938 regk_iop_sw_cfg_spu1_gioout0 = 0x00000001,
939 regk_iop_sw_cfg_spu1_gioout1 = 0x00000001,
940 regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f,
941 regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f,
942 regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f,
943 regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f,
944 regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f,
945 regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f,
946 regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f,
947 regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f,
948 regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f,
949 regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f,
950 regk_iop_sw_cfg_spu1_gioout2 = 0x00000003,
951 regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f,
952 regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f,
953 regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f,
954 regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f,
955 regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f,
956 regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f,
957 regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f,
958 regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f,
959 regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f,
960 regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f,
961 regk_iop_sw_cfg_spu1_gioout3 = 0x00000003,
962 regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f,
963 regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f,
964 regk_iop_sw_cfg_spu1_gioout4 = 0x00000005,
965 regk_iop_sw_cfg_spu1_gioout5 = 0x00000005,
966 regk_iop_sw_cfg_spu1_gioout6 = 0x00000007,
967 regk_iop_sw_cfg_spu1_gioout7 = 0x00000007,
968 regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f,
969 regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f,
970 regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
971 regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
972 regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001,
973 regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
974 regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003,
975 regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002,
976 regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003,
977 regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002,
978 regk_iop_sw_cfg_timer_grp0 = 0x00000000,
979 regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
980 regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a,
981 regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a,
982 regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a,
983 regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a,
984 regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004,
985 regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004,
986 regk_iop_sw_cfg_timer_grp1 = 0x00000000,
987 regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
988 regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b,
989 regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b,
990 regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b,
991 regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b,
992 regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005,
993 regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005,
994 regk_iop_sw_cfg_timer_grp2 = 0x00000000,
995 regk_iop_sw_cfg_timer_grp2_rot = 0x00000001,
996 regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c,
997 regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c,
998 regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c,
999 regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c,
1000 regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006,
1001 regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006,
1002 regk_iop_sw_cfg_timer_grp3 = 0x00000000,
1003 regk_iop_sw_cfg_timer_grp3_rot = 0x00000001,
1004 regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d,
1005 regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d,
1006 regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d,
1007 regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d,
1008 regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007,
1009 regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007,
1010 regk_iop_sw_cfg_trig0_0 = 0x00000000,
1011 regk_iop_sw_cfg_trig0_1 = 0x00000000,
1012 regk_iop_sw_cfg_trig0_2 = 0x00000000,
1013 regk_iop_sw_cfg_trig0_3 = 0x00000000,
1014 regk_iop_sw_cfg_trig1_0 = 0x00000000,
1015 regk_iop_sw_cfg_trig1_1 = 0x00000000,
1016 regk_iop_sw_cfg_trig1_2 = 0x00000000,
1017 regk_iop_sw_cfg_trig1_3 = 0x00000000,
1018 regk_iop_sw_cfg_trig2_0 = 0x00000000,
1019 regk_iop_sw_cfg_trig2_1 = 0x00000000,
1020 regk_iop_sw_cfg_trig2_2 = 0x00000000,
1021 regk_iop_sw_cfg_trig2_3 = 0x00000000,
1022 regk_iop_sw_cfg_trig3_0 = 0x00000000,
1023 regk_iop_sw_cfg_trig3_1 = 0x00000000,
1024 regk_iop_sw_cfg_trig3_2 = 0x00000000,
1025 regk_iop_sw_cfg_trig3_3 = 0x00000000,
1026 regk_iop_sw_cfg_trig4_0 = 0x00000001,
1027 regk_iop_sw_cfg_trig4_1 = 0x00000001,
1028 regk_iop_sw_cfg_trig4_2 = 0x00000001,
1029 regk_iop_sw_cfg_trig4_3 = 0x00000001,
1030 regk_iop_sw_cfg_trig5_0 = 0x00000001,
1031 regk_iop_sw_cfg_trig5_1 = 0x00000001,
1032 regk_iop_sw_cfg_trig5_2 = 0x00000001,
1033 regk_iop_sw_cfg_trig5_3 = 0x00000001,
1034 regk_iop_sw_cfg_trig6_0 = 0x00000001,
1035 regk_iop_sw_cfg_trig6_1 = 0x00000001,
1036 regk_iop_sw_cfg_trig6_2 = 0x00000001,
1037 regk_iop_sw_cfg_trig6_3 = 0x00000001,
1038 regk_iop_sw_cfg_trig7_0 = 0x00000001,
1039 regk_iop_sw_cfg_trig7_1 = 0x00000001,
1040 regk_iop_sw_cfg_trig7_2 = 0x00000001,
1041 regk_iop_sw_cfg_trig7_3 = 0x00000001
1043 #endif /* __iop_sw_cfg_defs_h */