1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_fifo_out_extra_defs_h
3 #define __iop_fifo_out_extra_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
9 * last modfied: Mon Apr 11 16:10:10 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
12 * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_fifo_out_extra */
88 /* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
89 typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
90 #define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
92 /* Register r_rd_data, scope iop_fifo_out_extra, type r */
93 typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
94 #define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
96 /* Register r_stat, scope iop_fifo_out_extra, type r */
98 unsigned int avail_bytes : 4;
99 unsigned int last : 8;
100 unsigned int dif_in_en : 1;
101 unsigned int dif_out_en : 1;
102 unsigned int zero_data_last : 1;
103 unsigned int dummy1 : 17;
104 } reg_iop_fifo_out_extra_r_stat;
105 #define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
107 /* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
108 typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
109 #define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
110 #define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
112 /* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
114 unsigned int urun : 1;
115 unsigned int last_data : 1;
116 unsigned int dav : 1;
117 unsigned int free : 1;
118 unsigned int orun : 1;
119 unsigned int dummy1 : 27;
120 } reg_iop_fifo_out_extra_rw_intr_mask;
121 #define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
122 #define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
124 /* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
126 unsigned int urun : 1;
127 unsigned int last_data : 1;
128 unsigned int dav : 1;
129 unsigned int free : 1;
130 unsigned int orun : 1;
131 unsigned int dummy1 : 27;
132 } reg_iop_fifo_out_extra_rw_ack_intr;
133 #define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
134 #define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
136 /* Register r_intr, scope iop_fifo_out_extra, type r */
138 unsigned int urun : 1;
139 unsigned int last_data : 1;
140 unsigned int dav : 1;
141 unsigned int free : 1;
142 unsigned int orun : 1;
143 unsigned int dummy1 : 27;
144 } reg_iop_fifo_out_extra_r_intr;
145 #define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
147 /* Register r_masked_intr, scope iop_fifo_out_extra, type r */
149 unsigned int urun : 1;
150 unsigned int last_data : 1;
151 unsigned int dav : 1;
152 unsigned int free : 1;
153 unsigned int orun : 1;
154 unsigned int dummy1 : 27;
155 } reg_iop_fifo_out_extra_r_masked_intr;
156 #define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
161 regk_iop_fifo_out_extra_no = 0x00000000,
162 regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
163 regk_iop_fifo_out_extra_yes = 0x00000001
165 #endif /* __iop_fifo_out_extra_defs_h */