1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_fifo_out_defs_h
3 #define __iop_fifo_out_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_fifo_out.r
9 * last modfied: Mon Apr 11 16:10:09 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
12 * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_fifo_out */
88 /* Register rw_cfg, scope iop_fifo_out, type rw */
90 unsigned int free_lim : 3;
91 unsigned int byte_order : 2;
92 unsigned int trig : 2;
93 unsigned int last_dis_dif_in : 1;
94 unsigned int mode : 2;
95 unsigned int delay_out_last : 1;
96 unsigned int last_dis_dif_out : 1;
97 unsigned int dummy1 : 20;
98 } reg_iop_fifo_out_rw_cfg;
99 #define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
100 #define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
102 /* Register rw_ctrl, scope iop_fifo_out, type rw */
104 unsigned int dif_in_en : 1;
105 unsigned int dif_out_en : 1;
106 unsigned int dummy1 : 30;
107 } reg_iop_fifo_out_rw_ctrl;
108 #define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
109 #define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
111 /* Register r_stat, scope iop_fifo_out, type r */
113 unsigned int avail_bytes : 4;
114 unsigned int last : 8;
115 unsigned int dif_in_en : 1;
116 unsigned int dif_out_en : 1;
117 unsigned int zero_data_last : 1;
118 unsigned int dummy1 : 17;
119 } reg_iop_fifo_out_r_stat;
120 #define REG_RD_ADDR_iop_fifo_out_r_stat 8
122 /* Register rw_wr1byte, scope iop_fifo_out, type rw */
124 unsigned int data : 8;
125 unsigned int dummy1 : 24;
126 } reg_iop_fifo_out_rw_wr1byte;
127 #define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
128 #define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
130 /* Register rw_wr2byte, scope iop_fifo_out, type rw */
132 unsigned int data : 16;
133 unsigned int dummy1 : 16;
134 } reg_iop_fifo_out_rw_wr2byte;
135 #define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
136 #define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
138 /* Register rw_wr3byte, scope iop_fifo_out, type rw */
140 unsigned int data : 24;
141 unsigned int dummy1 : 8;
142 } reg_iop_fifo_out_rw_wr3byte;
143 #define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
144 #define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
146 /* Register rw_wr4byte, scope iop_fifo_out, type rw */
148 unsigned int data : 32;
149 } reg_iop_fifo_out_rw_wr4byte;
150 #define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
151 #define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
153 /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
155 unsigned int data : 8;
156 unsigned int dummy1 : 24;
157 } reg_iop_fifo_out_rw_wr1byte_last;
158 #define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
159 #define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
161 /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
163 unsigned int data : 16;
164 unsigned int dummy1 : 16;
165 } reg_iop_fifo_out_rw_wr2byte_last;
166 #define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
167 #define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
169 /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
171 unsigned int data : 24;
172 unsigned int dummy1 : 8;
173 } reg_iop_fifo_out_rw_wr3byte_last;
174 #define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
175 #define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
177 /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
179 unsigned int data : 32;
180 } reg_iop_fifo_out_rw_wr4byte_last;
181 #define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
182 #define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
184 /* Register rw_set_last, scope iop_fifo_out, type rw */
185 typedef unsigned int reg_iop_fifo_out_rw_set_last;
186 #define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
187 #define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
189 /* Register rs_rd_data, scope iop_fifo_out, type rs */
190 typedef unsigned int reg_iop_fifo_out_rs_rd_data;
191 #define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
193 /* Register r_rd_data, scope iop_fifo_out, type r */
194 typedef unsigned int reg_iop_fifo_out_r_rd_data;
195 #define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
197 /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
198 typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
199 #define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
200 #define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
202 /* Register rw_intr_mask, scope iop_fifo_out, type rw */
204 unsigned int urun : 1;
205 unsigned int last_data : 1;
206 unsigned int dav : 1;
207 unsigned int free : 1;
208 unsigned int orun : 1;
209 unsigned int dummy1 : 27;
210 } reg_iop_fifo_out_rw_intr_mask;
211 #define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
212 #define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
214 /* Register rw_ack_intr, scope iop_fifo_out, type rw */
216 unsigned int urun : 1;
217 unsigned int last_data : 1;
218 unsigned int dav : 1;
219 unsigned int free : 1;
220 unsigned int orun : 1;
221 unsigned int dummy1 : 27;
222 } reg_iop_fifo_out_rw_ack_intr;
223 #define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
224 #define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
226 /* Register r_intr, scope iop_fifo_out, type r */
228 unsigned int urun : 1;
229 unsigned int last_data : 1;
230 unsigned int dav : 1;
231 unsigned int free : 1;
232 unsigned int orun : 1;
233 unsigned int dummy1 : 27;
234 } reg_iop_fifo_out_r_intr;
235 #define REG_RD_ADDR_iop_fifo_out_r_intr 68
237 /* Register r_masked_intr, scope iop_fifo_out, type r */
239 unsigned int urun : 1;
240 unsigned int last_data : 1;
241 unsigned int dav : 1;
242 unsigned int free : 1;
243 unsigned int orun : 1;
244 unsigned int dummy1 : 27;
245 } reg_iop_fifo_out_r_masked_intr;
246 #define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
251 regk_iop_fifo_out_hi = 0x00000000,
252 regk_iop_fifo_out_neg = 0x00000002,
253 regk_iop_fifo_out_no = 0x00000000,
254 regk_iop_fifo_out_order16 = 0x00000001,
255 regk_iop_fifo_out_order24 = 0x00000002,
256 regk_iop_fifo_out_order32 = 0x00000003,
257 regk_iop_fifo_out_order8 = 0x00000000,
258 regk_iop_fifo_out_pos = 0x00000001,
259 regk_iop_fifo_out_pos_neg = 0x00000003,
260 regk_iop_fifo_out_rw_cfg_default = 0x00000024,
261 regk_iop_fifo_out_rw_ctrl_default = 0x00000000,
262 regk_iop_fifo_out_rw_intr_mask_default = 0x00000000,
263 regk_iop_fifo_out_rw_set_last_default = 0x00000000,
264 regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
265 regk_iop_fifo_out_rw_wr1byte_default = 0x00000000,
266 regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
267 regk_iop_fifo_out_rw_wr2byte_default = 0x00000000,
268 regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
269 regk_iop_fifo_out_rw_wr3byte_default = 0x00000000,
270 regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
271 regk_iop_fifo_out_rw_wr4byte_default = 0x00000000,
272 regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
273 regk_iop_fifo_out_size16 = 0x00000002,
274 regk_iop_fifo_out_size24 = 0x00000001,
275 regk_iop_fifo_out_size32 = 0x00000000,
276 regk_iop_fifo_out_size8 = 0x00000003,
277 regk_iop_fifo_out_yes = 0x00000001
279 #endif /* __iop_fifo_out_defs_h */